Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/cacheops.h> |
| 10 | #include <asm/mipsregs.h> |
| 11 | |
Paul Burton | 8cb4817 | 2016-09-21 11:18:48 +0100 | [diff] [blame^] | 12 | DECLARE_GLOBAL_DATA_PTR; |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 13 | |
Paul Burton | 8cb4817 | 2016-09-21 11:18:48 +0100 | [diff] [blame^] | 14 | void mips_cache_probe(void) |
| 15 | { |
| 16 | #ifdef CONFIG_SYS_CACHE_SIZE_AUTO |
| 17 | unsigned long conf1, il, dl; |
Paul Burton | 3722862 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 18 | |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 19 | conf1 = read_c0_config1(); |
Paul Burton | 8cb4817 | 2016-09-21 11:18:48 +0100 | [diff] [blame^] | 20 | |
Daniel Schwierzeck | a3ab2ae | 2016-01-12 21:48:26 +0100 | [diff] [blame] | 21 | il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF; |
Paul Burton | 8cb4817 | 2016-09-21 11:18:48 +0100 | [diff] [blame^] | 22 | dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; |
| 23 | |
| 24 | gd->arch.l1i_line_size = il ? (2 << il) : 0; |
| 25 | gd->arch.l1d_line_size = dl ? (2 << dl) : 0; |
| 26 | #endif |
| 27 | } |
| 28 | |
| 29 | static inline unsigned long icache_line_size(void) |
| 30 | { |
| 31 | #ifdef CONFIG_SYS_CACHE_SIZE_AUTO |
| 32 | return gd->arch.l1i_line_size; |
| 33 | #else |
| 34 | return CONFIG_SYS_ICACHE_LINE_SIZE; |
| 35 | #endif |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 36 | } |
| 37 | |
| 38 | static inline unsigned long dcache_line_size(void) |
| 39 | { |
Paul Burton | 8cb4817 | 2016-09-21 11:18:48 +0100 | [diff] [blame^] | 40 | #ifdef CONFIG_SYS_CACHE_SIZE_AUTO |
| 41 | return gd->arch.l1d_line_size; |
| 42 | #else |
| 43 | return CONFIG_SYS_DCACHE_LINE_SIZE; |
| 44 | #endif |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 45 | } |
| 46 | |
Paul Burton | fb64cda | 2016-05-27 14:28:06 +0100 | [diff] [blame] | 47 | #define cache_loop(start, end, lsize, ops...) do { \ |
| 48 | const void *addr = (const void *)(start & ~(lsize - 1)); \ |
| 49 | const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \ |
| 50 | const unsigned int cache_ops[] = { ops }; \ |
| 51 | unsigned int i; \ |
| 52 | \ |
| 53 | for (; addr <= aend; addr += lsize) { \ |
| 54 | for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \ |
| 55 | mips_cache(cache_ops[i], addr); \ |
| 56 | } \ |
| 57 | } while (0) |
| 58 | |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 59 | void flush_cache(ulong start_addr, ulong size) |
| 60 | { |
| 61 | unsigned long ilsize = icache_line_size(); |
| 62 | unsigned long dlsize = dcache_line_size(); |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 63 | |
| 64 | /* aend will be miscalculated when size is zero, so we return here */ |
| 65 | if (size == 0) |
| 66 | return; |
| 67 | |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 68 | if (ilsize == dlsize) { |
| 69 | /* flush I-cache & D-cache simultaneously */ |
Paul Burton | fb64cda | 2016-05-27 14:28:06 +0100 | [diff] [blame] | 70 | cache_loop(start_addr, start_addr + size, ilsize, |
| 71 | HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 72 | return; |
| 73 | } |
| 74 | |
| 75 | /* flush D-cache */ |
Paul Burton | fb64cda | 2016-05-27 14:28:06 +0100 | [diff] [blame] | 76 | cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 77 | |
| 78 | /* flush I-cache */ |
Paul Burton | fb64cda | 2016-05-27 14:28:06 +0100 | [diff] [blame] | 79 | cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | void flush_dcache_range(ulong start_addr, ulong stop) |
| 83 | { |
| 84 | unsigned long lsize = dcache_line_size(); |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 85 | |
Marek Vasut | fbb0de0 | 2016-01-27 03:13:59 +0100 | [diff] [blame] | 86 | /* aend will be miscalculated when size is zero, so we return here */ |
| 87 | if (start_addr == stop) |
| 88 | return; |
| 89 | |
Paul Burton | fb64cda | 2016-05-27 14:28:06 +0100 | [diff] [blame] | 90 | cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | void invalidate_dcache_range(ulong start_addr, ulong stop) |
| 94 | { |
| 95 | unsigned long lsize = dcache_line_size(); |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 96 | |
Marek Vasut | fbb0de0 | 2016-01-27 03:13:59 +0100 | [diff] [blame] | 97 | /* aend will be miscalculated when size is zero, so we return here */ |
| 98 | if (start_addr == stop) |
| 99 | return; |
| 100 | |
Paul Burton | a95800e | 2016-06-09 13:09:51 +0100 | [diff] [blame] | 101 | cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); |
Paul Burton | 30374f9 | 2015-01-29 01:27:57 +0000 | [diff] [blame] | 102 | } |