| Marty E. Plummer | 8e2e601 | 2019-01-05 20:12:08 -0600 | [diff] [blame^] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_ROCKCHIP=y |
| 3 | CONFIG_SYS_TEXT_BASE=0x00100000 |
| 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 5 | CONFIG_ROCKCHIP_RK3288=y |
| 6 | # CONFIG_SPL_MMC_SUPPORT is not set |
| 7 | CONFIG_TARGET_CHROMEBOOK_SPEEDY=y |
| 8 | CONFIG_DEBUG_UART_BASE=0xff690000 |
| 9 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| 10 | CONFIG_SPL_STACK_R_ADDR=0x80000 |
| 11 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| 12 | CONFIG_SPL_SPI_SUPPORT=y |
| 13 | CONFIG_DEBUG_UART=y |
| 14 | CONFIG_NR_DRAM_BANKS=1 |
| 15 | # CONFIG_ANDROID_BOOT_IMAGE is not set |
| 16 | CONFIG_SILENT_CONSOLE=y |
| 17 | CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" |
| 18 | # CONFIG_DISPLAY_CPUINFO is not set |
| 19 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| 20 | CONFIG_BOARD_EARLY_INIT_F=y |
| 21 | CONFIG_SPL_STACK_R=y |
| 22 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 |
| 23 | CONFIG_SPL_SPI_LOAD=y |
| 24 | CONFIG_CMD_GPIO=y |
| 25 | CONFIG_CMD_GPT=y |
| 26 | CONFIG_CMD_I2C=y |
| 27 | CONFIG_CMD_MMC=y |
| 28 | CONFIG_CMD_SF=y |
| 29 | CONFIG_CMD_SF_TEST=y |
| 30 | CONFIG_CMD_SPI=y |
| 31 | CONFIG_CMD_USB=y |
| 32 | # CONFIG_CMD_SETEXPR is not set |
| 33 | CONFIG_CMD_CACHE=y |
| 34 | CONFIG_CMD_TIME=y |
| 35 | CONFIG_CMD_PMIC=y |
| 36 | CONFIG_CMD_REGULATOR=y |
| 37 | # CONFIG_SPL_DOS_PARTITION is not set |
| 38 | # CONFIG_SPL_EFI_PARTITION is not set |
| 39 | CONFIG_SPL_PARTITION_UUIDS=y |
| 40 | CONFIG_SPL_OF_CONTROL=y |
| 41 | CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" |
| 42 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 43 | CONFIG_SPL_OF_PLATDATA=y |
| 44 | CONFIG_REGMAP=y |
| 45 | CONFIG_SPL_REGMAP=y |
| 46 | CONFIG_SYSCON=y |
| 47 | CONFIG_SPL_SYSCON=y |
| 48 | # CONFIG_SPL_SIMPLE_BUS is not set |
| 49 | CONFIG_CLK=y |
| 50 | CONFIG_SPL_CLK=y |
| 51 | CONFIG_FASTBOOT_FLASH=y |
| 52 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
| 53 | CONFIG_FASTBOOT_CMD_OEM_FORMAT=y |
| 54 | CONFIG_ROCKCHIP_GPIO=y |
| 55 | CONFIG_I2C_CROS_EC_TUNNEL=y |
| 56 | CONFIG_SYS_I2C_ROCKCHIP=y |
| 57 | CONFIG_I2C_MUX=y |
| 58 | CONFIG_DM_KEYBOARD=y |
| 59 | CONFIG_CROS_EC_KEYB=y |
| 60 | CONFIG_CROS_EC=y |
| 61 | CONFIG_CROS_EC_SPI=y |
| 62 | CONFIG_PWRSEQ=y |
| 63 | CONFIG_MMC_DW=y |
| 64 | CONFIG_MMC_DW_ROCKCHIP=y |
| 65 | CONFIG_PINCTRL=y |
| 66 | CONFIG_SPL_PINCTRL=y |
| 67 | # CONFIG_SPL_PINCTRL_FULL is not set |
| 68 | CONFIG_PINCTRL_ROCKCHIP_RK3288=y |
| 69 | CONFIG_DM_PMIC=y |
| 70 | # CONFIG_SPL_PMIC_CHILDREN is not set |
| 71 | CONFIG_PMIC_RK8XX=y |
| 72 | CONFIG_DM_REGULATOR_FIXED=y |
| 73 | CONFIG_REGULATOR_RK8XX=y |
| 74 | CONFIG_PWM_ROCKCHIP=y |
| 75 | CONFIG_RAM=y |
| 76 | CONFIG_SPL_RAM=y |
| 77 | CONFIG_DEBUG_UART_SHIFT=2 |
| 78 | CONFIG_ROCKCHIP_SERIAL=y |
| 79 | CONFIG_ROCKCHIP_SPI=y |
| 80 | CONFIG_SYSRESET=y |
| 81 | CONFIG_USB=y |
| 82 | CONFIG_ROCKCHIP_USB2_PHY=y |
| 83 | CONFIG_USB_STORAGE=y |
| 84 | CONFIG_USB_GADGET=y |
| 85 | CONFIG_USB_GADGET_MANUFACTURER="Rockchip" |
| 86 | CONFIG_USB_GADGET_VENDOR_NUM=0x2207 |
| 87 | CONFIG_USB_GADGET_PRODUCT_NUM=0x320a |
| 88 | CONFIG_USB_GADGET_DWC2_OTG=y |
| 89 | CONFIG_USB_FUNCTION_MASS_STORAGE=y |
| 90 | CONFIG_DM_VIDEO=y |
| 91 | CONFIG_CONSOLE_TRUETYPE=y |
| 92 | CONFIG_DISPLAY=y |
| 93 | CONFIG_VIDEO_ROCKCHIP=y |
| 94 | CONFIG_DISPLAY_ROCKCHIP_EDP=y |
| 95 | CONFIG_DISPLAY_ROCKCHIP_HDMI=y |
| 96 | # CONFIG_USE_PRIVATE_LIBGCC is not set |
| 97 | CONFIG_USE_TINY_PRINTF=y |
| 98 | CONFIG_CMD_DHRYSTONE=y |
| 99 | CONFIG_ERRNO_STR=y |
| 100 | # CONFIG_SPL_OF_LIBFDT is not set |