blob: 0e93836c0cc23f6eec940f459e1486c8bedb9541 [file] [log] [blame]
Piotr Wilczek4d6c9672013-09-20 15:01:27 +02001/*
2 * Copyright (C) 2013 Samsung Electronics
3 * Sanghee Kim <sh0130.kim@samsung.com>
4 * Piotr Wilczek <p.wilczek@samsung.com>
5 *
6 * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18#define CONFIG_SAMSUNG /* in a SAMSUNG core */
19#define CONFIG_S5P /* which is in a S5P Family */
20#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
21#define CONFIG_TIZEN /* TIZEN lib */
22
23#define PLATFORM_NO_UNALIGNED
24
25#include <asm/arch/cpu.h> /* get chip and board defs */
26
27#define CONFIG_ARCH_CPU_INIT
28#define CONFIG_DISPLAY_CPUINFO
29#define CONFIG_DISPLAY_BOARDINFO
30
31#define CONFIG_SKIP_LOWLEVEL_INIT
32
33#define CONFIG_SYS_CACHELINE_SIZE 32
34
35#ifndef CONFIG_SYS_L2CACHE_OFF
36#define CONFIG_SYS_L2_PL310
37#define CONFIG_SYS_PL310_BASE 0x10502000
38#endif
39
40#define CONFIG_NR_DRAM_BANKS 4
41#define PHYS_SDRAM_1 0x40000000 /* LDDDR2 DMC 0 */
42#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
43#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
44#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
45#define PHYS_SDRAM_3 0x60000000 /* LPDDR2 DMC 1 */
46#define PHYS_SDRAM_3_SIZE (256 << 20) /* 256 MB in CS 0 */
47#define PHYS_SDRAM_4 0x70000000 /* LPDDR2 DMC 1 */
48#define PHYS_SDRAM_4_SIZE (256 << 20) /* 256 MB in CS 0 */
49#define PHYS_SDRAM_END 0x80000000
50
51#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
52
53#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
54#define CONFIG_SYS_TEXT_BASE 0x78100000
55
56#define CONFIG_SYS_CLK_FREQ 24000000
57
58#define CONFIG_SETUP_MEMORY_TAGS
59#define CONFIG_CMDLINE_TAG
60#define CONFIG_REVISION_TAG
61
62/* MACH_TYPE_TRATS2 */
63#define MACH_TYPE_TRATS2 3765
64#define CONFIG_MACH_TYPE MACH_TYPE_TRATS2
65
66#define CONFIG_DISPLAY_CPUINFO
67
68/*
69 * Size of malloc() pool
70 */
71#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20))
72
73/* select serial console configuration */
74#define CONFIG_SERIAL2
75
76#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
77#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
78
79#define CONFIG_CMDLINE_EDITING
80
81#define CONFIG_BAUDRATE 115200
82
83/* It should define before config_cmd_default.h */
84#define CONFIG_SYS_NO_FLASH
85
86/***********************************************************
87 * Command definition
88 ***********************************************************/
89#include <config_cmd_default.h>
90
91#undef CONFIG_CMD_ECHO
92#undef CONFIG_CMD_FPGA
93#undef CONFIG_CMD_FLASH
94#undef CONFIG_CMD_IMLS
95#undef CONFIG_CMD_NAND
96#undef CONFIG_CMD_MISC
97#undef CONFIG_CMD_NFS
98#undef CONFIG_CMD_SOURCE
99#undef CONFIG_CMD_XIMG
100#define CONFIG_CMD_CACHE
101#define CONFIG_CMD_I2C
102#define CONFIG_CMD_MMC
103#define CONFIG_CMD_GPT
104#define CONFIG_CMD_PMIC
105
106#define CONFIG_BOOTDELAY 3
107#define CONFIG_ZERO_BOOTDELAY_CHECK
108
109#define CONFIG_CMD_FAT
110#define CONFIG_FAT_WRITE
111
112/* EXT4 */
113#define CONFIG_CMD_EXT4
114#define CONFIG_CMD_EXT4_WRITE
115
116/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
117#undef CONFIG_CMD_NET
118
119/* MMC */
120#define CONFIG_GENERIC_MMC
121#define CONFIG_MMC
122#define CONFIG_S5P_SDHCI
123#define CONFIG_SDHCI
124#define CONFIG_MMC_SDMA
125#define CONFIG_MMC_DEFAULT_DEV 0
126
127/* PWM */
128#define CONFIG_PWM
129
130#define CONFIG_BOOTARGS "Please use defined boot"
131#define CONFIG_BOOTCOMMAND "run mmcboot"
132#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
133
134#define CONFIG_ENV_OVERWRITE
135#define CONFIG_SYS_CONSOLE_INFO_QUIET
136#define CONFIG_SYS_CONSOLE_IS_IN_ENV
137
138/* Tizen - partitions definitions */
139#define PARTS_CSA "csa-mmc"
140#define PARTS_BOOTLOADER "u-boot"
141#define PARTS_BOOT "boot"
142#define PARTS_ROOT "platform"
143#define PARTS_DATA "data"
144#define PARTS_CSC "csc"
145#define PARTS_UMS "ums"
146
147#define PARTS_DEFAULT \
148 "uuid_disk=${uuid_gpt_disk};" \
149 "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
150 "name="PARTS_BOOTLOADER",size=60MiB," \
151 "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
152 "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
153 "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
154 "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
155 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
156 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
157
158#define CONFIG_EXTRA_ENV_SETTINGS \
159 "bootk=" \
160 "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
161 "updatemmc=" \
162 "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \
163 "mmc boot 0 1 1 0\0" \
164 "updatebackup=" \
165 "mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \
166 " mmc boot 0 1 1 0\0" \
167 "updatebootb=" \
168 "mmc read 0x51000000 0x80 0x200; run updatebackup\0" \
169 "updateuboot=" \
170 "mmc write 0x50000000 0x80 0x400\0" \
171 "mmcboot=" \
172 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
173 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
174 "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
175 "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
176 "boottrace=setenv opts initcall_debug; run bootcmd\0" \
177 "verify=n\0" \
178 "rootfstype=ext4\0" \
179 "console=" CONFIG_DEFAULT_CONSOLE \
180 "kernelname=uImage\0" \
181 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
182 "0x40007FC0 ${kernelname}\0" \
183 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
184 "${fdtfile}\0" \
185 "mmcdev=0\0" \
186 "mmcbootpart=2\0" \
187 "mmcrootpart=5\0" \
188 "opts=always_resume=1\0" \
189 "partitions=" PARTS_DEFAULT \
190 "uartpath=ap\0" \
191 "usbpath=ap\0" \
192 "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
193 "consoleoff=set console console=ram; save; reset\0" \
194 "spladdr=0x40000100\0" \
195 "splsize=0x200\0" \
196 "splfile=falcon.bin\0" \
197 "spl_export=" \
198 "setexpr spl_imgsize ${splsize} + 8 ;" \
199 "setenv spl_imgsize 0x${spl_imgsize};" \
200 "setexpr spl_imgaddr ${spladdr} - 8 ;" \
201 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
202 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
203 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
204 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
205 "spl export atags 0x40007FC0;" \
206 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
207 "mw.l ${spl_addr_tmp} ${splsize};" \
208 "ext4write mmc ${mmcdev}:${mmcbootpart}" \
209 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
210 "setenv spl_imgsize;" \
211 "setenv spl_imgaddr;" \
212 "setenv spl_addr_tmp;\0" \
213 "fdtaddr=40800000\0" \
214 "fdtfile=exynos4412-trats2.dtb\0"
215
216/*
217 * Miscellaneous configurable options
218 */
219#define CONFIG_SYS_LONGHELP /* undef to save memory */
220#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
221#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
222#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
223#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
224
225/* Boot Argument Buffer Size */
226#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
227
228/* memtest works on */
229#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
230#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
231#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
232
233#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
234 - GENERATED_GBL_DATA_SIZE)
235
236#define CONFIG_SYS_HZ 1000
237
238/* valid baudrates */
239#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
240
241#define CONFIG_SYS_MONITOR_BASE 0x00000000
242
243/*-----------------------------------------------------------------------
244 * FLASH and environment organization
245 */
246
247#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
248
249#define CONFIG_ENV_IS_IN_MMC
250#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
251#define CONFIG_ENV_SIZE 4096
252#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
253#define CONFIG_EFI_PARTITION
254#define CONFIG_PARTITION_UUIDS
255
256#define CONFIG_MISC_INIT_R
257#define CONFIG_BOARD_EARLY_INIT_F
258
259/* I2C */
260#include <asm/arch/gpio.h>
261
262#define CONFIG_SYS_I2C
263#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
264#define CONFIG_SYS_I2C_SOFT_SPEED 50000
265#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
266#define I2C_SOFT_DECLARATIONS2
267#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
268#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00
269#define I2C_SOFT_DECLARATIONS3
270#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
271#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x00
272#define CONFIG_SOFT_I2C_READ_REPEATED_START
273#define CONFIG_SYS_I2C_INIT_BOARD
274#define CONFIG_I2C_MULTI_BUS
275#define CONFIG_SOFT_I2C_MULTI_BUS
276#define CONFIG_SYS_MAX_I2C_BUS 15
277
278#define CONFIG_SOFT_I2C_I2C5_SCL exynos4x12_gpio_part1_get_nr(d0, 3)
279#define CONFIG_SOFT_I2C_I2C5_SDA exynos4x12_gpio_part1_get_nr(d0, 2)
280#define CONFIG_SOFT_I2C_I2C9_SCL exynos4x12_gpio_part1_get_nr(f1, 4)
281#define CONFIG_SOFT_I2C_I2C9_SDA exynos4x12_gpio_part1_get_nr(f1, 5)
282#define CONFIG_SOFT_I2C_I2C10_SCL exynos4x12_gpio_part2_get_nr(m2, 1)
283#define CONFIG_SOFT_I2C_I2C10_SDA exynos4x12_gpio_part2_get_nr(m2, 0)
284#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
285#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
286#define I2C_INIT multi_i2c_init()
287
288/* POWER */
289#define CONFIG_POWER
290#define CONFIG_POWER_I2C
291#define CONFIG_POWER_MAX77686
292#define CONFIG_POWER_PMIC_MAX77693
293#define CONFIG_POWER_MUIC_MAX77693
294#define CONFIG_POWER_FG_MAX77693
295#define CONFIG_POWER_BATTERY_TRATS2
296
297/* LCD */
298#define CONFIG_EXYNOS_FB
299#define CONFIG_LCD
300#define CONFIG_CMD_BMP
301#define CONFIG_BMP_32BPP
302#define CONFIG_FB_ADDR 0x52504000
303#define CONFIG_S6E8AX0
304#define CONFIG_EXYNOS_MIPI_DSIM
305#define CONFIG_VIDEO_BMP_GZIP
306#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12))
307
308/* Pass open firmware flat tree */
309#define CONFIG_OF_LIBFDT 1
310
311#endif /* __CONFIG_H */