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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 910df4d07e370dc0dabafaaf85417508cccf43f3 / . / drivers / pinctrl / renesas / pfc-r8a7795.c
blob: 43eef69025203c2a5e9ff5faaf19c16d67614715 [file] [log] [blame]
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame^]1/*
2 * R8A7795 ES2.0+ processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9#include <common.h>
10#include <dm.h>
11#include <errno.h>
12#include <dm/pinctrl.h>
13#include <linux/kernel.h>
14
15#include "sh_pfc.h"
16
17#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
21#define CPU_ALL_PORT(fn, sfx) \
22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
34/*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39/* GPSR0 */
40#define GPSR0_15 F_(D15, IP7_11_8)
41#define GPSR0_14 F_(D14, IP7_7_4)
42#define GPSR0_13 F_(D13, IP7_3_0)
43#define GPSR0_12 F_(D12, IP6_31_28)
44#define GPSR0_11 F_(D11, IP6_27_24)
45#define GPSR0_10 F_(D10, IP6_23_20)
46#define GPSR0_9 F_(D9, IP6_19_16)
47#define GPSR0_8 F_(D8, IP6_15_12)
48#define GPSR0_7 F_(D7, IP6_11_8)
49#define GPSR0_6 F_(D6, IP6_7_4)
50#define GPSR0_5 F_(D5, IP6_3_0)
51#define GPSR0_4 F_(D4, IP5_31_28)
52#define GPSR0_3 F_(D3, IP5_27_24)
53#define GPSR0_2 F_(D2, IP5_23_20)
54#define GPSR0_1 F_(D1, IP5_19_16)
55#define GPSR0_0 F_(D0, IP5_15_12)
56
57/* GPSR1 */
58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0)
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20)
64#define GPSR1_21 F_(CS1_N, IP4_19_16)
65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4)
68#define GPSR1_17 F_(A17, IP4_3_0)
69#define GPSR1_16 F_(A16, IP3_31_28)
70#define GPSR1_15 F_(A15, IP3_27_24)
71#define GPSR1_14 F_(A14, IP3_23_20)
72#define GPSR1_13 F_(A13, IP3_19_16)
73#define GPSR1_12 F_(A12, IP3_15_12)
74#define GPSR1_11 F_(A11, IP3_11_8)
75#define GPSR1_10 F_(A10, IP3_7_4)
76#define GPSR1_9 F_(A9, IP3_3_0)
77#define GPSR1_8 F_(A8, IP2_31_28)
78#define GPSR1_7 F_(A7, IP2_27_24)
79#define GPSR1_6 F_(A6, IP2_23_20)
80#define GPSR1_5 F_(A5, IP2_19_16)
81#define GPSR1_4 F_(A4, IP2_15_12)
82#define GPSR1_3 F_(A3, IP2_11_8)
83#define GPSR1_2 F_(A2, IP2_7_4)
84#define GPSR1_1 F_(A1, IP2_3_0)
85#define GPSR1_0 F_(A0, IP1_31_28)
86
87/* GPSR2 */
88#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94#define GPSR2_8 F_(PWM2_A, IP1_27_24)
95#define GPSR2_7 F_(PWM1_A, IP1_23_20)
96#define GPSR2_6 F_(PWM0, IP1_19_16)
97#define GPSR2_5 F_(IRQ5, IP1_15_12)
98#define GPSR2_4 F_(IRQ4, IP1_11_8)
99#define GPSR2_3 F_(IRQ3, IP1_7_4)
100#define GPSR2_2 F_(IRQ2, IP1_3_0)
101#define GPSR2_1 F_(IRQ1, IP0_31_28)
102#define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104/* GPSR3 */
105#define GPSR3_15 F_(SD1_WP, IP11_23_20)
106#define GPSR3_14 F_(SD1_CD, IP11_19_16)
107#define GPSR3_13 F_(SD0_WP, IP11_15_12)
108#define GPSR3_12 F_(SD0_CD, IP11_11_8)
109#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122/* GPSR4 */
123#define GPSR4_17 F_(SD3_DS, IP11_7_4)
124#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134#define GPSR4_6 F_(SD2_DS, IP9_27_24)
135#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
140#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142/* GPSR5 */
143#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
146#define GPSR5_22 FM(MSIOF0_RXD)
147#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
148#define GPSR5_20 FM(MSIOF0_TXD)
149#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
151#define GPSR5_17 FM(MSIOF0_SCK)
152#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154#define GPSR5_14 F_(HTX0, IP13_19_16)
155#define GPSR5_13 F_(HRX0, IP13_15_12)
156#define GPSR5_12 F_(HSCK0, IP13_11_8)
157#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28)
160#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
161#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12)
164#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
165#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28)
168#define GPSR5_0 F_(SCK0, IP11_27_24)
169
170/* GPSR6 */
171#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
189#define GPSR6_13 FM(SSI_SDATA5)
190#define GPSR6_12 FM(SSI_WS5)
191#define GPSR6_11 FM(SSI_SCK5)
192#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
196#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
198#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
203
204/* GPSR7 */
205#define GPSR7_3 FM(HDMI1_CEC)
206#define GPSR7_2 FM(HDMI0_CEC)
207#define GPSR7_1 FM(AVS2)
208#define GPSR7_0 FM(AVS1)
209
210
211/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306
307/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
308#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
329#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336
337/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
338#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
358#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
359#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
360#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
361#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
364#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
365
366#define PINMUX_GPSR \
367\
368 GPSR6_31 \
369 GPSR6_30 \
370 GPSR6_29 \
371 GPSR6_28 \
372 GPSR1_27 GPSR6_27 \
373 GPSR1_26 GPSR6_26 \
374 GPSR1_25 GPSR5_25 GPSR6_25 \
375 GPSR1_24 GPSR5_24 GPSR6_24 \
376 GPSR1_23 GPSR5_23 GPSR6_23 \
377 GPSR1_22 GPSR5_22 GPSR6_22 \
378 GPSR1_21 GPSR5_21 GPSR6_21 \
379 GPSR1_20 GPSR5_20 GPSR6_20 \
380 GPSR1_19 GPSR5_19 GPSR6_19 \
381 GPSR1_18 GPSR5_18 GPSR6_18 \
382 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
383 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
384GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
385GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
386GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
387GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
388GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
389GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
390GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
391GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
392GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
393GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
394GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
395GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
396GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
397GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
398GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
399GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
400
401#define PINMUX_IPSR \
402\
403FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
404FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
405FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
406FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
407FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
408FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
409FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
410FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
411\
412FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
413FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
414FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
415FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
416FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
417FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
418FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
419FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
420\
421FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
422FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
423FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
424FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
425FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
426FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
427FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
428FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
429\
430FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
431FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
432FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
433FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
434FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
435FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
436FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
437FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
438\
439FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
440FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
441FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
442FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
443FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
444FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
445FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
446FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
447
448/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
449#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
450#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
451#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
452#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
453#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
454#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
455#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
456#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
457#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
458#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
459#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
460#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
461#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
462#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
463#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
464#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
465#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
466#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
467
468/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
469#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
470#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
471#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
472#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
473#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
474#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
475#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
476#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
477#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
478#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
479#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
480#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
481#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
482#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
483#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
484#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
485#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
486#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
487#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
488#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
489#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
490#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
491
492/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
493#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
494#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
495#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
496#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
497#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
498#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
500#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
501#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
502#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
503#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
504#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
505
506#define PINMUX_MOD_SELS \
507\
508MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
509 MOD_SEL2_30 \
510 MOD_SEL1_29_28_27 MOD_SEL2_29 \
511MOD_SEL0_28_27 MOD_SEL2_28_27 \
512MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
513 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
514MOD_SEL0_23 MOD_SEL1_23_22_21 \
515MOD_SEL0_22 \
516MOD_SEL0_21 MOD_SEL2_21 \
517MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
518MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
519MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
520 MOD_SEL2_17 \
521MOD_SEL0_16 MOD_SEL1_16 \
522 MOD_SEL1_15_14 \
523MOD_SEL0_14_13 \
524 MOD_SEL1_13 \
525MOD_SEL0_12 MOD_SEL1_12 \
526MOD_SEL0_11 MOD_SEL1_11 \
527MOD_SEL0_10 MOD_SEL1_10 \
528MOD_SEL0_9_8 MOD_SEL1_9 \
529MOD_SEL0_7_6 \
530 MOD_SEL1_6 \
531MOD_SEL0_5 MOD_SEL1_5 \
532MOD_SEL0_4_3 MOD_SEL1_4 \
533 MOD_SEL1_3 \
534 MOD_SEL1_2 \
535 MOD_SEL1_1 \
536 MOD_SEL1_0 MOD_SEL2_0
537
538/*
539 * These pins are not able to be muxed but have other properties
540 * that can be set, such as drive-strength or pull-up/pull-down enable.
541 */
542#define PINMUX_STATIC \
543 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
544 FM(QSPI0_IO2) FM(QSPI0_IO3) \
545 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
546 FM(QSPI1_IO2) FM(QSPI1_IO3) \
547 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
548 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
551 FM(CLKOUT) FM(PRESETOUT) \
552 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
553 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
554
555enum {
556 PINMUX_RESERVED = 0,
557
558 PINMUX_DATA_BEGIN,
559 GP_ALL(DATA),
560 PINMUX_DATA_END,
561
562#define F_(x, y)
563#define FM(x) FN_##x,
564 PINMUX_FUNCTION_BEGIN,
565 GP_ALL(FN),
566 PINMUX_GPSR
567 PINMUX_IPSR
568 PINMUX_MOD_SELS
569 PINMUX_FUNCTION_END,
570#undef F_
571#undef FM
572
573#define F_(x, y)
574#define FM(x) x##_MARK,
575 PINMUX_MARK_BEGIN,
576 PINMUX_GPSR
577 PINMUX_IPSR
578 PINMUX_MOD_SELS
579 PINMUX_STATIC
580 PINMUX_MARK_END,
581#undef F_
582#undef FM
583};
584
585static const u16 pinmux_data[] = {
586 PINMUX_DATA_GP_ALL(),
587
588 PINMUX_SINGLE(AVS1),
589 PINMUX_SINGLE(AVS2),
590 PINMUX_SINGLE(HDMI0_CEC),
591 PINMUX_SINGLE(HDMI1_CEC),
592 PINMUX_SINGLE(I2C_SEL_0_1),
593 PINMUX_SINGLE(I2C_SEL_3_1),
594 PINMUX_SINGLE(I2C_SEL_5_1),
595 PINMUX_SINGLE(MSIOF0_RXD),
596 PINMUX_SINGLE(MSIOF0_SCK),
597 PINMUX_SINGLE(MSIOF0_TXD),
598 PINMUX_SINGLE(SSI_SCK5),
599 PINMUX_SINGLE(SSI_SDATA5),
600 PINMUX_SINGLE(SSI_WS5),
601
602 /* IPSR0 */
603 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
604 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
605
606 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
607 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
608 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
609
610 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
611 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
612 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
613
614 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
615 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
616 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
617
618 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
619 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
620 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
621 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
622
623 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
624 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
625 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
626
627 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
628 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
629 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
630 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
631 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
632 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
634
635 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
636 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
637 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
638 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
639 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
640 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
642
643 /* IPSR1 */
644 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
645 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
646 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
647 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
648 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
649 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
650
651 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
652 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
653 PINMUX_IPSR_GPSR(IP1_7_4, A25),
654 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
655 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
656 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
657 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
658
659 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
660 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
661 PINMUX_IPSR_GPSR(IP1_11_8, A24),
662 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
663 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
665 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
666
667 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
668 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
669 PINMUX_IPSR_GPSR(IP1_15_12, A23),
670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
673 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
675
676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
678 PINMUX_IPSR_GPSR(IP1_19_16, A22),
679 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
680 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
681
682 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
683 PINMUX_IPSR_GPSR(IP1_23_20, A21),
684 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
685 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
687
688 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
689 PINMUX_IPSR_GPSR(IP1_27_24, A20),
690 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
691 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
692
693 PINMUX_IPSR_GPSR(IP1_31_28, A0),
694 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
695 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
696 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
697 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
698 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
699
700 /* IPSR2 */
701 PINMUX_IPSR_GPSR(IP2_3_0, A1),
702 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
703 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
704 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
705 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
706 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
707
708 PINMUX_IPSR_GPSR(IP2_7_4, A2),
709 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
710 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
711 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
712 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
713 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
714
715 PINMUX_IPSR_GPSR(IP2_11_8, A3),
716 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
717 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
718 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
719 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
720 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
721
722 PINMUX_IPSR_GPSR(IP2_15_12, A4),
723 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
724 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
725 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
726 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
727 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
728
729 PINMUX_IPSR_GPSR(IP2_19_16, A5),
730 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
731 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
732 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
733 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
734 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
735 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
736
737 PINMUX_IPSR_GPSR(IP2_23_20, A6),
738 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
739 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
740 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
741 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
742 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
743 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
744
745 PINMUX_IPSR_GPSR(IP2_27_24, A7),
746 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
747 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
749 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
750 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
751 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
752
753 PINMUX_IPSR_GPSR(IP2_31_28, A8),
754 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
756 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
760
761 /* IPSR3 */
762 PINMUX_IPSR_GPSR(IP3_3_0, A9),
763 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
765 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
766
767 PINMUX_IPSR_GPSR(IP3_7_4, A10),
768 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
769 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
770 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
771
772 PINMUX_IPSR_GPSR(IP3_11_8, A11),
773 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
774 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
776 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
777 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
778 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
779 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
780 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
781
782 PINMUX_IPSR_GPSR(IP3_15_12, A12),
783 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
784 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
785 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
786 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
787 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
788
789 PINMUX_IPSR_GPSR(IP3_19_16, A13),
790 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
791 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
792 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
793 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
794 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
795
796 PINMUX_IPSR_GPSR(IP3_23_20, A14),
797 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
798 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
799 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
800 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
801 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
802
803 PINMUX_IPSR_GPSR(IP3_27_24, A15),
804 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
805 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
806 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
807 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
808 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
809
810 PINMUX_IPSR_GPSR(IP3_31_28, A16),
811 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
812 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
813 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
814
815 /* IPSR4 */
816 PINMUX_IPSR_GPSR(IP4_3_0, A17),
817 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
818 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
819 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
820
821 PINMUX_IPSR_GPSR(IP4_7_4, A18),
822 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
823 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
824 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
825
826 PINMUX_IPSR_GPSR(IP4_11_8, A19),
827 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
828 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
829 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
830
831 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
832 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
833
834 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
835 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
836 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
837
838 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
839 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
840 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
841 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
842 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
843 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
844 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
845 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
846
847 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
848 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
849 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
850 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
851 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
853
854 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
855 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
856 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
857 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
858 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
860
861 /* IPSR5 */
862 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
864 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
865 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
866 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
867 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
868 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
869
870 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
872 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
873 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
874 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
875 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
876 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
877 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
878
879 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
880 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
881 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
882 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
883
884 PINMUX_IPSR_GPSR(IP5_15_12, D0),
885 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
886 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
887 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
888 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
889
890 PINMUX_IPSR_GPSR(IP5_19_16, D1),
891 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
893 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
894 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
895
896 PINMUX_IPSR_GPSR(IP5_23_20, D2),
897 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
898 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
899 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
900
901 PINMUX_IPSR_GPSR(IP5_27_24, D3),
902 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
903 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
904 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
905
906 PINMUX_IPSR_GPSR(IP5_31_28, D4),
907 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
908 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
909 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
910
911 /* IPSR6 */
912 PINMUX_IPSR_GPSR(IP6_3_0, D5),
913 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
914 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
915 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
916
917 PINMUX_IPSR_GPSR(IP6_7_4, D6),
918 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
920 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
921
922 PINMUX_IPSR_GPSR(IP6_11_8, D7),
923 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
924 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
925 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
926
927 PINMUX_IPSR_GPSR(IP6_15_12, D8),
928 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
929 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
930 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
931 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
932 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
933
934 PINMUX_IPSR_GPSR(IP6_19_16, D9),
935 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
936 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
937 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
938 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
939
940 PINMUX_IPSR_GPSR(IP6_23_20, D10),
941 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
942 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
943 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
944 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
945 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
946 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
947
948 PINMUX_IPSR_GPSR(IP6_27_24, D11),
949 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
950 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
953 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
954 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
955
956 PINMUX_IPSR_GPSR(IP6_31_28, D12),
957 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
958 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
959 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
960 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
961 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
962
963 /* IPSR7 */
964 PINMUX_IPSR_GPSR(IP7_3_0, D13),
965 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
966 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
967 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
968 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
969 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
970
971 PINMUX_IPSR_GPSR(IP7_7_4, D14),
972 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
973 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
974 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
975 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
976 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
977 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
978
979 PINMUX_IPSR_GPSR(IP7_11_8, D15),
980 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
981 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
982 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
983 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
985 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
986
987 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
988 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
989 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
990
991 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
992 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
994
995 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
996 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
998 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
999
1000 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1001 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1002 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1003 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1004
1005 /* IPSR8 */
1006 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1007 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1008 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1009 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1010
1011 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1012 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1013 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1014 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1015
1016 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1017 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1019
1020 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1021 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1023 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1024 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1025
1026 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1027 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1028 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1029 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1030 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1032
1033 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1034 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1035 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1036 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1037 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1038 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1039
1040 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1041 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1042 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1043 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1044 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1045 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1046
1047 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1048 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1049 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1050 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1051 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1052 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1053
1054 /* IPSR9 */
1055 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1056 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1057
1058 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1059 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1060
1061 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1062 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1063
1064 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1065 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1066
1067 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1068 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1069
1070 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1071 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1072
1073 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1074 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1075 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1076
1077 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1078 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1079
1080 /* IPSR10 */
1081 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1082 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1083
1084 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1085 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1086
1087 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1088 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1089
1090 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1091 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1092
1093 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1094 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1095
1096 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1097 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1099
1100 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1101 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1103
1104 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1105 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1106 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1107
1108 /* IPSR11 */
1109 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1110 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1111 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1112
1113 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1114 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1115
1116 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1117 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1118 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1119
1120 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1121 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1122
1123 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1124 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1125
1126 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1127 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1128
1129 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1136 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1137 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1139
1140 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1141 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1142 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1143 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1145
1146 /* IPSR12 */
1147 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1148 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1149 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1150 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1152
1153 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1154 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1155 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1157 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1159 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1160 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1161
1162 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1163 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1164 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1167 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1168 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1169 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1170
1171 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1172 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1174 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1176
1177 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1178 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1180 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1182
1183 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1184 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1185 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1186 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1187 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1189 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1190
1191 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1192 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1195 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1197 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1198
1199 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1200 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1201 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1206
1207 /* IPSR13 */
1208 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1209 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1213 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1214
1215 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1216 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1220 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1221
1222 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1223 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1225 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1226 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1227 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1230
1231 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1232 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1233 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1234 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1235 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1237
1238 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1239 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1240 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1241 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1242 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1244
1245 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1246 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1247 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1248 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1249 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1250 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1252 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1253
1254 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1255 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1256 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1257 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1258 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1259 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1260 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1261
1262 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1263 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1264 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1265 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1266
1267 /* IPSR14 */
1268 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1269 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1270 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
1271 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1272 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1273 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1274 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1275 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1276
1277 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1278 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1279 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1280 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1281 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1284 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1285
1286 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1287 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1291 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1293 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1294
1295 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1296 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1297 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1298
1299 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1300 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1301
1302 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1303 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1304
1305 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1306 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1307
1308 /* IPSR15 */
1309 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1310
1311 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1313
1314 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1315 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1317
1318 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1319 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1322
1323 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1324 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1330
1331 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1332 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1338
1339 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1340 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1346
1347 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1348 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1354
1355 /* IPSR16 */
1356 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1357 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1358 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1361 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1362 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1363
1364 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1365 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1366 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1367
1368 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1369 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1370 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1371 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1375
1376 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1377 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1378 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1379 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1383
1384 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1385 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1386 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1387 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1391 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1392
1393 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1394 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1395 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1396 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1400
1401 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1402 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1403 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1406 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1408 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1409
1410 /* IPSR17 */
1411 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1412 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1413
1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1418 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1419
1420 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1421 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1422 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1426 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1427
1428 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1429 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1430 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1432 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1433 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1434
1435 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1437 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1438 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1442 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1443 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1444
1445 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1446 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1447 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1448 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1450 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1454
1455 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1456 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1457 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1458 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1462 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1463 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1464 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1465 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1466
1467 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1468 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1469 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1470 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1472 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1473 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1474 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1475 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1476
1477 /* IPSR18 */
1478 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1479 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1480 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1481 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1483 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1484 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1487
1488 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1489 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1490 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1491 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1493 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1496 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1497
1498/*
1499 * Static pins can not be muxed between different functions but
1500 * still needs a mark entry in the pinmux list. Add each static
1501 * pin to the list without an associated function. The sh-pfc
1502 * core will do the right thing and skip trying to mux then pin
1503 * while still applying configuration to it
1504 */
1505#define FM(x) PINMUX_DATA(x##_MARK, 0),
1506 PINMUX_STATIC
1507#undef FM
1508};
1509
1510/*
1511 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
1512 * Physical layout rows: A - AW, cols: 1 - 39.
1513 */
1514#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1515#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1516#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1517
1518static const struct sh_pfc_pin pinmux_pins[] = {
1519 PINMUX_GPIO_GP_ALL(),
1520
1521 /*
1522 * Pins not associated with a GPIO port.
1523 *
1524 * The pin positions are different between different r8a7795
1525 * packages, all that is needed for the pfc driver is a unique
1526 * number for each pin. To this end use the pin layout from
1527 * R-Car H3SiP to calculate a unique number for each pin.
1528 */
1529 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1530 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1573};
1574
1575/* - EtherAVB --------------------------------------------------------------- */
1576static const unsigned int avb_link_pins[] = {
1577 /* AVB_LINK */
1578 RCAR_GP_PIN(2, 12),
1579};
1580static const unsigned int avb_link_mux[] = {
1581 AVB_LINK_MARK,
1582};
1583static const unsigned int avb_magic_pins[] = {
1584 /* AVB_MAGIC_ */
1585 RCAR_GP_PIN(2, 10),
1586};
1587static const unsigned int avb_magic_mux[] = {
1588 AVB_MAGIC_MARK,
1589};
1590static const unsigned int avb_phy_int_pins[] = {
1591 /* AVB_PHY_INT */
1592 RCAR_GP_PIN(2, 11),
1593};
1594static const unsigned int avb_phy_int_mux[] = {
1595 AVB_PHY_INT_MARK,
1596};
1597static const unsigned int avb_mdc_pins[] = {
1598 /* AVB_MDC, AVB_MDIO */
1599 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1600};
1601static const unsigned int avb_mdc_mux[] = {
1602 AVB_MDC_MARK, AVB_MDIO_MARK,
1603};
1604static const unsigned int avb_mii_pins[] = {
1605 /*
1606 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1607 * AVB_TD1, AVB_TD2, AVB_TD3,
1608 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1609 * AVB_RD1, AVB_RD2, AVB_RD3,
1610 * AVB_TXCREFCLK
1611 */
1612 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1613 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1614 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1615 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1616 PIN_NUMBER('A', 12),
1617
1618};
1619static const unsigned int avb_mii_mux[] = {
1620 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1621 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1622 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1623 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1624 AVB_TXCREFCLK_MARK,
1625};
1626static const unsigned int avb_avtp_pps_pins[] = {
1627 /* AVB_AVTP_PPS */
1628 RCAR_GP_PIN(2, 6),
1629};
1630static const unsigned int avb_avtp_pps_mux[] = {
1631 AVB_AVTP_PPS_MARK,
1632};
1633static const unsigned int avb_avtp_match_a_pins[] = {
1634 /* AVB_AVTP_MATCH_A */
1635 RCAR_GP_PIN(2, 13),
1636};
1637static const unsigned int avb_avtp_match_a_mux[] = {
1638 AVB_AVTP_MATCH_A_MARK,
1639};
1640static const unsigned int avb_avtp_capture_a_pins[] = {
1641 /* AVB_AVTP_CAPTURE_A */
1642 RCAR_GP_PIN(2, 14),
1643};
1644static const unsigned int avb_avtp_capture_a_mux[] = {
1645 AVB_AVTP_CAPTURE_A_MARK,
1646};
1647static const unsigned int avb_avtp_match_b_pins[] = {
1648 /* AVB_AVTP_MATCH_B */
1649 RCAR_GP_PIN(1, 8),
1650};
1651static const unsigned int avb_avtp_match_b_mux[] = {
1652 AVB_AVTP_MATCH_B_MARK,
1653};
1654static const unsigned int avb_avtp_capture_b_pins[] = {
1655 /* AVB_AVTP_CAPTURE_B */
1656 RCAR_GP_PIN(1, 11),
1657};
1658static const unsigned int avb_avtp_capture_b_mux[] = {
1659 AVB_AVTP_CAPTURE_B_MARK,
1660};
1661
1662/* - DRIF0 --------------------------------------------------------------- */
1663static const unsigned int drif0_ctrl_a_pins[] = {
1664 /* CLK, SYNC */
1665 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1666};
1667static const unsigned int drif0_ctrl_a_mux[] = {
1668 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1669};
1670static const unsigned int drif0_data0_a_pins[] = {
1671 /* D0 */
1672 RCAR_GP_PIN(6, 10),
1673};
1674static const unsigned int drif0_data0_a_mux[] = {
1675 RIF0_D0_A_MARK,
1676};
1677static const unsigned int drif0_data1_a_pins[] = {
1678 /* D1 */
1679 RCAR_GP_PIN(6, 7),
1680};
1681static const unsigned int drif0_data1_a_mux[] = {
1682 RIF0_D1_A_MARK,
1683};
1684static const unsigned int drif0_ctrl_b_pins[] = {
1685 /* CLK, SYNC */
1686 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1687};
1688static const unsigned int drif0_ctrl_b_mux[] = {
1689 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1690};
1691static const unsigned int drif0_data0_b_pins[] = {
1692 /* D0 */
1693 RCAR_GP_PIN(5, 1),
1694};
1695static const unsigned int drif0_data0_b_mux[] = {
1696 RIF0_D0_B_MARK,
1697};
1698static const unsigned int drif0_data1_b_pins[] = {
1699 /* D1 */
1700 RCAR_GP_PIN(5, 2),
1701};
1702static const unsigned int drif0_data1_b_mux[] = {
1703 RIF0_D1_B_MARK,
1704};
1705static const unsigned int drif0_ctrl_c_pins[] = {
1706 /* CLK, SYNC */
1707 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1708};
1709static const unsigned int drif0_ctrl_c_mux[] = {
1710 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1711};
1712static const unsigned int drif0_data0_c_pins[] = {
1713 /* D0 */
1714 RCAR_GP_PIN(5, 13),
1715};
1716static const unsigned int drif0_data0_c_mux[] = {
1717 RIF0_D0_C_MARK,
1718};
1719static const unsigned int drif0_data1_c_pins[] = {
1720 /* D1 */
1721 RCAR_GP_PIN(5, 14),
1722};
1723static const unsigned int drif0_data1_c_mux[] = {
1724 RIF0_D1_C_MARK,
1725};
1726/* - DRIF1 --------------------------------------------------------------- */
1727static const unsigned int drif1_ctrl_a_pins[] = {
1728 /* CLK, SYNC */
1729 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1730};
1731static const unsigned int drif1_ctrl_a_mux[] = {
1732 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1733};
1734static const unsigned int drif1_data0_a_pins[] = {
1735 /* D0 */
1736 RCAR_GP_PIN(6, 19),
1737};
1738static const unsigned int drif1_data0_a_mux[] = {
1739 RIF1_D0_A_MARK,
1740};
1741static const unsigned int drif1_data1_a_pins[] = {
1742 /* D1 */
1743 RCAR_GP_PIN(6, 20),
1744};
1745static const unsigned int drif1_data1_a_mux[] = {
1746 RIF1_D1_A_MARK,
1747};
1748static const unsigned int drif1_ctrl_b_pins[] = {
1749 /* CLK, SYNC */
1750 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1751};
1752static const unsigned int drif1_ctrl_b_mux[] = {
1753 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1754};
1755static const unsigned int drif1_data0_b_pins[] = {
1756 /* D0 */
1757 RCAR_GP_PIN(5, 7),
1758};
1759static const unsigned int drif1_data0_b_mux[] = {
1760 RIF1_D0_B_MARK,
1761};
1762static const unsigned int drif1_data1_b_pins[] = {
1763 /* D1 */
1764 RCAR_GP_PIN(5, 8),
1765};
1766static const unsigned int drif1_data1_b_mux[] = {
1767 RIF1_D1_B_MARK,
1768};
1769static const unsigned int drif1_ctrl_c_pins[] = {
1770 /* CLK, SYNC */
1771 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1772};
1773static const unsigned int drif1_ctrl_c_mux[] = {
1774 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1775};
1776static const unsigned int drif1_data0_c_pins[] = {
1777 /* D0 */
1778 RCAR_GP_PIN(5, 6),
1779};
1780static const unsigned int drif1_data0_c_mux[] = {
1781 RIF1_D0_C_MARK,
1782};
1783static const unsigned int drif1_data1_c_pins[] = {
1784 /* D1 */
1785 RCAR_GP_PIN(5, 10),
1786};
1787static const unsigned int drif1_data1_c_mux[] = {
1788 RIF1_D1_C_MARK,
1789};
1790/* - DRIF2 --------------------------------------------------------------- */
1791static const unsigned int drif2_ctrl_a_pins[] = {
1792 /* CLK, SYNC */
1793 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1794};
1795static const unsigned int drif2_ctrl_a_mux[] = {
1796 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1797};
1798static const unsigned int drif2_data0_a_pins[] = {
1799 /* D0 */
1800 RCAR_GP_PIN(6, 7),
1801};
1802static const unsigned int drif2_data0_a_mux[] = {
1803 RIF2_D0_A_MARK,
1804};
1805static const unsigned int drif2_data1_a_pins[] = {
1806 /* D1 */
1807 RCAR_GP_PIN(6, 10),
1808};
1809static const unsigned int drif2_data1_a_mux[] = {
1810 RIF2_D1_A_MARK,
1811};
1812static const unsigned int drif2_ctrl_b_pins[] = {
1813 /* CLK, SYNC */
1814 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1815};
1816static const unsigned int drif2_ctrl_b_mux[] = {
1817 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1818};
1819static const unsigned int drif2_data0_b_pins[] = {
1820 /* D0 */
1821 RCAR_GP_PIN(6, 30),
1822};
1823static const unsigned int drif2_data0_b_mux[] = {
1824 RIF2_D0_B_MARK,
1825};
1826static const unsigned int drif2_data1_b_pins[] = {
1827 /* D1 */
1828 RCAR_GP_PIN(6, 31),
1829};
1830static const unsigned int drif2_data1_b_mux[] = {
1831 RIF2_D1_B_MARK,
1832};
1833/* - DRIF3 --------------------------------------------------------------- */
1834static const unsigned int drif3_ctrl_a_pins[] = {
1835 /* CLK, SYNC */
1836 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1837};
1838static const unsigned int drif3_ctrl_a_mux[] = {
1839 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1840};
1841static const unsigned int drif3_data0_a_pins[] = {
1842 /* D0 */
1843 RCAR_GP_PIN(6, 19),
1844};
1845static const unsigned int drif3_data0_a_mux[] = {
1846 RIF3_D0_A_MARK,
1847};
1848static const unsigned int drif3_data1_a_pins[] = {
1849 /* D1 */
1850 RCAR_GP_PIN(6, 20),
1851};
1852static const unsigned int drif3_data1_a_mux[] = {
1853 RIF3_D1_A_MARK,
1854};
1855static const unsigned int drif3_ctrl_b_pins[] = {
1856 /* CLK, SYNC */
1857 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1858};
1859static const unsigned int drif3_ctrl_b_mux[] = {
1860 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1861};
1862static const unsigned int drif3_data0_b_pins[] = {
1863 /* D0 */
1864 RCAR_GP_PIN(6, 28),
1865};
1866static const unsigned int drif3_data0_b_mux[] = {
1867 RIF3_D0_B_MARK,
1868};
1869static const unsigned int drif3_data1_b_pins[] = {
1870 /* D1 */
1871 RCAR_GP_PIN(6, 29),
1872};
1873static const unsigned int drif3_data1_b_mux[] = {
1874 RIF3_D1_B_MARK,
1875};
1876
1877/* - DU --------------------------------------------------------------------- */
1878static const unsigned int du_rgb666_pins[] = {
1879 /* R[7:2], G[7:2], B[7:2] */
1880 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1881 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1882 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1883 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1884 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1885 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1886};
1887static const unsigned int du_rgb666_mux[] = {
1888 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1889 DU_DR3_MARK, DU_DR2_MARK,
1890 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1891 DU_DG3_MARK, DU_DG2_MARK,
1892 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1893 DU_DB3_MARK, DU_DB2_MARK,
1894};
1895static const unsigned int du_rgb888_pins[] = {
1896 /* R[7:0], G[7:0], B[7:0] */
1897 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1898 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1899 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1900 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1901 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1902 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1903 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1904 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1905 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1906};
1907static const unsigned int du_rgb888_mux[] = {
1908 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1909 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1910 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1911 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1912 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1913 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1914};
1915static const unsigned int du_clk_out_0_pins[] = {
1916 /* CLKOUT */
1917 RCAR_GP_PIN(1, 27),
1918};
1919static const unsigned int du_clk_out_0_mux[] = {
1920 DU_DOTCLKOUT0_MARK
1921};
1922static const unsigned int du_clk_out_1_pins[] = {
1923 /* CLKOUT */
1924 RCAR_GP_PIN(2, 3),
1925};
1926static const unsigned int du_clk_out_1_mux[] = {
1927 DU_DOTCLKOUT1_MARK
1928};
1929static const unsigned int du_sync_pins[] = {
1930 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1931 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1932};
1933static const unsigned int du_sync_mux[] = {
1934 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1935};
1936static const unsigned int du_oddf_pins[] = {
1937 /* EXDISP/EXODDF/EXCDE */
1938 RCAR_GP_PIN(2, 2),
1939};
1940static const unsigned int du_oddf_mux[] = {
1941 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1942};
1943static const unsigned int du_cde_pins[] = {
1944 /* CDE */
1945 RCAR_GP_PIN(2, 0),
1946};
1947static const unsigned int du_cde_mux[] = {
1948 DU_CDE_MARK,
1949};
1950static const unsigned int du_disp_pins[] = {
1951 /* DISP */
1952 RCAR_GP_PIN(2, 1),
1953};
1954static const unsigned int du_disp_mux[] = {
1955 DU_DISP_MARK,
1956};
1957
1958/* - MSIOF0 ----------------------------------------------------------------- */
1959static const unsigned int msiof0_clk_pins[] = {
1960 /* SCK */
1961 RCAR_GP_PIN(5, 17),
1962};
1963static const unsigned int msiof0_clk_mux[] = {
1964 MSIOF0_SCK_MARK,
1965};
1966static const unsigned int msiof0_sync_pins[] = {
1967 /* SYNC */
1968 RCAR_GP_PIN(5, 18),
1969};
1970static const unsigned int msiof0_sync_mux[] = {
1971 MSIOF0_SYNC_MARK,
1972};
1973static const unsigned int msiof0_ss1_pins[] = {
1974 /* SS1 */
1975 RCAR_GP_PIN(5, 19),
1976};
1977static const unsigned int msiof0_ss1_mux[] = {
1978 MSIOF0_SS1_MARK,
1979};
1980static const unsigned int msiof0_ss2_pins[] = {
1981 /* SS2 */
1982 RCAR_GP_PIN(5, 21),
1983};
1984static const unsigned int msiof0_ss2_mux[] = {
1985 MSIOF0_SS2_MARK,
1986};
1987static const unsigned int msiof0_txd_pins[] = {
1988 /* TXD */
1989 RCAR_GP_PIN(5, 20),
1990};
1991static const unsigned int msiof0_txd_mux[] = {
1992 MSIOF0_TXD_MARK,
1993};
1994static const unsigned int msiof0_rxd_pins[] = {
1995 /* RXD */
1996 RCAR_GP_PIN(5, 22),
1997};
1998static const unsigned int msiof0_rxd_mux[] = {
1999 MSIOF0_RXD_MARK,
2000};
2001/* - MSIOF1 ----------------------------------------------------------------- */
2002static const unsigned int msiof1_clk_a_pins[] = {
2003 /* SCK */
2004 RCAR_GP_PIN(6, 8),
2005};
2006static const unsigned int msiof1_clk_a_mux[] = {
2007 MSIOF1_SCK_A_MARK,
2008};
2009static const unsigned int msiof1_sync_a_pins[] = {
2010 /* SYNC */
2011 RCAR_GP_PIN(6, 9),
2012};
2013static const unsigned int msiof1_sync_a_mux[] = {
2014 MSIOF1_SYNC_A_MARK,
2015};
2016static const unsigned int msiof1_ss1_a_pins[] = {
2017 /* SS1 */
2018 RCAR_GP_PIN(6, 5),
2019};
2020static const unsigned int msiof1_ss1_a_mux[] = {
2021 MSIOF1_SS1_A_MARK,
2022};
2023static const unsigned int msiof1_ss2_a_pins[] = {
2024 /* SS2 */
2025 RCAR_GP_PIN(6, 6),
2026};
2027static const unsigned int msiof1_ss2_a_mux[] = {
2028 MSIOF1_SS2_A_MARK,
2029};
2030static const unsigned int msiof1_txd_a_pins[] = {
2031 /* TXD */
2032 RCAR_GP_PIN(6, 7),
2033};
2034static const unsigned int msiof1_txd_a_mux[] = {
2035 MSIOF1_TXD_A_MARK,
2036};
2037static const unsigned int msiof1_rxd_a_pins[] = {
2038 /* RXD */
2039 RCAR_GP_PIN(6, 10),
2040};
2041static const unsigned int msiof1_rxd_a_mux[] = {
2042 MSIOF1_RXD_A_MARK,
2043};
2044static const unsigned int msiof1_clk_b_pins[] = {
2045 /* SCK */
2046 RCAR_GP_PIN(5, 9),
2047};
2048static const unsigned int msiof1_clk_b_mux[] = {
2049 MSIOF1_SCK_B_MARK,
2050};
2051static const unsigned int msiof1_sync_b_pins[] = {
2052 /* SYNC */
2053 RCAR_GP_PIN(5, 3),
2054};
2055static const unsigned int msiof1_sync_b_mux[] = {
2056 MSIOF1_SYNC_B_MARK,
2057};
2058static const unsigned int msiof1_ss1_b_pins[] = {
2059 /* SS1 */
2060 RCAR_GP_PIN(5, 4),
2061};
2062static const unsigned int msiof1_ss1_b_mux[] = {
2063 MSIOF1_SS1_B_MARK,
2064};
2065static const unsigned int msiof1_ss2_b_pins[] = {
2066 /* SS2 */
2067 RCAR_GP_PIN(5, 0),
2068};
2069static const unsigned int msiof1_ss2_b_mux[] = {
2070 MSIOF1_SS2_B_MARK,
2071};
2072static const unsigned int msiof1_txd_b_pins[] = {
2073 /* TXD */
2074 RCAR_GP_PIN(5, 8),
2075};
2076static const unsigned int msiof1_txd_b_mux[] = {
2077 MSIOF1_TXD_B_MARK,
2078};
2079static const unsigned int msiof1_rxd_b_pins[] = {
2080 /* RXD */
2081 RCAR_GP_PIN(5, 7),
2082};
2083static const unsigned int msiof1_rxd_b_mux[] = {
2084 MSIOF1_RXD_B_MARK,
2085};
2086static const unsigned int msiof1_clk_c_pins[] = {
2087 /* SCK */
2088 RCAR_GP_PIN(6, 17),
2089};
2090static const unsigned int msiof1_clk_c_mux[] = {
2091 MSIOF1_SCK_C_MARK,
2092};
2093static const unsigned int msiof1_sync_c_pins[] = {
2094 /* SYNC */
2095 RCAR_GP_PIN(6, 18),
2096};
2097static const unsigned int msiof1_sync_c_mux[] = {
2098 MSIOF1_SYNC_C_MARK,
2099};
2100static const unsigned int msiof1_ss1_c_pins[] = {
2101 /* SS1 */
2102 RCAR_GP_PIN(6, 21),
2103};
2104static const unsigned int msiof1_ss1_c_mux[] = {
2105 MSIOF1_SS1_C_MARK,
2106};
2107static const unsigned int msiof1_ss2_c_pins[] = {
2108 /* SS2 */
2109 RCAR_GP_PIN(6, 27),
2110};
2111static const unsigned int msiof1_ss2_c_mux[] = {
2112 MSIOF1_SS2_C_MARK,
2113};
2114static const unsigned int msiof1_txd_c_pins[] = {
2115 /* TXD */
2116 RCAR_GP_PIN(6, 20),
2117};
2118static const unsigned int msiof1_txd_c_mux[] = {
2119 MSIOF1_TXD_C_MARK,
2120};
2121static const unsigned int msiof1_rxd_c_pins[] = {
2122 /* RXD */
2123 RCAR_GP_PIN(6, 19),
2124};
2125static const unsigned int msiof1_rxd_c_mux[] = {
2126 MSIOF1_RXD_C_MARK,
2127};
2128static const unsigned int msiof1_clk_d_pins[] = {
2129 /* SCK */
2130 RCAR_GP_PIN(5, 12),
2131};
2132static const unsigned int msiof1_clk_d_mux[] = {
2133 MSIOF1_SCK_D_MARK,
2134};
2135static const unsigned int msiof1_sync_d_pins[] = {
2136 /* SYNC */
2137 RCAR_GP_PIN(5, 15),
2138};
2139static const unsigned int msiof1_sync_d_mux[] = {
2140 MSIOF1_SYNC_D_MARK,
2141};
2142static const unsigned int msiof1_ss1_d_pins[] = {
2143 /* SS1 */
2144 RCAR_GP_PIN(5, 16),
2145};
2146static const unsigned int msiof1_ss1_d_mux[] = {
2147 MSIOF1_SS1_D_MARK,
2148};
2149static const unsigned int msiof1_ss2_d_pins[] = {
2150 /* SS2 */
2151 RCAR_GP_PIN(5, 21),
2152};
2153static const unsigned int msiof1_ss2_d_mux[] = {
2154 MSIOF1_SS2_D_MARK,
2155};
2156static const unsigned int msiof1_txd_d_pins[] = {
2157 /* TXD */
2158 RCAR_GP_PIN(5, 14),
2159};
2160static const unsigned int msiof1_txd_d_mux[] = {
2161 MSIOF1_TXD_D_MARK,
2162};
2163static const unsigned int msiof1_rxd_d_pins[] = {
2164 /* RXD */
2165 RCAR_GP_PIN(5, 13),
2166};
2167static const unsigned int msiof1_rxd_d_mux[] = {
2168 MSIOF1_RXD_D_MARK,
2169};
2170static const unsigned int msiof1_clk_e_pins[] = {
2171 /* SCK */
2172 RCAR_GP_PIN(3, 0),
2173};
2174static const unsigned int msiof1_clk_e_mux[] = {
2175 MSIOF1_SCK_E_MARK,
2176};
2177static const unsigned int msiof1_sync_e_pins[] = {
2178 /* SYNC */
2179 RCAR_GP_PIN(3, 1),
2180};
2181static const unsigned int msiof1_sync_e_mux[] = {
2182 MSIOF1_SYNC_E_MARK,
2183};
2184static const unsigned int msiof1_ss1_e_pins[] = {
2185 /* SS1 */
2186 RCAR_GP_PIN(3, 4),
2187};
2188static const unsigned int msiof1_ss1_e_mux[] = {
2189 MSIOF1_SS1_E_MARK,
2190};
2191static const unsigned int msiof1_ss2_e_pins[] = {
2192 /* SS2 */
2193 RCAR_GP_PIN(3, 5),
2194};
2195static const unsigned int msiof1_ss2_e_mux[] = {
2196 MSIOF1_SS2_E_MARK,
2197};
2198static const unsigned int msiof1_txd_e_pins[] = {
2199 /* TXD */
2200 RCAR_GP_PIN(3, 3),
2201};
2202static const unsigned int msiof1_txd_e_mux[] = {
2203 MSIOF1_TXD_E_MARK,
2204};
2205static const unsigned int msiof1_rxd_e_pins[] = {
2206 /* RXD */
2207 RCAR_GP_PIN(3, 2),
2208};
2209static const unsigned int msiof1_rxd_e_mux[] = {
2210 MSIOF1_RXD_E_MARK,
2211};
2212static const unsigned int msiof1_clk_f_pins[] = {
2213 /* SCK */
2214 RCAR_GP_PIN(5, 23),
2215};
2216static const unsigned int msiof1_clk_f_mux[] = {
2217 MSIOF1_SCK_F_MARK,
2218};
2219static const unsigned int msiof1_sync_f_pins[] = {
2220 /* SYNC */
2221 RCAR_GP_PIN(5, 24),
2222};
2223static const unsigned int msiof1_sync_f_mux[] = {
2224 MSIOF1_SYNC_F_MARK,
2225};
2226static const unsigned int msiof1_ss1_f_pins[] = {
2227 /* SS1 */
2228 RCAR_GP_PIN(6, 1),
2229};
2230static const unsigned int msiof1_ss1_f_mux[] = {
2231 MSIOF1_SS1_F_MARK,
2232};
2233static const unsigned int msiof1_ss2_f_pins[] = {
2234 /* SS2 */
2235 RCAR_GP_PIN(6, 2),
2236};
2237static const unsigned int msiof1_ss2_f_mux[] = {
2238 MSIOF1_SS2_F_MARK,
2239};
2240static const unsigned int msiof1_txd_f_pins[] = {
2241 /* TXD */
2242 RCAR_GP_PIN(6, 0),
2243};
2244static const unsigned int msiof1_txd_f_mux[] = {
2245 MSIOF1_TXD_F_MARK,
2246};
2247static const unsigned int msiof1_rxd_f_pins[] = {
2248 /* RXD */
2249 RCAR_GP_PIN(5, 25),
2250};
2251static const unsigned int msiof1_rxd_f_mux[] = {
2252 MSIOF1_RXD_F_MARK,
2253};
2254static const unsigned int msiof1_clk_g_pins[] = {
2255 /* SCK */
2256 RCAR_GP_PIN(3, 6),
2257};
2258static const unsigned int msiof1_clk_g_mux[] = {
2259 MSIOF1_SCK_G_MARK,
2260};
2261static const unsigned int msiof1_sync_g_pins[] = {
2262 /* SYNC */
2263 RCAR_GP_PIN(3, 7),
2264};
2265static const unsigned int msiof1_sync_g_mux[] = {
2266 MSIOF1_SYNC_G_MARK,
2267};
2268static const unsigned int msiof1_ss1_g_pins[] = {
2269 /* SS1 */
2270 RCAR_GP_PIN(3, 10),
2271};
2272static const unsigned int msiof1_ss1_g_mux[] = {
2273 MSIOF1_SS1_G_MARK,
2274};
2275static const unsigned int msiof1_ss2_g_pins[] = {
2276 /* SS2 */
2277 RCAR_GP_PIN(3, 11),
2278};
2279static const unsigned int msiof1_ss2_g_mux[] = {
2280 MSIOF1_SS2_G_MARK,
2281};
2282static const unsigned int msiof1_txd_g_pins[] = {
2283 /* TXD */
2284 RCAR_GP_PIN(3, 9),
2285};
2286static const unsigned int msiof1_txd_g_mux[] = {
2287 MSIOF1_TXD_G_MARK,
2288};
2289static const unsigned int msiof1_rxd_g_pins[] = {
2290 /* RXD */
2291 RCAR_GP_PIN(3, 8),
2292};
2293static const unsigned int msiof1_rxd_g_mux[] = {
2294 MSIOF1_RXD_G_MARK,
2295};
2296/* - MSIOF2 ----------------------------------------------------------------- */
2297static const unsigned int msiof2_clk_a_pins[] = {
2298 /* SCK */
2299 RCAR_GP_PIN(1, 9),
2300};
2301static const unsigned int msiof2_clk_a_mux[] = {
2302 MSIOF2_SCK_A_MARK,
2303};
2304static const unsigned int msiof2_sync_a_pins[] = {
2305 /* SYNC */
2306 RCAR_GP_PIN(1, 8),
2307};
2308static const unsigned int msiof2_sync_a_mux[] = {
2309 MSIOF2_SYNC_A_MARK,
2310};
2311static const unsigned int msiof2_ss1_a_pins[] = {
2312 /* SS1 */
2313 RCAR_GP_PIN(1, 6),
2314};
2315static const unsigned int msiof2_ss1_a_mux[] = {
2316 MSIOF2_SS1_A_MARK,
2317};
2318static const unsigned int msiof2_ss2_a_pins[] = {
2319 /* SS2 */
2320 RCAR_GP_PIN(1, 7),
2321};
2322static const unsigned int msiof2_ss2_a_mux[] = {
2323 MSIOF2_SS2_A_MARK,
2324};
2325static const unsigned int msiof2_txd_a_pins[] = {
2326 /* TXD */
2327 RCAR_GP_PIN(1, 11),
2328};
2329static const unsigned int msiof2_txd_a_mux[] = {
2330 MSIOF2_TXD_A_MARK,
2331};
2332static const unsigned int msiof2_rxd_a_pins[] = {
2333 /* RXD */
2334 RCAR_GP_PIN(1, 10),
2335};
2336static const unsigned int msiof2_rxd_a_mux[] = {
2337 MSIOF2_RXD_A_MARK,
2338};
2339static const unsigned int msiof2_clk_b_pins[] = {
2340 /* SCK */
2341 RCAR_GP_PIN(0, 4),
2342};
2343static const unsigned int msiof2_clk_b_mux[] = {
2344 MSIOF2_SCK_B_MARK,
2345};
2346static const unsigned int msiof2_sync_b_pins[] = {
2347 /* SYNC */
2348 RCAR_GP_PIN(0, 5),
2349};
2350static const unsigned int msiof2_sync_b_mux[] = {
2351 MSIOF2_SYNC_B_MARK,
2352};
2353static const unsigned int msiof2_ss1_b_pins[] = {
2354 /* SS1 */
2355 RCAR_GP_PIN(0, 0),
2356};
2357static const unsigned int msiof2_ss1_b_mux[] = {
2358 MSIOF2_SS1_B_MARK,
2359};
2360static const unsigned int msiof2_ss2_b_pins[] = {
2361 /* SS2 */
2362 RCAR_GP_PIN(0, 1),
2363};
2364static const unsigned int msiof2_ss2_b_mux[] = {
2365 MSIOF2_SS2_B_MARK,
2366};
2367static const unsigned int msiof2_txd_b_pins[] = {
2368 /* TXD */
2369 RCAR_GP_PIN(0, 7),
2370};
2371static const unsigned int msiof2_txd_b_mux[] = {
2372 MSIOF2_TXD_B_MARK,
2373};
2374static const unsigned int msiof2_rxd_b_pins[] = {
2375 /* RXD */
2376 RCAR_GP_PIN(0, 6),
2377};
2378static const unsigned int msiof2_rxd_b_mux[] = {
2379 MSIOF2_RXD_B_MARK,
2380};
2381static const unsigned int msiof2_clk_c_pins[] = {
2382 /* SCK */
2383 RCAR_GP_PIN(2, 12),
2384};
2385static const unsigned int msiof2_clk_c_mux[] = {
2386 MSIOF2_SCK_C_MARK,
2387};
2388static const unsigned int msiof2_sync_c_pins[] = {
2389 /* SYNC */
2390 RCAR_GP_PIN(2, 11),
2391};
2392static const unsigned int msiof2_sync_c_mux[] = {
2393 MSIOF2_SYNC_C_MARK,
2394};
2395static const unsigned int msiof2_ss1_c_pins[] = {
2396 /* SS1 */
2397 RCAR_GP_PIN(2, 10),
2398};
2399static const unsigned int msiof2_ss1_c_mux[] = {
2400 MSIOF2_SS1_C_MARK,
2401};
2402static const unsigned int msiof2_ss2_c_pins[] = {
2403 /* SS2 */
2404 RCAR_GP_PIN(2, 9),
2405};
2406static const unsigned int msiof2_ss2_c_mux[] = {
2407 MSIOF2_SS2_C_MARK,
2408};
2409static const unsigned int msiof2_txd_c_pins[] = {
2410 /* TXD */
2411 RCAR_GP_PIN(2, 14),
2412};
2413static const unsigned int msiof2_txd_c_mux[] = {
2414 MSIOF2_TXD_C_MARK,
2415};
2416static const unsigned int msiof2_rxd_c_pins[] = {
2417 /* RXD */
2418 RCAR_GP_PIN(2, 13),
2419};
2420static const unsigned int msiof2_rxd_c_mux[] = {
2421 MSIOF2_RXD_C_MARK,
2422};
2423static const unsigned int msiof2_clk_d_pins[] = {
2424 /* SCK */
2425 RCAR_GP_PIN(0, 8),
2426};
2427static const unsigned int msiof2_clk_d_mux[] = {
2428 MSIOF2_SCK_D_MARK,
2429};
2430static const unsigned int msiof2_sync_d_pins[] = {
2431 /* SYNC */
2432 RCAR_GP_PIN(0, 9),
2433};
2434static const unsigned int msiof2_sync_d_mux[] = {
2435 MSIOF2_SYNC_D_MARK,
2436};
2437static const unsigned int msiof2_ss1_d_pins[] = {
2438 /* SS1 */
2439 RCAR_GP_PIN(0, 12),
2440};
2441static const unsigned int msiof2_ss1_d_mux[] = {
2442 MSIOF2_SS1_D_MARK,
2443};
2444static const unsigned int msiof2_ss2_d_pins[] = {
2445 /* SS2 */
2446 RCAR_GP_PIN(0, 13),
2447};
2448static const unsigned int msiof2_ss2_d_mux[] = {
2449 MSIOF2_SS2_D_MARK,
2450};
2451static const unsigned int msiof2_txd_d_pins[] = {
2452 /* TXD */
2453 RCAR_GP_PIN(0, 11),
2454};
2455static const unsigned int msiof2_txd_d_mux[] = {
2456 MSIOF2_TXD_D_MARK,
2457};
2458static const unsigned int msiof2_rxd_d_pins[] = {
2459 /* RXD */
2460 RCAR_GP_PIN(0, 10),
2461};
2462static const unsigned int msiof2_rxd_d_mux[] = {
2463 MSIOF2_RXD_D_MARK,
2464};
2465/* - MSIOF3 ----------------------------------------------------------------- */
2466static const unsigned int msiof3_clk_a_pins[] = {
2467 /* SCK */
2468 RCAR_GP_PIN(0, 0),
2469};
2470static const unsigned int msiof3_clk_a_mux[] = {
2471 MSIOF3_SCK_A_MARK,
2472};
2473static const unsigned int msiof3_sync_a_pins[] = {
2474 /* SYNC */
2475 RCAR_GP_PIN(0, 1),
2476};
2477static const unsigned int msiof3_sync_a_mux[] = {
2478 MSIOF3_SYNC_A_MARK,
2479};
2480static const unsigned int msiof3_ss1_a_pins[] = {
2481 /* SS1 */
2482 RCAR_GP_PIN(0, 14),
2483};
2484static const unsigned int msiof3_ss1_a_mux[] = {
2485 MSIOF3_SS1_A_MARK,
2486};
2487static const unsigned int msiof3_ss2_a_pins[] = {
2488 /* SS2 */
2489 RCAR_GP_PIN(0, 15),
2490};
2491static const unsigned int msiof3_ss2_a_mux[] = {
2492 MSIOF3_SS2_A_MARK,
2493};
2494static const unsigned int msiof3_txd_a_pins[] = {
2495 /* TXD */
2496 RCAR_GP_PIN(0, 3),
2497};
2498static const unsigned int msiof3_txd_a_mux[] = {
2499 MSIOF3_TXD_A_MARK,
2500};
2501static const unsigned int msiof3_rxd_a_pins[] = {
2502 /* RXD */
2503 RCAR_GP_PIN(0, 2),
2504};
2505static const unsigned int msiof3_rxd_a_mux[] = {
2506 MSIOF3_RXD_A_MARK,
2507};
2508static const unsigned int msiof3_clk_b_pins[] = {
2509 /* SCK */
2510 RCAR_GP_PIN(1, 2),
2511};
2512static const unsigned int msiof3_clk_b_mux[] = {
2513 MSIOF3_SCK_B_MARK,
2514};
2515static const unsigned int msiof3_sync_b_pins[] = {
2516 /* SYNC */
2517 RCAR_GP_PIN(1, 0),
2518};
2519static const unsigned int msiof3_sync_b_mux[] = {
2520 MSIOF3_SYNC_B_MARK,
2521};
2522static const unsigned int msiof3_ss1_b_pins[] = {
2523 /* SS1 */
2524 RCAR_GP_PIN(1, 4),
2525};
2526static const unsigned int msiof3_ss1_b_mux[] = {
2527 MSIOF3_SS1_B_MARK,
2528};
2529static const unsigned int msiof3_ss2_b_pins[] = {
2530 /* SS2 */
2531 RCAR_GP_PIN(1, 5),
2532};
2533static const unsigned int msiof3_ss2_b_mux[] = {
2534 MSIOF3_SS2_B_MARK,
2535};
2536static const unsigned int msiof3_txd_b_pins[] = {
2537 /* TXD */
2538 RCAR_GP_PIN(1, 1),
2539};
2540static const unsigned int msiof3_txd_b_mux[] = {
2541 MSIOF3_TXD_B_MARK,
2542};
2543static const unsigned int msiof3_rxd_b_pins[] = {
2544 /* RXD */
2545 RCAR_GP_PIN(1, 3),
2546};
2547static const unsigned int msiof3_rxd_b_mux[] = {
2548 MSIOF3_RXD_B_MARK,
2549};
2550static const unsigned int msiof3_clk_c_pins[] = {
2551 /* SCK */
2552 RCAR_GP_PIN(1, 12),
2553};
2554static const unsigned int msiof3_clk_c_mux[] = {
2555 MSIOF3_SCK_C_MARK,
2556};
2557static const unsigned int msiof3_sync_c_pins[] = {
2558 /* SYNC */
2559 RCAR_GP_PIN(1, 13),
2560};
2561static const unsigned int msiof3_sync_c_mux[] = {
2562 MSIOF3_SYNC_C_MARK,
2563};
2564static const unsigned int msiof3_txd_c_pins[] = {
2565 /* TXD */
2566 RCAR_GP_PIN(1, 15),
2567};
2568static const unsigned int msiof3_txd_c_mux[] = {
2569 MSIOF3_TXD_C_MARK,
2570};
2571static const unsigned int msiof3_rxd_c_pins[] = {
2572 /* RXD */
2573 RCAR_GP_PIN(1, 14),
2574};
2575static const unsigned int msiof3_rxd_c_mux[] = {
2576 MSIOF3_RXD_C_MARK,
2577};
2578static const unsigned int msiof3_clk_d_pins[] = {
2579 /* SCK */
2580 RCAR_GP_PIN(1, 22),
2581};
2582static const unsigned int msiof3_clk_d_mux[] = {
2583 MSIOF3_SCK_D_MARK,
2584};
2585static const unsigned int msiof3_sync_d_pins[] = {
2586 /* SYNC */
2587 RCAR_GP_PIN(1, 23),
2588};
2589static const unsigned int msiof3_sync_d_mux[] = {
2590 MSIOF3_SYNC_D_MARK,
2591};
2592static const unsigned int msiof3_ss1_d_pins[] = {
2593 /* SS1 */
2594 RCAR_GP_PIN(1, 26),
2595};
2596static const unsigned int msiof3_ss1_d_mux[] = {
2597 MSIOF3_SS1_D_MARK,
2598};
2599static const unsigned int msiof3_txd_d_pins[] = {
2600 /* TXD */
2601 RCAR_GP_PIN(1, 25),
2602};
2603static const unsigned int msiof3_txd_d_mux[] = {
2604 MSIOF3_TXD_D_MARK,
2605};
2606static const unsigned int msiof3_rxd_d_pins[] = {
2607 /* RXD */
2608 RCAR_GP_PIN(1, 24),
2609};
2610static const unsigned int msiof3_rxd_d_mux[] = {
2611 MSIOF3_RXD_D_MARK,
2612};
2613static const unsigned int msiof3_clk_e_pins[] = {
2614 /* SCK */
2615 RCAR_GP_PIN(2, 3),
2616};
2617static const unsigned int msiof3_clk_e_mux[] = {
2618 MSIOF3_SCK_E_MARK,
2619};
2620static const unsigned int msiof3_sync_e_pins[] = {
2621 /* SYNC */
2622 RCAR_GP_PIN(2, 2),
2623};
2624static const unsigned int msiof3_sync_e_mux[] = {
2625 MSIOF3_SYNC_E_MARK,
2626};
2627static const unsigned int msiof3_ss1_e_pins[] = {
2628 /* SS1 */
2629 RCAR_GP_PIN(2, 1),
2630};
2631static const unsigned int msiof3_ss1_e_mux[] = {
2632 MSIOF3_SS1_E_MARK,
2633};
2634static const unsigned int msiof3_ss2_e_pins[] = {
2635 /* SS1 */
2636 RCAR_GP_PIN(2, 0),
2637};
2638static const unsigned int msiof3_ss2_e_mux[] = {
2639 MSIOF3_SS2_E_MARK,
2640};
2641static const unsigned int msiof3_txd_e_pins[] = {
2642 /* TXD */
2643 RCAR_GP_PIN(2, 5),
2644};
2645static const unsigned int msiof3_txd_e_mux[] = {
2646 MSIOF3_TXD_E_MARK,
2647};
2648static const unsigned int msiof3_rxd_e_pins[] = {
2649 /* RXD */
2650 RCAR_GP_PIN(2, 4),
2651};
2652static const unsigned int msiof3_rxd_e_mux[] = {
2653 MSIOF3_RXD_E_MARK,
2654};
2655
2656/* - PWM0 --------------------------------------------------------------------*/
2657static const unsigned int pwm0_pins[] = {
2658 /* PWM */
2659 RCAR_GP_PIN(2, 6),
2660};
2661static const unsigned int pwm0_mux[] = {
2662 PWM0_MARK,
2663};
2664/* - PWM1 --------------------------------------------------------------------*/
2665static const unsigned int pwm1_a_pins[] = {
2666 /* PWM */
2667 RCAR_GP_PIN(2, 7),
2668};
2669static const unsigned int pwm1_a_mux[] = {
2670 PWM1_A_MARK,
2671};
2672static const unsigned int pwm1_b_pins[] = {
2673 /* PWM */
2674 RCAR_GP_PIN(1, 8),
2675};
2676static const unsigned int pwm1_b_mux[] = {
2677 PWM1_B_MARK,
2678};
2679/* - PWM2 --------------------------------------------------------------------*/
2680static const unsigned int pwm2_a_pins[] = {
2681 /* PWM */
2682 RCAR_GP_PIN(2, 8),
2683};
2684static const unsigned int pwm2_a_mux[] = {
2685 PWM2_A_MARK,
2686};
2687static const unsigned int pwm2_b_pins[] = {
2688 /* PWM */
2689 RCAR_GP_PIN(1, 11),
2690};
2691static const unsigned int pwm2_b_mux[] = {
2692 PWM2_B_MARK,
2693};
2694/* - PWM3 --------------------------------------------------------------------*/
2695static const unsigned int pwm3_a_pins[] = {
2696 /* PWM */
2697 RCAR_GP_PIN(1, 0),
2698};
2699static const unsigned int pwm3_a_mux[] = {
2700 PWM3_A_MARK,
2701};
2702static const unsigned int pwm3_b_pins[] = {
2703 /* PWM */
2704 RCAR_GP_PIN(2, 2),
2705};
2706static const unsigned int pwm3_b_mux[] = {
2707 PWM3_B_MARK,
2708};
2709/* - PWM4 --------------------------------------------------------------------*/
2710static const unsigned int pwm4_a_pins[] = {
2711 /* PWM */
2712 RCAR_GP_PIN(1, 1),
2713};
2714static const unsigned int pwm4_a_mux[] = {
2715 PWM4_A_MARK,
2716};
2717static const unsigned int pwm4_b_pins[] = {
2718 /* PWM */
2719 RCAR_GP_PIN(2, 3),
2720};
2721static const unsigned int pwm4_b_mux[] = {
2722 PWM4_B_MARK,
2723};
2724/* - PWM5 --------------------------------------------------------------------*/
2725static const unsigned int pwm5_a_pins[] = {
2726 /* PWM */
2727 RCAR_GP_PIN(1, 2),
2728};
2729static const unsigned int pwm5_a_mux[] = {
2730 PWM5_A_MARK,
2731};
2732static const unsigned int pwm5_b_pins[] = {
2733 /* PWM */
2734 RCAR_GP_PIN(2, 4),
2735};
2736static const unsigned int pwm5_b_mux[] = {
2737 PWM5_B_MARK,
2738};
2739/* - PWM6 --------------------------------------------------------------------*/
2740static const unsigned int pwm6_a_pins[] = {
2741 /* PWM */
2742 RCAR_GP_PIN(1, 3),
2743};
2744static const unsigned int pwm6_a_mux[] = {
2745 PWM6_A_MARK,
2746};
2747static const unsigned int pwm6_b_pins[] = {
2748 /* PWM */
2749 RCAR_GP_PIN(2, 5),
2750};
2751static const unsigned int pwm6_b_mux[] = {
2752 PWM6_B_MARK,
2753};
2754
2755/* - SCIF0 ------------------------------------------------------------------ */
2756static const unsigned int scif0_data_pins[] = {
2757 /* RX, TX */
2758 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2759};
2760static const unsigned int scif0_data_mux[] = {
2761 RX0_MARK, TX0_MARK,
2762};
2763static const unsigned int scif0_clk_pins[] = {
2764 /* SCK */
2765 RCAR_GP_PIN(5, 0),
2766};
2767static const unsigned int scif0_clk_mux[] = {
2768 SCK0_MARK,
2769};
2770static const unsigned int scif0_ctrl_pins[] = {
2771 /* RTS, CTS */
2772 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2773};
2774static const unsigned int scif0_ctrl_mux[] = {
2775 RTS0_N_TANS_MARK, CTS0_N_MARK,
2776};
2777/* - SCIF1 ------------------------------------------------------------------ */
2778static const unsigned int scif1_data_a_pins[] = {
2779 /* RX, TX */
2780 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2781};
2782static const unsigned int scif1_data_a_mux[] = {
2783 RX1_A_MARK, TX1_A_MARK,
2784};
2785static const unsigned int scif1_clk_pins[] = {
2786 /* SCK */
2787 RCAR_GP_PIN(6, 21),
2788};
2789static const unsigned int scif1_clk_mux[] = {
2790 SCK1_MARK,
2791};
2792static const unsigned int scif1_ctrl_pins[] = {
2793 /* RTS, CTS */
2794 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2795};
2796static const unsigned int scif1_ctrl_mux[] = {
2797 RTS1_N_TANS_MARK, CTS1_N_MARK,
2798};
2799
2800static const unsigned int scif1_data_b_pins[] = {
2801 /* RX, TX */
2802 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2803};
2804static const unsigned int scif1_data_b_mux[] = {
2805 RX1_B_MARK, TX1_B_MARK,
2806};
2807/* - SCIF2 ------------------------------------------------------------------ */
2808static const unsigned int scif2_data_a_pins[] = {
2809 /* RX, TX */
2810 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2811};
2812static const unsigned int scif2_data_a_mux[] = {
2813 RX2_A_MARK, TX2_A_MARK,
2814};
2815static const unsigned int scif2_clk_pins[] = {
2816 /* SCK */
2817 RCAR_GP_PIN(5, 9),
2818};
2819static const unsigned int scif2_clk_mux[] = {
2820 SCK2_MARK,
2821};
2822static const unsigned int scif2_data_b_pins[] = {
2823 /* RX, TX */
2824 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2825};
2826static const unsigned int scif2_data_b_mux[] = {
2827 RX2_B_MARK, TX2_B_MARK,
2828};
2829/* - SCIF3 ------------------------------------------------------------------ */
2830static const unsigned int scif3_data_a_pins[] = {
2831 /* RX, TX */
2832 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2833};
2834static const unsigned int scif3_data_a_mux[] = {
2835 RX3_A_MARK, TX3_A_MARK,
2836};
2837static const unsigned int scif3_clk_pins[] = {
2838 /* SCK */
2839 RCAR_GP_PIN(1, 22),
2840};
2841static const unsigned int scif3_clk_mux[] = {
2842 SCK3_MARK,
2843};
2844static const unsigned int scif3_ctrl_pins[] = {
2845 /* RTS, CTS */
2846 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2847};
2848static const unsigned int scif3_ctrl_mux[] = {
2849 RTS3_N_TANS_MARK, CTS3_N_MARK,
2850};
2851static const unsigned int scif3_data_b_pins[] = {
2852 /* RX, TX */
2853 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2854};
2855static const unsigned int scif3_data_b_mux[] = {
2856 RX3_B_MARK, TX3_B_MARK,
2857};
2858/* - SCIF4 ------------------------------------------------------------------ */
2859static const unsigned int scif4_data_a_pins[] = {
2860 /* RX, TX */
2861 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2862};
2863static const unsigned int scif4_data_a_mux[] = {
2864 RX4_A_MARK, TX4_A_MARK,
2865};
2866static const unsigned int scif4_clk_a_pins[] = {
2867 /* SCK */
2868 RCAR_GP_PIN(2, 10),
2869};
2870static const unsigned int scif4_clk_a_mux[] = {
2871 SCK4_A_MARK,
2872};
2873static const unsigned int scif4_ctrl_a_pins[] = {
2874 /* RTS, CTS */
2875 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2876};
2877static const unsigned int scif4_ctrl_a_mux[] = {
2878 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
2879};
2880static const unsigned int scif4_data_b_pins[] = {
2881 /* RX, TX */
2882 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2883};
2884static const unsigned int scif4_data_b_mux[] = {
2885 RX4_B_MARK, TX4_B_MARK,
2886};
2887static const unsigned int scif4_clk_b_pins[] = {
2888 /* SCK */
2889 RCAR_GP_PIN(1, 5),
2890};
2891static const unsigned int scif4_clk_b_mux[] = {
2892 SCK4_B_MARK,
2893};
2894static const unsigned int scif4_ctrl_b_pins[] = {
2895 /* RTS, CTS */
2896 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
2897};
2898static const unsigned int scif4_ctrl_b_mux[] = {
2899 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
2900};
2901static const unsigned int scif4_data_c_pins[] = {
2902 /* RX, TX */
2903 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2904};
2905static const unsigned int scif4_data_c_mux[] = {
2906 RX4_C_MARK, TX4_C_MARK,
2907};
2908static const unsigned int scif4_clk_c_pins[] = {
2909 /* SCK */
2910 RCAR_GP_PIN(0, 8),
2911};
2912static const unsigned int scif4_clk_c_mux[] = {
2913 SCK4_C_MARK,
2914};
2915static const unsigned int scif4_ctrl_c_pins[] = {
2916 /* RTS, CTS */
2917 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2918};
2919static const unsigned int scif4_ctrl_c_mux[] = {
2920 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
2921};
2922/* - SCIF5 ------------------------------------------------------------------ */
2923static const unsigned int scif5_data_a_pins[] = {
2924 /* RX, TX */
2925 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2926};
2927static const unsigned int scif5_data_a_mux[] = {
2928 RX5_A_MARK, TX5_A_MARK,
2929};
2930static const unsigned int scif5_clk_a_pins[] = {
2931 /* SCK */
2932 RCAR_GP_PIN(6, 21),
2933};
2934static const unsigned int scif5_clk_a_mux[] = {
2935 SCK5_A_MARK,
2936};
2937static const unsigned int scif5_data_b_pins[] = {
2938 /* RX, TX */
2939 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
2940};
2941static const unsigned int scif5_data_b_mux[] = {
2942 RX5_B_MARK, TX5_B_MARK,
2943};
2944static const unsigned int scif5_clk_b_pins[] = {
2945 /* SCK */
2946 RCAR_GP_PIN(5, 0),
2947};
2948static const unsigned int scif5_clk_b_mux[] = {
2949 SCK5_B_MARK,
2950};
2951
2952/* - SDHI0 ------------------------------------------------------------------ */
2953static const unsigned int sdhi0_data1_pins[] = {
2954 /* D0 */
2955 RCAR_GP_PIN(3, 2),
2956};
2957static const unsigned int sdhi0_data1_mux[] = {
2958 SD0_DAT0_MARK,
2959};
2960static const unsigned int sdhi0_data4_pins[] = {
2961 /* D[0:3] */
2962 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2963 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2964};
2965static const unsigned int sdhi0_data4_mux[] = {
2966 SD0_DAT0_MARK, SD0_DAT1_MARK,
2967 SD0_DAT2_MARK, SD0_DAT3_MARK,
2968};
2969static const unsigned int sdhi0_ctrl_pins[] = {
2970 /* CLK, CMD */
2971 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2972};
2973static const unsigned int sdhi0_ctrl_mux[] = {
2974 SD0_CLK_MARK, SD0_CMD_MARK,
2975};
2976static const unsigned int sdhi0_cd_pins[] = {
2977 /* CD */
2978 RCAR_GP_PIN(3, 12),
2979};
2980static const unsigned int sdhi0_cd_mux[] = {
2981 SD0_CD_MARK,
2982};
2983static const unsigned int sdhi0_wp_pins[] = {
2984 /* WP */
2985 RCAR_GP_PIN(3, 13),
2986};
2987static const unsigned int sdhi0_wp_mux[] = {
2988 SD0_WP_MARK,
2989};
2990/* - SDHI1 ------------------------------------------------------------------ */
2991static const unsigned int sdhi1_data1_pins[] = {
2992 /* D0 */
2993 RCAR_GP_PIN(3, 8),
2994};
2995static const unsigned int sdhi1_data1_mux[] = {
2996 SD1_DAT0_MARK,
2997};
2998static const unsigned int sdhi1_data4_pins[] = {
2999 /* D[0:3] */
3000 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3001 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3002};
3003static const unsigned int sdhi1_data4_mux[] = {
3004 SD1_DAT0_MARK, SD1_DAT1_MARK,
3005 SD1_DAT2_MARK, SD1_DAT3_MARK,
3006};
3007static const unsigned int sdhi1_ctrl_pins[] = {
3008 /* CLK, CMD */
3009 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3010};
3011static const unsigned int sdhi1_ctrl_mux[] = {
3012 SD1_CLK_MARK, SD1_CMD_MARK,
3013};
3014static const unsigned int sdhi1_cd_pins[] = {
3015 /* CD */
3016 RCAR_GP_PIN(3, 14),
3017};
3018static const unsigned int sdhi1_cd_mux[] = {
3019 SD1_CD_MARK,
3020};
3021static const unsigned int sdhi1_wp_pins[] = {
3022 /* WP */
3023 RCAR_GP_PIN(3, 15),
3024};
3025static const unsigned int sdhi1_wp_mux[] = {
3026 SD1_WP_MARK,
3027};
3028/* - SDHI2 ------------------------------------------------------------------ */
3029static const unsigned int sdhi2_data1_pins[] = {
3030 /* D0 */
3031 RCAR_GP_PIN(4, 2),
3032};
3033static const unsigned int sdhi2_data1_mux[] = {
3034 SD2_DAT0_MARK,
3035};
3036static const unsigned int sdhi2_data4_pins[] = {
3037 /* D[0:3] */
3038 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3039 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3040};
3041static const unsigned int sdhi2_data4_mux[] = {
3042 SD2_DAT0_MARK, SD2_DAT1_MARK,
3043 SD2_DAT2_MARK, SD2_DAT3_MARK,
3044};
3045static const unsigned int sdhi2_data8_pins[] = {
3046 /* D[0:7] */
3047 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3048 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3049 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3050 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3051};
3052static const unsigned int sdhi2_data8_mux[] = {
3053 SD2_DAT0_MARK, SD2_DAT1_MARK,
3054 SD2_DAT2_MARK, SD2_DAT3_MARK,
3055 SD2_DAT4_MARK, SD2_DAT5_MARK,
3056 SD2_DAT6_MARK, SD2_DAT7_MARK,
3057};
3058static const unsigned int sdhi2_ctrl_pins[] = {
3059 /* CLK, CMD */
3060 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3061};
3062static const unsigned int sdhi2_ctrl_mux[] = {
3063 SD2_CLK_MARK, SD2_CMD_MARK,
3064};
3065static const unsigned int sdhi2_cd_a_pins[] = {
3066 /* CD */
3067 RCAR_GP_PIN(4, 13),
3068};
3069static const unsigned int sdhi2_cd_a_mux[] = {
3070 SD2_CD_A_MARK,
3071};
3072static const unsigned int sdhi2_cd_b_pins[] = {
3073 /* CD */
3074 RCAR_GP_PIN(5, 10),
3075};
3076static const unsigned int sdhi2_cd_b_mux[] = {
3077 SD2_CD_B_MARK,
3078};
3079static const unsigned int sdhi2_wp_a_pins[] = {
3080 /* WP */
3081 RCAR_GP_PIN(4, 14),
3082};
3083static const unsigned int sdhi2_wp_a_mux[] = {
3084 SD2_WP_A_MARK,
3085};
3086static const unsigned int sdhi2_wp_b_pins[] = {
3087 /* WP */
3088 RCAR_GP_PIN(5, 11),
3089};
3090static const unsigned int sdhi2_wp_b_mux[] = {
3091 SD2_WP_B_MARK,
3092};
3093static const unsigned int sdhi2_ds_pins[] = {
3094 /* DS */
3095 RCAR_GP_PIN(4, 6),
3096};
3097static const unsigned int sdhi2_ds_mux[] = {
3098 SD2_DS_MARK,
3099};
3100/* - SDHI3 ------------------------------------------------------------------ */
3101static const unsigned int sdhi3_data1_pins[] = {
3102 /* D0 */
3103 RCAR_GP_PIN(4, 9),
3104};
3105static const unsigned int sdhi3_data1_mux[] = {
3106 SD3_DAT0_MARK,
3107};
3108static const unsigned int sdhi3_data4_pins[] = {
3109 /* D[0:3] */
3110 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3111 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3112};
3113static const unsigned int sdhi3_data4_mux[] = {
3114 SD3_DAT0_MARK, SD3_DAT1_MARK,
3115 SD3_DAT2_MARK, SD3_DAT3_MARK,
3116};
3117static const unsigned int sdhi3_data8_pins[] = {
3118 /* D[0:7] */
3119 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3120 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3121 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3122 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3123};
3124static const unsigned int sdhi3_data8_mux[] = {
3125 SD3_DAT0_MARK, SD3_DAT1_MARK,
3126 SD3_DAT2_MARK, SD3_DAT3_MARK,
3127 SD3_DAT4_MARK, SD3_DAT5_MARK,
3128 SD3_DAT6_MARK, SD3_DAT7_MARK,
3129};
3130static const unsigned int sdhi3_ctrl_pins[] = {
3131 /* CLK, CMD */
3132 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3133};
3134static const unsigned int sdhi3_ctrl_mux[] = {
3135 SD3_CLK_MARK, SD3_CMD_MARK,
3136};
3137static const unsigned int sdhi3_cd_pins[] = {
3138 /* CD */
3139 RCAR_GP_PIN(4, 15),
3140};
3141static const unsigned int sdhi3_cd_mux[] = {
3142 SD3_CD_MARK,
3143};
3144static const unsigned int sdhi3_wp_pins[] = {
3145 /* WP */
3146 RCAR_GP_PIN(4, 16),
3147};
3148static const unsigned int sdhi3_wp_mux[] = {
3149 SD3_WP_MARK,
3150};
3151static const unsigned int sdhi3_ds_pins[] = {
3152 /* DS */
3153 RCAR_GP_PIN(4, 17),
3154};
3155static const unsigned int sdhi3_ds_mux[] = {
3156 SD3_DS_MARK,
3157};
3158
3159/* - SCIF Clock ------------------------------------------------------------- */
3160static const unsigned int scif_clk_a_pins[] = {
3161 /* SCIF_CLK */
3162 RCAR_GP_PIN(6, 23),
3163};
3164static const unsigned int scif_clk_a_mux[] = {
3165 SCIF_CLK_A_MARK,
3166};
3167static const unsigned int scif_clk_b_pins[] = {
3168 /* SCIF_CLK */
3169 RCAR_GP_PIN(5, 9),
3170};
3171static const unsigned int scif_clk_b_mux[] = {
3172 SCIF_CLK_B_MARK,
3173};
3174
3175/* - USB0 ------------------------------------------------------------------- */
3176static const unsigned int usb0_pins[] = {
3177 /* PWEN, OVC */
3178 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3179};
3180static const unsigned int usb0_mux[] = {
3181 USB0_PWEN_MARK, USB0_OVC_MARK,
3182};
3183/* - USB1 ------------------------------------------------------------------- */
3184static const unsigned int usb1_pins[] = {
3185 /* PWEN, OVC */
3186 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3187};
3188static const unsigned int usb1_mux[] = {
3189 USB1_PWEN_MARK, USB1_OVC_MARK,
3190};
3191/* - USB2 ------------------------------------------------------------------- */
3192static const unsigned int usb2_pins[] = {
3193 /* PWEN, OVC */
3194 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3195};
3196static const unsigned int usb2_mux[] = {
3197 USB2_PWEN_MARK, USB2_OVC_MARK,
3198};
3199/* - USB2_CH3 --------------------------------------------------------------- */
3200static const unsigned int usb2_ch3_pins[] = {
3201 /* PWEN, OVC */
3202 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3203};
3204static const unsigned int usb2_ch3_mux[] = {
3205 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3206};
3207
3208static const struct sh_pfc_pin_group pinmux_groups[] = {
3209 SH_PFC_PIN_GROUP(avb_link),
3210 SH_PFC_PIN_GROUP(avb_magic),
3211 SH_PFC_PIN_GROUP(avb_phy_int),
3212 SH_PFC_PIN_GROUP(avb_mdc),
3213 SH_PFC_PIN_GROUP(avb_mii),
3214 SH_PFC_PIN_GROUP(avb_avtp_pps),
3215 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3216 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3217 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3218 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3219 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3220 SH_PFC_PIN_GROUP(drif0_data0_a),
3221 SH_PFC_PIN_GROUP(drif0_data1_a),
3222 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3223 SH_PFC_PIN_GROUP(drif0_data0_b),
3224 SH_PFC_PIN_GROUP(drif0_data1_b),
3225 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3226 SH_PFC_PIN_GROUP(drif0_data0_c),
3227 SH_PFC_PIN_GROUP(drif0_data1_c),
3228 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3229 SH_PFC_PIN_GROUP(drif1_data0_a),
3230 SH_PFC_PIN_GROUP(drif1_data1_a),
3231 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3232 SH_PFC_PIN_GROUP(drif1_data0_b),
3233 SH_PFC_PIN_GROUP(drif1_data1_b),
3234 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3235 SH_PFC_PIN_GROUP(drif1_data0_c),
3236 SH_PFC_PIN_GROUP(drif1_data1_c),
3237 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3238 SH_PFC_PIN_GROUP(drif2_data0_a),
3239 SH_PFC_PIN_GROUP(drif2_data1_a),
3240 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3241 SH_PFC_PIN_GROUP(drif2_data0_b),
3242 SH_PFC_PIN_GROUP(drif2_data1_b),
3243 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3244 SH_PFC_PIN_GROUP(drif3_data0_a),
3245 SH_PFC_PIN_GROUP(drif3_data1_a),
3246 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3247 SH_PFC_PIN_GROUP(drif3_data0_b),
3248 SH_PFC_PIN_GROUP(drif3_data1_b),
3249 SH_PFC_PIN_GROUP(du_rgb666),
3250 SH_PFC_PIN_GROUP(du_rgb888),
3251 SH_PFC_PIN_GROUP(du_clk_out_0),
3252 SH_PFC_PIN_GROUP(du_clk_out_1),
3253 SH_PFC_PIN_GROUP(du_sync),
3254 SH_PFC_PIN_GROUP(du_oddf),
3255 SH_PFC_PIN_GROUP(du_cde),
3256 SH_PFC_PIN_GROUP(du_disp),
3257 SH_PFC_PIN_GROUP(msiof0_clk),
3258 SH_PFC_PIN_GROUP(msiof0_sync),
3259 SH_PFC_PIN_GROUP(msiof0_ss1),
3260 SH_PFC_PIN_GROUP(msiof0_ss2),
3261 SH_PFC_PIN_GROUP(msiof0_txd),
3262 SH_PFC_PIN_GROUP(msiof0_rxd),
3263 SH_PFC_PIN_GROUP(msiof1_clk_a),
3264 SH_PFC_PIN_GROUP(msiof1_sync_a),
3265 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3266 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3267 SH_PFC_PIN_GROUP(msiof1_txd_a),
3268 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3269 SH_PFC_PIN_GROUP(msiof1_clk_b),
3270 SH_PFC_PIN_GROUP(msiof1_sync_b),
3271 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3272 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3273 SH_PFC_PIN_GROUP(msiof1_txd_b),
3274 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3275 SH_PFC_PIN_GROUP(msiof1_clk_c),
3276 SH_PFC_PIN_GROUP(msiof1_sync_c),
3277 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3278 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3279 SH_PFC_PIN_GROUP(msiof1_txd_c),
3280 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3281 SH_PFC_PIN_GROUP(msiof1_clk_d),
3282 SH_PFC_PIN_GROUP(msiof1_sync_d),
3283 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3284 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3285 SH_PFC_PIN_GROUP(msiof1_txd_d),
3286 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3287 SH_PFC_PIN_GROUP(msiof1_clk_e),
3288 SH_PFC_PIN_GROUP(msiof1_sync_e),
3289 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3290 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3291 SH_PFC_PIN_GROUP(msiof1_txd_e),
3292 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3293 SH_PFC_PIN_GROUP(msiof1_clk_f),
3294 SH_PFC_PIN_GROUP(msiof1_sync_f),
3295 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3296 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3297 SH_PFC_PIN_GROUP(msiof1_txd_f),
3298 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3299 SH_PFC_PIN_GROUP(msiof1_clk_g),
3300 SH_PFC_PIN_GROUP(msiof1_sync_g),
3301 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3302 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3303 SH_PFC_PIN_GROUP(msiof1_txd_g),
3304 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3305 SH_PFC_PIN_GROUP(msiof2_clk_a),
3306 SH_PFC_PIN_GROUP(msiof2_sync_a),
3307 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3308 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3309 SH_PFC_PIN_GROUP(msiof2_txd_a),
3310 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3311 SH_PFC_PIN_GROUP(msiof2_clk_b),
3312 SH_PFC_PIN_GROUP(msiof2_sync_b),
3313 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3314 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3315 SH_PFC_PIN_GROUP(msiof2_txd_b),
3316 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3317 SH_PFC_PIN_GROUP(msiof2_clk_c),
3318 SH_PFC_PIN_GROUP(msiof2_sync_c),
3319 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3320 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3321 SH_PFC_PIN_GROUP(msiof2_txd_c),
3322 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3323 SH_PFC_PIN_GROUP(msiof2_clk_d),
3324 SH_PFC_PIN_GROUP(msiof2_sync_d),
3325 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3326 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3327 SH_PFC_PIN_GROUP(msiof2_txd_d),
3328 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3329 SH_PFC_PIN_GROUP(msiof3_clk_a),
3330 SH_PFC_PIN_GROUP(msiof3_sync_a),
3331 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3332 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3333 SH_PFC_PIN_GROUP(msiof3_txd_a),
3334 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3335 SH_PFC_PIN_GROUP(msiof3_clk_b),
3336 SH_PFC_PIN_GROUP(msiof3_sync_b),
3337 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3338 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3339 SH_PFC_PIN_GROUP(msiof3_txd_b),
3340 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3341 SH_PFC_PIN_GROUP(msiof3_clk_c),
3342 SH_PFC_PIN_GROUP(msiof3_sync_c),
3343 SH_PFC_PIN_GROUP(msiof3_txd_c),
3344 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3345 SH_PFC_PIN_GROUP(msiof3_clk_d),
3346 SH_PFC_PIN_GROUP(msiof3_sync_d),
3347 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3348 SH_PFC_PIN_GROUP(msiof3_txd_d),
3349 SH_PFC_PIN_GROUP(msiof3_rxd_d),
3350 SH_PFC_PIN_GROUP(msiof3_clk_e),
3351 SH_PFC_PIN_GROUP(msiof3_sync_e),
3352 SH_PFC_PIN_GROUP(msiof3_ss1_e),
3353 SH_PFC_PIN_GROUP(msiof3_ss2_e),
3354 SH_PFC_PIN_GROUP(msiof3_txd_e),
3355 SH_PFC_PIN_GROUP(msiof3_rxd_e),
3356 SH_PFC_PIN_GROUP(pwm0),
3357 SH_PFC_PIN_GROUP(pwm1_a),
3358 SH_PFC_PIN_GROUP(pwm1_b),
3359 SH_PFC_PIN_GROUP(pwm2_a),
3360 SH_PFC_PIN_GROUP(pwm2_b),
3361 SH_PFC_PIN_GROUP(pwm3_a),
3362 SH_PFC_PIN_GROUP(pwm3_b),
3363 SH_PFC_PIN_GROUP(pwm4_a),
3364 SH_PFC_PIN_GROUP(pwm4_b),
3365 SH_PFC_PIN_GROUP(pwm5_a),
3366 SH_PFC_PIN_GROUP(pwm5_b),
3367 SH_PFC_PIN_GROUP(pwm6_a),
3368 SH_PFC_PIN_GROUP(pwm6_b),
3369 SH_PFC_PIN_GROUP(scif0_data),
3370 SH_PFC_PIN_GROUP(scif0_clk),
3371 SH_PFC_PIN_GROUP(scif0_ctrl),
3372 SH_PFC_PIN_GROUP(scif1_data_a),
3373 SH_PFC_PIN_GROUP(scif1_clk),
3374 SH_PFC_PIN_GROUP(scif1_ctrl),
3375 SH_PFC_PIN_GROUP(scif1_data_b),
3376 SH_PFC_PIN_GROUP(scif2_data_a),
3377 SH_PFC_PIN_GROUP(scif2_clk),
3378 SH_PFC_PIN_GROUP(scif2_data_b),
3379 SH_PFC_PIN_GROUP(scif3_data_a),
3380 SH_PFC_PIN_GROUP(scif3_clk),
3381 SH_PFC_PIN_GROUP(scif3_ctrl),
3382 SH_PFC_PIN_GROUP(scif3_data_b),
3383 SH_PFC_PIN_GROUP(scif4_data_a),
3384 SH_PFC_PIN_GROUP(scif4_clk_a),
3385 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3386 SH_PFC_PIN_GROUP(scif4_data_b),
3387 SH_PFC_PIN_GROUP(scif4_clk_b),
3388 SH_PFC_PIN_GROUP(scif4_ctrl_b),
3389 SH_PFC_PIN_GROUP(scif4_data_c),
3390 SH_PFC_PIN_GROUP(scif4_clk_c),
3391 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3392 SH_PFC_PIN_GROUP(scif5_data_a),
3393 SH_PFC_PIN_GROUP(scif5_clk_a),
3394 SH_PFC_PIN_GROUP(scif5_data_b),
3395 SH_PFC_PIN_GROUP(scif5_clk_b),
3396 SH_PFC_PIN_GROUP(scif_clk_a),
3397 SH_PFC_PIN_GROUP(scif_clk_b),
3398 SH_PFC_PIN_GROUP(sdhi0_data1),
3399 SH_PFC_PIN_GROUP(sdhi0_data4),
3400 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3401 SH_PFC_PIN_GROUP(sdhi0_cd),
3402 SH_PFC_PIN_GROUP(sdhi0_wp),
3403 SH_PFC_PIN_GROUP(sdhi1_data1),
3404 SH_PFC_PIN_GROUP(sdhi1_data4),
3405 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3406 SH_PFC_PIN_GROUP(sdhi1_cd),
3407 SH_PFC_PIN_GROUP(sdhi1_wp),
3408 SH_PFC_PIN_GROUP(sdhi2_data1),
3409 SH_PFC_PIN_GROUP(sdhi2_data4),
3410 SH_PFC_PIN_GROUP(sdhi2_data8),
3411 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3412 SH_PFC_PIN_GROUP(sdhi2_cd_a),
3413 SH_PFC_PIN_GROUP(sdhi2_wp_a),
3414 SH_PFC_PIN_GROUP(sdhi2_cd_b),
3415 SH_PFC_PIN_GROUP(sdhi2_wp_b),
3416 SH_PFC_PIN_GROUP(sdhi2_ds),
3417 SH_PFC_PIN_GROUP(sdhi3_data1),
3418 SH_PFC_PIN_GROUP(sdhi3_data4),
3419 SH_PFC_PIN_GROUP(sdhi3_data8),
3420 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3421 SH_PFC_PIN_GROUP(sdhi3_cd),
3422 SH_PFC_PIN_GROUP(sdhi3_wp),
3423 SH_PFC_PIN_GROUP(sdhi3_ds),
3424 SH_PFC_PIN_GROUP(usb0),
3425 SH_PFC_PIN_GROUP(usb1),
3426 SH_PFC_PIN_GROUP(usb2),
3427 SH_PFC_PIN_GROUP(usb2_ch3),
3428};
3429
3430static const char * const avb_groups[] = {
3431 "avb_link",
3432 "avb_magic",
3433 "avb_phy_int",
3434 "avb_mdc",
3435 "avb_mii",
3436 "avb_avtp_pps",
3437 "avb_avtp_match_a",
3438 "avb_avtp_capture_a",
3439 "avb_avtp_match_b",
3440 "avb_avtp_capture_b",
3441};
3442
3443static const char * const drif0_groups[] = {
3444 "drif0_ctrl_a",
3445 "drif0_data0_a",
3446 "drif0_data1_a",
3447 "drif0_ctrl_b",
3448 "drif0_data0_b",
3449 "drif0_data1_b",
3450 "drif0_ctrl_c",
3451 "drif0_data0_c",
3452 "drif0_data1_c",
3453};
3454
3455static const char * const drif1_groups[] = {
3456 "drif1_ctrl_a",
3457 "drif1_data0_a",
3458 "drif1_data1_a",
3459 "drif1_ctrl_b",
3460 "drif1_data0_b",
3461 "drif1_data1_b",
3462 "drif1_ctrl_c",
3463 "drif1_data0_c",
3464 "drif1_data1_c",
3465};
3466
3467static const char * const drif2_groups[] = {
3468 "drif2_ctrl_a",
3469 "drif2_data0_a",
3470 "drif2_data1_a",
3471 "drif2_ctrl_b",
3472 "drif2_data0_b",
3473 "drif2_data1_b",
3474};
3475
3476static const char * const drif3_groups[] = {
3477 "drif3_ctrl_a",
3478 "drif3_data0_a",
3479 "drif3_data1_a",
3480 "drif3_ctrl_b",
3481 "drif3_data0_b",
3482 "drif3_data1_b",
3483};
3484
3485static const char * const du_groups[] = {
3486 "du_rgb666",
3487 "du_rgb888",
3488 "du_clk_out_0",
3489 "du_clk_out_1",
3490 "du_sync",
3491 "du_oddf",
3492 "du_cde",
3493 "du_disp",
3494};
3495
3496static const char * const msiof0_groups[] = {
3497 "msiof0_clk",
3498 "msiof0_sync",
3499 "msiof0_ss1",
3500 "msiof0_ss2",
3501 "msiof0_txd",
3502 "msiof0_rxd",
3503};
3504
3505static const char * const msiof1_groups[] = {
3506 "msiof1_clk_a",
3507 "msiof1_sync_a",
3508 "msiof1_ss1_a",
3509 "msiof1_ss2_a",
3510 "msiof1_txd_a",
3511 "msiof1_rxd_a",
3512 "msiof1_clk_b",
3513 "msiof1_sync_b",
3514 "msiof1_ss1_b",
3515 "msiof1_ss2_b",
3516 "msiof1_txd_b",
3517 "msiof1_rxd_b",
3518 "msiof1_clk_c",
3519 "msiof1_sync_c",
3520 "msiof1_ss1_c",
3521 "msiof1_ss2_c",
3522 "msiof1_txd_c",
3523 "msiof1_rxd_c",
3524 "msiof1_clk_d",
3525 "msiof1_sync_d",
3526 "msiof1_ss1_d",
3527 "msiof1_ss2_d",
3528 "msiof1_txd_d",
3529 "msiof1_rxd_d",
3530 "msiof1_clk_e",
3531 "msiof1_sync_e",
3532 "msiof1_ss1_e",
3533 "msiof1_ss2_e",
3534 "msiof1_txd_e",
3535 "msiof1_rxd_e",
3536 "msiof1_clk_f",
3537 "msiof1_sync_f",
3538 "msiof1_ss1_f",
3539 "msiof1_ss2_f",
3540 "msiof1_txd_f",
3541 "msiof1_rxd_f",
3542 "msiof1_clk_g",
3543 "msiof1_sync_g",
3544 "msiof1_ss1_g",
3545 "msiof1_ss2_g",
3546 "msiof1_txd_g",
3547 "msiof1_rxd_g",
3548};
3549
3550static const char * const msiof2_groups[] = {
3551 "msiof2_clk_a",
3552 "msiof2_sync_a",
3553 "msiof2_ss1_a",
3554 "msiof2_ss2_a",
3555 "msiof2_txd_a",
3556 "msiof2_rxd_a",
3557 "msiof2_clk_b",
3558 "msiof2_sync_b",
3559 "msiof2_ss1_b",
3560 "msiof2_ss2_b",
3561 "msiof2_txd_b",
3562 "msiof2_rxd_b",
3563 "msiof2_clk_c",
3564 "msiof2_sync_c",
3565 "msiof2_ss1_c",
3566 "msiof2_ss2_c",
3567 "msiof2_txd_c",
3568 "msiof2_rxd_c",
3569 "msiof2_clk_d",
3570 "msiof2_sync_d",
3571 "msiof2_ss1_d",
3572 "msiof2_ss2_d",
3573 "msiof2_txd_d",
3574 "msiof2_rxd_d",
3575};
3576
3577static const char * const msiof3_groups[] = {
3578 "msiof3_clk_a",
3579 "msiof3_sync_a",
3580 "msiof3_ss1_a",
3581 "msiof3_ss2_a",
3582 "msiof3_txd_a",
3583 "msiof3_rxd_a",
3584 "msiof3_clk_b",
3585 "msiof3_sync_b",
3586 "msiof3_ss1_b",
3587 "msiof3_ss2_b",
3588 "msiof3_txd_b",
3589 "msiof3_rxd_b",
3590 "msiof3_clk_c",
3591 "msiof3_sync_c",
3592 "msiof3_txd_c",
3593 "msiof3_rxd_c",
3594 "msiof3_clk_d",
3595 "msiof3_sync_d",
3596 "msiof3_ss1_d",
3597 "msiof3_txd_d",
3598 "msiof3_rxd_d",
3599 "msiof3_clk_e",
3600 "msiof3_sync_e",
3601 "msiof3_ss1_e",
3602 "msiof3_ss2_e",
3603 "msiof3_txd_e",
3604 "msiof3_rxd_e",
3605};
3606
3607static const char * const pwm0_groups[] = {
3608 "pwm0",
3609};
3610
3611static const char * const pwm1_groups[] = {
3612 "pwm1_a",
3613 "pwm1_b",
3614};
3615
3616static const char * const pwm2_groups[] = {
3617 "pwm2_a",
3618 "pwm2_b",
3619};
3620
3621static const char * const pwm3_groups[] = {
3622 "pwm3_a",
3623 "pwm3_b",
3624};
3625
3626static const char * const pwm4_groups[] = {
3627 "pwm4_a",
3628 "pwm4_b",
3629};
3630
3631static const char * const pwm5_groups[] = {
3632 "pwm5_a",
3633 "pwm5_b",
3634};
3635
3636static const char * const pwm6_groups[] = {
3637 "pwm6_a",
3638 "pwm6_b",
3639};
3640
3641static const char * const scif0_groups[] = {
3642 "scif0_data",
3643 "scif0_clk",
3644 "scif0_ctrl",
3645};
3646
3647static const char * const scif1_groups[] = {
3648 "scif1_data_a",
3649 "scif1_clk",
3650 "scif1_ctrl",
3651 "scif1_data_b",
3652};
3653
3654static const char * const scif2_groups[] = {
3655 "scif2_data_a",
3656 "scif2_clk",
3657 "scif2_data_b",
3658};
3659
3660static const char * const scif3_groups[] = {
3661 "scif3_data_a",
3662 "scif3_clk",
3663 "scif3_ctrl",
3664 "scif3_data_b",
3665};
3666
3667static const char * const scif4_groups[] = {
3668 "scif4_data_a",
3669 "scif4_clk_a",
3670 "scif4_ctrl_a",
3671 "scif4_data_b",
3672 "scif4_clk_b",
3673 "scif4_ctrl_b",
3674 "scif4_data_c",
3675 "scif4_clk_c",
3676 "scif4_ctrl_c",
3677};
3678
3679static const char * const scif5_groups[] = {
3680 "scif5_data_a",
3681 "scif5_clk_a",
3682 "scif5_data_b",
3683 "scif5_clk_b",
3684};
3685
3686static const char * const scif_clk_groups[] = {
3687 "scif_clk_a",
3688 "scif_clk_b",
3689};
3690
3691static const char * const sdhi0_groups[] = {
3692 "sdhi0_data1",
3693 "sdhi0_data4",
3694 "sdhi0_ctrl",
3695 "sdhi0_cd",
3696 "sdhi0_wp",
3697};
3698
3699static const char * const sdhi1_groups[] = {
3700 "sdhi1_data1",
3701 "sdhi1_data4",
3702 "sdhi1_ctrl",
3703 "sdhi1_cd",
3704 "sdhi1_wp",
3705};
3706
3707static const char * const sdhi2_groups[] = {
3708 "sdhi2_data1",
3709 "sdhi2_data4",
3710 "sdhi2_data8",
3711 "sdhi2_ctrl",
3712 "sdhi2_cd_a",
3713 "sdhi2_wp_a",
3714 "sdhi2_cd_b",
3715 "sdhi2_wp_b",
3716 "sdhi2_ds",
3717};
3718
3719static const char * const sdhi3_groups[] = {
3720 "sdhi3_data1",
3721 "sdhi3_data4",
3722 "sdhi3_data8",
3723 "sdhi3_ctrl",
3724 "sdhi3_cd",
3725 "sdhi3_wp",
3726 "sdhi3_ds",
3727};
3728
3729static const char * const usb0_groups[] = {
3730 "usb0",
3731};
3732
3733static const char * const usb1_groups[] = {
3734 "usb1",
3735};
3736
3737static const char * const usb2_groups[] = {
3738 "usb2",
3739};
3740
3741static const char * const usb2_ch3_groups[] = {
3742 "usb2_ch3",
3743};
3744
3745static const struct sh_pfc_function pinmux_functions[] = {
3746 SH_PFC_FUNCTION(avb),
3747 SH_PFC_FUNCTION(drif0),
3748 SH_PFC_FUNCTION(drif1),
3749 SH_PFC_FUNCTION(drif2),
3750 SH_PFC_FUNCTION(drif3),
3751 SH_PFC_FUNCTION(du),
3752 SH_PFC_FUNCTION(msiof0),
3753 SH_PFC_FUNCTION(msiof1),
3754 SH_PFC_FUNCTION(msiof2),
3755 SH_PFC_FUNCTION(msiof3),
3756 SH_PFC_FUNCTION(pwm0),
3757 SH_PFC_FUNCTION(pwm1),
3758 SH_PFC_FUNCTION(pwm2),
3759 SH_PFC_FUNCTION(pwm3),
3760 SH_PFC_FUNCTION(pwm4),
3761 SH_PFC_FUNCTION(pwm5),
3762 SH_PFC_FUNCTION(pwm6),
3763 SH_PFC_FUNCTION(scif0),
3764 SH_PFC_FUNCTION(scif1),
3765 SH_PFC_FUNCTION(scif2),
3766 SH_PFC_FUNCTION(scif3),
3767 SH_PFC_FUNCTION(scif4),
3768 SH_PFC_FUNCTION(scif5),
3769 SH_PFC_FUNCTION(scif_clk),
3770 SH_PFC_FUNCTION(sdhi0),
3771 SH_PFC_FUNCTION(sdhi1),
3772 SH_PFC_FUNCTION(sdhi2),
3773 SH_PFC_FUNCTION(sdhi3),
3774 SH_PFC_FUNCTION(usb0),
3775 SH_PFC_FUNCTION(usb1),
3776 SH_PFC_FUNCTION(usb2),
3777 SH_PFC_FUNCTION(usb2_ch3),
3778};
3779
3780static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3781#define F_(x, y) FN_##y
3782#define FM(x) FN_##x
3783 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
3784 0, 0,
3785 0, 0,
3786 0, 0,
3787 0, 0,
3788 0, 0,
3789 0, 0,
3790 0, 0,
3791 0, 0,
3792 0, 0,
3793 0, 0,
3794 0, 0,
3795 0, 0,
3796 0, 0,
3797 0, 0,
3798 0, 0,
3799 0, 0,
3800 GP_0_15_FN, GPSR0_15,
3801 GP_0_14_FN, GPSR0_14,
3802 GP_0_13_FN, GPSR0_13,
3803 GP_0_12_FN, GPSR0_12,
3804 GP_0_11_FN, GPSR0_11,
3805 GP_0_10_FN, GPSR0_10,
3806 GP_0_9_FN, GPSR0_9,
3807 GP_0_8_FN, GPSR0_8,
3808 GP_0_7_FN, GPSR0_7,
3809 GP_0_6_FN, GPSR0_6,
3810 GP_0_5_FN, GPSR0_5,
3811 GP_0_4_FN, GPSR0_4,
3812 GP_0_3_FN, GPSR0_3,
3813 GP_0_2_FN, GPSR0_2,
3814 GP_0_1_FN, GPSR0_1,
3815 GP_0_0_FN, GPSR0_0, }
3816 },
3817 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
3818 0, 0,
3819 0, 0,
3820 0, 0,
3821 0, 0,
3822 GP_1_27_FN, GPSR1_27,
3823 GP_1_26_FN, GPSR1_26,
3824 GP_1_25_FN, GPSR1_25,
3825 GP_1_24_FN, GPSR1_24,
3826 GP_1_23_FN, GPSR1_23,
3827 GP_1_22_FN, GPSR1_22,
3828 GP_1_21_FN, GPSR1_21,
3829 GP_1_20_FN, GPSR1_20,
3830 GP_1_19_FN, GPSR1_19,
3831 GP_1_18_FN, GPSR1_18,
3832 GP_1_17_FN, GPSR1_17,
3833 GP_1_16_FN, GPSR1_16,
3834 GP_1_15_FN, GPSR1_15,
3835 GP_1_14_FN, GPSR1_14,
3836 GP_1_13_FN, GPSR1_13,
3837 GP_1_12_FN, GPSR1_12,
3838 GP_1_11_FN, GPSR1_11,
3839 GP_1_10_FN, GPSR1_10,
3840 GP_1_9_FN, GPSR1_9,
3841 GP_1_8_FN, GPSR1_8,
3842 GP_1_7_FN, GPSR1_7,
3843 GP_1_6_FN, GPSR1_6,
3844 GP_1_5_FN, GPSR1_5,
3845 GP_1_4_FN, GPSR1_4,
3846 GP_1_3_FN, GPSR1_3,
3847 GP_1_2_FN, GPSR1_2,
3848 GP_1_1_FN, GPSR1_1,
3849 GP_1_0_FN, GPSR1_0, }
3850 },
3851 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
3852 0, 0,
3853 0, 0,
3854 0, 0,
3855 0, 0,
3856 0, 0,
3857 0, 0,
3858 0, 0,
3859 0, 0,
3860 0, 0,
3861 0, 0,
3862 0, 0,
3863 0, 0,
3864 0, 0,
3865 0, 0,
3866 0, 0,
3867 0, 0,
3868 0, 0,
3869 GP_2_14_FN, GPSR2_14,
3870 GP_2_13_FN, GPSR2_13,
3871 GP_2_12_FN, GPSR2_12,
3872 GP_2_11_FN, GPSR2_11,
3873 GP_2_10_FN, GPSR2_10,
3874 GP_2_9_FN, GPSR2_9,
3875 GP_2_8_FN, GPSR2_8,
3876 GP_2_7_FN, GPSR2_7,
3877 GP_2_6_FN, GPSR2_6,
3878 GP_2_5_FN, GPSR2_5,
3879 GP_2_4_FN, GPSR2_4,
3880 GP_2_3_FN, GPSR2_3,
3881 GP_2_2_FN, GPSR2_2,
3882 GP_2_1_FN, GPSR2_1,
3883 GP_2_0_FN, GPSR2_0, }
3884 },
3885 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
3886 0, 0,
3887 0, 0,
3888 0, 0,
3889 0, 0,
3890 0, 0,
3891 0, 0,
3892 0, 0,
3893 0, 0,
3894 0, 0,
3895 0, 0,
3896 0, 0,
3897 0, 0,
3898 0, 0,
3899 0, 0,
3900 0, 0,
3901 0, 0,
3902 GP_3_15_FN, GPSR3_15,
3903 GP_3_14_FN, GPSR3_14,
3904 GP_3_13_FN, GPSR3_13,
3905 GP_3_12_FN, GPSR3_12,
3906 GP_3_11_FN, GPSR3_11,
3907 GP_3_10_FN, GPSR3_10,
3908 GP_3_9_FN, GPSR3_9,
3909 GP_3_8_FN, GPSR3_8,
3910 GP_3_7_FN, GPSR3_7,
3911 GP_3_6_FN, GPSR3_6,
3912 GP_3_5_FN, GPSR3_5,
3913 GP_3_4_FN, GPSR3_4,
3914 GP_3_3_FN, GPSR3_3,
3915 GP_3_2_FN, GPSR3_2,
3916 GP_3_1_FN, GPSR3_1,
3917 GP_3_0_FN, GPSR3_0, }
3918 },
3919 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
3920 0, 0,
3921 0, 0,
3922 0, 0,
3923 0, 0,
3924 0, 0,
3925 0, 0,
3926 0, 0,
3927 0, 0,
3928 0, 0,
3929 0, 0,
3930 0, 0,
3931 0, 0,
3932 0, 0,
3933 0, 0,
3934 GP_4_17_FN, GPSR4_17,
3935 GP_4_16_FN, GPSR4_16,
3936 GP_4_15_FN, GPSR4_15,
3937 GP_4_14_FN, GPSR4_14,
3938 GP_4_13_FN, GPSR4_13,
3939 GP_4_12_FN, GPSR4_12,
3940 GP_4_11_FN, GPSR4_11,
3941 GP_4_10_FN, GPSR4_10,
3942 GP_4_9_FN, GPSR4_9,
3943 GP_4_8_FN, GPSR4_8,
3944 GP_4_7_FN, GPSR4_7,
3945 GP_4_6_FN, GPSR4_6,
3946 GP_4_5_FN, GPSR4_5,
3947 GP_4_4_FN, GPSR4_4,
3948 GP_4_3_FN, GPSR4_3,
3949 GP_4_2_FN, GPSR4_2,
3950 GP_4_1_FN, GPSR4_1,
3951 GP_4_0_FN, GPSR4_0, }
3952 },
3953 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
3954 0, 0,
3955 0, 0,
3956 0, 0,
3957 0, 0,
3958 0, 0,
3959 0, 0,
3960 GP_5_25_FN, GPSR5_25,
3961 GP_5_24_FN, GPSR5_24,
3962 GP_5_23_FN, GPSR5_23,
3963 GP_5_22_FN, GPSR5_22,
3964 GP_5_21_FN, GPSR5_21,
3965 GP_5_20_FN, GPSR5_20,
3966 GP_5_19_FN, GPSR5_19,
3967 GP_5_18_FN, GPSR5_18,
3968 GP_5_17_FN, GPSR5_17,
3969 GP_5_16_FN, GPSR5_16,
3970 GP_5_15_FN, GPSR5_15,
3971 GP_5_14_FN, GPSR5_14,
3972 GP_5_13_FN, GPSR5_13,
3973 GP_5_12_FN, GPSR5_12,
3974 GP_5_11_FN, GPSR5_11,
3975 GP_5_10_FN, GPSR5_10,
3976 GP_5_9_FN, GPSR5_9,
3977 GP_5_8_FN, GPSR5_8,
3978 GP_5_7_FN, GPSR5_7,
3979 GP_5_6_FN, GPSR5_6,
3980 GP_5_5_FN, GPSR5_5,
3981 GP_5_4_FN, GPSR5_4,
3982 GP_5_3_FN, GPSR5_3,
3983 GP_5_2_FN, GPSR5_2,
3984 GP_5_1_FN, GPSR5_1,
3985 GP_5_0_FN, GPSR5_0, }
3986 },
3987 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
3988 GP_6_31_FN, GPSR6_31,
3989 GP_6_30_FN, GPSR6_30,
3990 GP_6_29_FN, GPSR6_29,
3991 GP_6_28_FN, GPSR6_28,
3992 GP_6_27_FN, GPSR6_27,
3993 GP_6_26_FN, GPSR6_26,
3994 GP_6_25_FN, GPSR6_25,
3995 GP_6_24_FN, GPSR6_24,
3996 GP_6_23_FN, GPSR6_23,
3997 GP_6_22_FN, GPSR6_22,
3998 GP_6_21_FN, GPSR6_21,
3999 GP_6_20_FN, GPSR6_20,
4000 GP_6_19_FN, GPSR6_19,
4001 GP_6_18_FN, GPSR6_18,
4002 GP_6_17_FN, GPSR6_17,
4003 GP_6_16_FN, GPSR6_16,
4004 GP_6_15_FN, GPSR6_15,
4005 GP_6_14_FN, GPSR6_14,
4006 GP_6_13_FN, GPSR6_13,
4007 GP_6_12_FN, GPSR6_12,
4008 GP_6_11_FN, GPSR6_11,
4009 GP_6_10_FN, GPSR6_10,
4010 GP_6_9_FN, GPSR6_9,
4011 GP_6_8_FN, GPSR6_8,
4012 GP_6_7_FN, GPSR6_7,
4013 GP_6_6_FN, GPSR6_6,
4014 GP_6_5_FN, GPSR6_5,
4015 GP_6_4_FN, GPSR6_4,
4016 GP_6_3_FN, GPSR6_3,
4017 GP_6_2_FN, GPSR6_2,
4018 GP_6_1_FN, GPSR6_1,
4019 GP_6_0_FN, GPSR6_0, }
4020 },
4021 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4022 0, 0,
4023 0, 0,
4024 0, 0,
4025 0, 0,
4026 0, 0,
4027 0, 0,
4028 0, 0,
4029 0, 0,
4030 0, 0,
4031 0, 0,
4032 0, 0,
4033 0, 0,
4034 0, 0,
4035 0, 0,
4036 0, 0,
4037 0, 0,
4038 0, 0,
4039 0, 0,
4040 0, 0,
4041 0, 0,
4042 0, 0,
4043 0, 0,
4044 0, 0,
4045 0, 0,
4046 0, 0,
4047 0, 0,
4048 0, 0,
4049 0, 0,
4050 GP_7_3_FN, GPSR7_3,
4051 GP_7_2_FN, GPSR7_2,
4052 GP_7_1_FN, GPSR7_1,
4053 GP_7_0_FN, GPSR7_0, }
4054 },
4055#undef F_
4056#undef FM
4057
4058#define F_(x, y) x,
4059#define FM(x) FN_##x,
4060 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4061 IP0_31_28
4062 IP0_27_24
4063 IP0_23_20
4064 IP0_19_16
4065 IP0_15_12
4066 IP0_11_8
4067 IP0_7_4
4068 IP0_3_0 }
4069 },
4070 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4071 IP1_31_28
4072 IP1_27_24
4073 IP1_23_20
4074 IP1_19_16
4075 IP1_15_12
4076 IP1_11_8
4077 IP1_7_4
4078 IP1_3_0 }
4079 },
4080 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4081 IP2_31_28
4082 IP2_27_24
4083 IP2_23_20
4084 IP2_19_16
4085 IP2_15_12
4086 IP2_11_8
4087 IP2_7_4
4088 IP2_3_0 }
4089 },
4090 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4091 IP3_31_28
4092 IP3_27_24
4093 IP3_23_20
4094 IP3_19_16
4095 IP3_15_12
4096 IP3_11_8
4097 IP3_7_4
4098 IP3_3_0 }
4099 },
4100 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4101 IP4_31_28
4102 IP4_27_24
4103 IP4_23_20
4104 IP4_19_16
4105 IP4_15_12
4106 IP4_11_8
4107 IP4_7_4
4108 IP4_3_0 }
4109 },
4110 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4111 IP5_31_28
4112 IP5_27_24
4113 IP5_23_20
4114 IP5_19_16
4115 IP5_15_12
4116 IP5_11_8
4117 IP5_7_4
4118 IP5_3_0 }
4119 },
4120 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4121 IP6_31_28
4122 IP6_27_24
4123 IP6_23_20
4124 IP6_19_16
4125 IP6_15_12
4126 IP6_11_8
4127 IP6_7_4
4128 IP6_3_0 }
4129 },
4130 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4131 IP7_31_28
4132 IP7_27_24
4133 IP7_23_20
4134 IP7_19_16
4135 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4136 IP7_11_8
4137 IP7_7_4
4138 IP7_3_0 }
4139 },
4140 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4141 IP8_31_28
4142 IP8_27_24
4143 IP8_23_20
4144 IP8_19_16
4145 IP8_15_12
4146 IP8_11_8
4147 IP8_7_4
4148 IP8_3_0 }
4149 },
4150 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4151 IP9_31_28
4152 IP9_27_24
4153 IP9_23_20
4154 IP9_19_16
4155 IP9_15_12
4156 IP9_11_8
4157 IP9_7_4
4158 IP9_3_0 }
4159 },
4160 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4161 IP10_31_28
4162 IP10_27_24
4163 IP10_23_20
4164 IP10_19_16
4165 IP10_15_12
4166 IP10_11_8
4167 IP10_7_4
4168 IP10_3_0 }
4169 },
4170 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4171 IP11_31_28
4172 IP11_27_24
4173 IP11_23_20
4174 IP11_19_16
4175 IP11_15_12
4176 IP11_11_8
4177 IP11_7_4
4178 IP11_3_0 }
4179 },
4180 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4181 IP12_31_28
4182 IP12_27_24
4183 IP12_23_20
4184 IP12_19_16
4185 IP12_15_12
4186 IP12_11_8
4187 IP12_7_4
4188 IP12_3_0 }
4189 },
4190 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4191 IP13_31_28
4192 IP13_27_24
4193 IP13_23_20
4194 IP13_19_16
4195 IP13_15_12
4196 IP13_11_8
4197 IP13_7_4
4198 IP13_3_0 }
4199 },
4200 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4201 IP14_31_28
4202 IP14_27_24
4203 IP14_23_20
4204 IP14_19_16
4205 IP14_15_12
4206 IP14_11_8
4207 IP14_7_4
4208 IP14_3_0 }
4209 },
4210 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4211 IP15_31_28
4212 IP15_27_24
4213 IP15_23_20
4214 IP15_19_16
4215 IP15_15_12
4216 IP15_11_8
4217 IP15_7_4
4218 IP15_3_0 }
4219 },
4220 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4221 IP16_31_28
4222 IP16_27_24
4223 IP16_23_20
4224 IP16_19_16
4225 IP16_15_12
4226 IP16_11_8
4227 IP16_7_4
4228 IP16_3_0 }
4229 },
4230 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4231 IP17_31_28
4232 IP17_27_24
4233 IP17_23_20
4234 IP17_19_16
4235 IP17_15_12
4236 IP17_11_8
4237 IP17_7_4
4238 IP17_3_0 }
4239 },
4240 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
4241 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4242 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4243 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4244 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4245 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4246 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4247 IP18_7_4
4248 IP18_3_0 }
4249 },
4250#undef F_
4251#undef FM
4252
4253#define F_(x, y) x,
4254#define FM(x) FN_##x,
4255 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4256 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
4257 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
4258 MOD_SEL0_31_30_29
4259 MOD_SEL0_28_27
4260 MOD_SEL0_26_25_24
4261 MOD_SEL0_23
4262 MOD_SEL0_22
4263 MOD_SEL0_21
4264 MOD_SEL0_20
4265 MOD_SEL0_19
4266 MOD_SEL0_18_17
4267 MOD_SEL0_16
4268 0, 0, /* RESERVED 15 */
4269 MOD_SEL0_14_13
4270 MOD_SEL0_12
4271 MOD_SEL0_11
4272 MOD_SEL0_10
4273 MOD_SEL0_9_8
4274 MOD_SEL0_7_6
4275 MOD_SEL0_5
4276 MOD_SEL0_4_3
4277 /* RESERVED 2, 1, 0 */
4278 0, 0, 0, 0, 0, 0, 0, 0 }
4279 },
4280 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4281 2, 3, 1, 2, 3, 1, 1, 2, 1,
4282 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4283 MOD_SEL1_31_30
4284 MOD_SEL1_29_28_27
4285 MOD_SEL1_26
4286 MOD_SEL1_25_24
4287 MOD_SEL1_23_22_21
4288 MOD_SEL1_20
4289 MOD_SEL1_19
4290 MOD_SEL1_18_17
4291 MOD_SEL1_16
4292 MOD_SEL1_15_14
4293 MOD_SEL1_13
4294 MOD_SEL1_12
4295 MOD_SEL1_11
4296 MOD_SEL1_10
4297 MOD_SEL1_9
4298 0, 0, 0, 0, /* RESERVED 8, 7 */
4299 MOD_SEL1_6
4300 MOD_SEL1_5
4301 MOD_SEL1_4
4302 MOD_SEL1_3
4303 MOD_SEL1_2
4304 MOD_SEL1_1
4305 MOD_SEL1_0 }
4306 },
4307 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4308 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
4309 4, 4, 4, 3, 1) {
4310 MOD_SEL2_31
4311 MOD_SEL2_30
4312 MOD_SEL2_29
4313 MOD_SEL2_28_27
4314 MOD_SEL2_26
4315 MOD_SEL2_25_24_23
4316 /* RESERVED 22 */
4317 0, 0,
4318 MOD_SEL2_21
4319 MOD_SEL2_20
4320 MOD_SEL2_19
4321 MOD_SEL2_18
4322 MOD_SEL2_17
4323 /* RESERVED 16 */
4324 0, 0,
4325 /* RESERVED 15, 14, 13, 12 */
4326 0, 0, 0, 0, 0, 0, 0, 0,
4327 0, 0, 0, 0, 0, 0, 0, 0,
4328 /* RESERVED 11, 10, 9, 8 */
4329 0, 0, 0, 0, 0, 0, 0, 0,
4330 0, 0, 0, 0, 0, 0, 0, 0,
4331 /* RESERVED 7, 6, 5, 4 */
4332 0, 0, 0, 0, 0, 0, 0, 0,
4333 0, 0, 0, 0, 0, 0, 0, 0,
4334 /* RESERVED 3, 2, 1 */
4335 0, 0, 0, 0, 0, 0, 0, 0,
4336 MOD_SEL2_0 }
4337 },
4338 { },
4339};
4340
4341static const struct pinmux_drive_reg pinmux_drive_regs[] = {
4342 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
4343 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
4344 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
4345 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
4346 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
4347 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
4348 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
4349 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
4350 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
4351 } },
4352 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
4353 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
4354 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
4355 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
4356 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
4357 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
4358 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
4359 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
4360 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
4361 } },
4362 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
4363 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
4364 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
4365 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
4366 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
4367 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
4368 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
4369 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
4370 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
4371 } },
4372 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
4373 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
4374 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
4375 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
4376 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
4377 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
4378 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
4379 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
4380 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
4381 } },
4382 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4383 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
4384 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
4385 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
4386 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
4387 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
4388 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
4389 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
4390 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
4391 } },
4392 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4393 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
4394 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
4395 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
4396 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
4397 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
4398 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
4399 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
4400 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
4401 } },
4402 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4403 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
4404 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
4405 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
4406 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
4407 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
4408 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
4409 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
4410 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
4411 } },
4412 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
4413 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
4414 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
4415 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
4416 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
4417 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
4418 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
4419 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
4420 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
4421 } },
4422 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
4423 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
4424 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
4425 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
4426 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
4427 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
4428 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
4429 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
4430 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
4431 } },
4432 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
4433 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
4434 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
4435 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
4436 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
4437 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
4438 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
4439 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
4440 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
4441 } },
4442 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
4443 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
4444 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
4445 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
4446 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
4447 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
4448 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
4449 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
4450 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
4451 } },
4452 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
4453 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
4454 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
4455 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
4456 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
4457 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
4458 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
4459 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
4460 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
4461 } },
4462 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
4463 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
4464 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
4465 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
4466 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
4467 } },
4468 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
4469 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
4470 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
4471 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
4472 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
4473 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
4474 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
4475 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
4476 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
4477 } },
4478 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
4479 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
4480 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
4481 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
4482 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
4483 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
4484 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
4485 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
4486 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
4487 } },
4488 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
4489 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
4490 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
4491 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
4492 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
4493 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
4494 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
4495 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
4496 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
4497 } },
4498 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
4499 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
4500 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
4501 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
4502 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
4503 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
4504 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
4505 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
4506 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
4507 } },
4508 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
4509 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
4510 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
4511 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
4512 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
4513 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
4514 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
4515 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
4516 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
4517 } },
4518 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
4519 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
4520 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
4521 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
4522 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
4523 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
4524 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
4525 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
4526 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
4527 } },
4528 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
4529 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
4530 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
4531 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
4532 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
4533 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
4534 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
4535 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
4536 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
4537 } },
4538 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
4539 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
4540 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
4541 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
4542 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
4543 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
4544 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
4545 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
4546 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
4547 } },
4548 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
4549 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
4550 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
4551 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
4552 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
4553 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
4554 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
4555 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
4556 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
4557 } },
4558 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
4559 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
4560 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
4561 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
4562 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
4563 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
4564 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
4565 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
4566 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
4567 } },
4568 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4569 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
4570 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
4571 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
4572 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
4573 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
4574 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
4575 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
4576 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
4577 } },
4578 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4579 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
4580 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
4581 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
4582 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
4583 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
4584 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
4585 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
4586 } },
4587 { },
4588};
4589
4590static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
4591{
4592 int bit = -EINVAL;
4593
4594 *pocctrl = 0xe6060380;
4595
4596 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
4597 bit = pin & 0x1f;
4598
4599 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4600 bit = (pin & 0x1f) + 12;
4601
4602 return bit;
4603}
4604
4605#define PUEN 0xe6060400
4606#define PUD 0xe6060440
4607
4608#define PU0 0x00
4609#define PU1 0x04
4610#define PU2 0x08
4611#define PU3 0x0c
4612#define PU4 0x10
4613#define PU5 0x14
4614#define PU6 0x18
4615
4616static const struct sh_pfc_bias_info bias_info[] = {
4617 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
4618 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
4619 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
4620 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
4621 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
4622 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
4623 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
4624 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
4625 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
4626 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
4627 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
4628 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
4629 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
4630 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
4631 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
4632 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
4633 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
4634 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
4635 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
4636 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
4637 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
4638 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
4639 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
4640 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
4641 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
4642 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
4643 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
4644 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
4645 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
4646 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
4647 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
4648 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
4649
4650 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
4651 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
4652 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
4653 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
4654 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
4655 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
4656 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
4657 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
4658 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
4659 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
4660 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
4661 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
4662 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
4663 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
4664 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
4665 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
4666 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
4667 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
4668 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
4669 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
4670 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
4671 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
4672 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
4673 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
4674 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
4675 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
4676 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
4677 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
4678 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
4679 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
4680 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
4681 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
4682
4683 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
4684 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
4685 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
4686 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
4687 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
4688 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
4689 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
4690 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
4691 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
4692 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
4693 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
4694 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
4695 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
4696 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
4697 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
4698 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
4699 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
4700 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
4701 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
4702 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
4703 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
4704 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
4705 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
4706 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
4707 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
4708 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
4709 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
4710 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
4711 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
4712 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
4713 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
4714 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
4715
4716 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
4717 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
4718 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
4719 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
4720 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
4721 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
4722 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
4723 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
4724 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
4725 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
4726 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
4727 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
4728 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
4729 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
4730 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
4731 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
4732 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
4733 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
4734 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
4735 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
4736 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
4737 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
4738 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
4739 /* bit 8 n/a */
4740 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
4741 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
4742 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
4743 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
4744 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
4745 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
4746 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
4747 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
4748
4749 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
4750 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
4751 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
4752 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
4753 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
4754 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
4755 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
4756 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
4757 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
4758 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
4759 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
4760 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
4761 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
4762 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
4763 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
4764 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
4765 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
4766 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
4767 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
4768 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
4769 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
4770 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
4771 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
4772 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
4773 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
4774 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
4775 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
4776 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
4777 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
4778 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
4779 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
4780 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
4781
4782 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
4783 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
4784 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
4785 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
4786 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
4787 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
4788 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
4789 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
4790 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
4791 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
4792 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
4793 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
4794 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
4795 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
4796 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
4797 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
4798 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
4799 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
4800 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
4801 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
4802 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
4803 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
4804 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
4805 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
4806 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
4807 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
4808 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
4809 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
4810 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
4811 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
4812 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
4813 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
4814
4815 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */
4816 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */
4817 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
4818 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
4819 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
4820 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
4821 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
4822};
4823
4824static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
4825 unsigned int pin)
4826{
4827 const struct sh_pfc_bias_info *info;
4828 u32 reg;
4829 u32 bit;
4830
4831 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
4832 if (!info)
4833 return PIN_CONFIG_BIAS_DISABLE;
4834
4835 reg = info->reg;
4836 bit = BIT(info->bit);
4837
4838 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
4839 return PIN_CONFIG_BIAS_DISABLE;
4840 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
4841 return PIN_CONFIG_BIAS_PULL_UP;
4842 else
4843 return PIN_CONFIG_BIAS_PULL_DOWN;
4844}
4845
4846static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4847 unsigned int bias)
4848{
4849 const struct sh_pfc_bias_info *info;
4850 u32 enable, updown;
4851 u32 reg;
4852 u32 bit;
4853
4854 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
4855 if (!info)
4856 return;
4857
4858 reg = info->reg;
4859 bit = BIT(info->bit);
4860
4861 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
4862 if (bias != PIN_CONFIG_BIAS_DISABLE)
4863 enable |= bit;
4864
4865 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
4866 if (bias == PIN_CONFIG_BIAS_PULL_UP)
4867 updown |= bit;
4868
4869 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
4870 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
4871}
4872
4873static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
4874 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
4875 .get_bias = r8a7795_pinmux_get_bias,
4876 .set_bias = r8a7795_pinmux_set_bias,
4877};
4878
4879const struct sh_pfc_soc_info r8a7795_pinmux_info = {
4880 .name = "r8a77951_pfc",
4881 .ops = &r8a7795_pinmux_ops,
4882 .unlock_reg = 0xe6060000, /* PMMR */
4883
4884 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4885
4886 .pins = pinmux_pins,
4887 .nr_pins = ARRAY_SIZE(pinmux_pins),
4888 .groups = pinmux_groups,
4889 .nr_groups = ARRAY_SIZE(pinmux_groups),
4890 .functions = pinmux_functions,
4891 .nr_functions = ARRAY_SIZE(pinmux_functions),
4892
4893 .cfg_regs = pinmux_config_regs,
4894 .drive_regs = pinmux_drive_regs,
4895
4896 .pinmux_data = pinmux_data,
4897 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4898};