blob: 479b700c868696dd9e7489210cf82b8e2eae1251 [file] [log] [blame]
Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01002/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01004 */
5
6/ {
7 soc {
Patrick Delaunay35a54d42019-07-11 11:15:28 +02008 ddr: ddr@5A003000 {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01009 u-boot,dm-pre-reloc;
10
11 compatible = "st,stm32mp1-ddr";
12
13 reg = <0x5A003000 0x550
14 0x5A004000 0x234>;
15
Patrick Delaunaya6743132018-07-09 15:17:19 +020016 clocks = <&rcc AXIDCG>,
17 <&rcc DDRC1>,
18 <&rcc DDRC2>,
19 <&rcc DDRPHYC>,
20 <&rcc DDRCAPB>,
21 <&rcc DDRPHYCAPB>;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010022
23 clock-names = "axidcg",
24 "ddrc1",
25 "ddrc2",
26 "ddrphyc",
27 "ddrcapb",
28 "ddrphycapb";
29
30 st,mem-name = DDR_MEM_NAME;
31 st,mem-speed = <DDR_MEM_SPEED>;
32 st,mem-size = <DDR_MEM_SIZE>;
33
34 st,ctl-reg = <
35 DDR_MSTR
36 DDR_MRCTRL0
37 DDR_MRCTRL1
38 DDR_DERATEEN
39 DDR_DERATEINT
40 DDR_PWRCTL
41 DDR_PWRTMG
42 DDR_HWLPCTL
43 DDR_RFSHCTL0
44 DDR_RFSHCTL3
45 DDR_CRCPARCTL0
46 DDR_ZQCTL0
47 DDR_DFITMG0
48 DDR_DFITMG1
49 DDR_DFILPCFG0
50 DDR_DFIUPD0
51 DDR_DFIUPD1
52 DDR_DFIUPD2
53 DDR_DFIPHYMSTR
54 DDR_ODTMAP
55 DDR_DBG0
56 DDR_DBG1
57 DDR_DBGCMD
58 DDR_POISONCFG
59 DDR_PCCFG
60 >;
61
62 st,ctl-timing = <
63 DDR_RFSHTMG
64 DDR_DRAMTMG0
65 DDR_DRAMTMG1
66 DDR_DRAMTMG2
67 DDR_DRAMTMG3
68 DDR_DRAMTMG4
69 DDR_DRAMTMG5
70 DDR_DRAMTMG6
71 DDR_DRAMTMG7
72 DDR_DRAMTMG8
73 DDR_DRAMTMG14
74 DDR_ODTCFG
75 >;
76
77 st,ctl-map = <
78 DDR_ADDRMAP1
79 DDR_ADDRMAP2
80 DDR_ADDRMAP3
81 DDR_ADDRMAP4
82 DDR_ADDRMAP5
83 DDR_ADDRMAP6
84 DDR_ADDRMAP9
85 DDR_ADDRMAP10
86 DDR_ADDRMAP11
87 >;
88
89 st,ctl-perf = <
90 DDR_SCHED
91 DDR_SCHED1
92 DDR_PERFHPR1
93 DDR_PERFLPR1
94 DDR_PERFWR1
95 DDR_PCFGR_0
96 DDR_PCFGW_0
97 DDR_PCFGQOS0_0
98 DDR_PCFGQOS1_0
99 DDR_PCFGWQOS0_0
100 DDR_PCFGWQOS1_0
101 DDR_PCFGR_1
102 DDR_PCFGW_1
103 DDR_PCFGQOS0_1
104 DDR_PCFGQOS1_1
105 DDR_PCFGWQOS0_1
106 DDR_PCFGWQOS1_1
107 >;
108
109 st,phy-reg = <
110 DDR_PGCR
111 DDR_ACIOCR
112 DDR_DXCCR
113 DDR_DSGCR
114 DDR_DCR
115 DDR_ODTCR
116 DDR_ZQ0CR1
117 DDR_DX0GCR
118 DDR_DX1GCR
119 DDR_DX2GCR
120 DDR_DX3GCR
121 >;
122
123 st,phy-timing = <
124 DDR_PTR0
125 DDR_PTR1
126 DDR_PTR2
127 DDR_DTPR0
128 DDR_DTPR1
129 DDR_DTPR2
130 DDR_MR0
131 DDR_MR1
132 DDR_MR2
133 DDR_MR3
134 >;
135
136 st,phy-cal = <
137 DDR_DX0DLLCR
138 DDR_DX0DQTR
139 DDR_DX0DQSTR
140 DDR_DX1DLLCR
141 DDR_DX1DQTR
142 DDR_DX1DQSTR
143 DDR_DX2DLLCR
144 DDR_DX2DQTR
145 DDR_DX2DQSTR
146 DDR_DX3DLLCR
147 DDR_DX3DQTR
148 DDR_DX3DQSTR
149 >;
150
151 status = "okay";
152 };
153 };
154};