blob: d3d4c181afad83d3b3dd8d43b449ce90b7d6ff58 [file] [log] [blame]
Sergei Poselenov9531a232010-09-09 23:03:31 +02001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * (C) Copyright 2010
9 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
10 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
Sergei Poselenov9531a232010-09-09 23:03:31 +020012 */
13
14#include <common.h>
15#include <mpc5xxx.h>
16#include <pci.h>
17#include <asm/processor.h>
18#include <asm/io.h>
19#include <libfdt.h>
20#include <netdev.h>
Ilya Yanokcb5639c2010-09-09 23:03:33 +020021#include <led-display.h>
Ilya Yanok92d1a402010-09-09 23:03:34 +020022#include <linux/err.h>
Sergei Poselenov9531a232010-09-09 23:03:31 +020023
24#include "mt46v32m16.h"
25
26#ifndef CONFIG_SYS_RAMBOOT
27static void sdram_start (int hi_addr)
28{
29 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
30 long control = SDRAM_CONTROL | hi_addr_bit;
31
32 /* unlock mode register */
33 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
34 __asm__ volatile ("sync");
35
36 /* precharge all banks */
37 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
38 __asm__ volatile ("sync");
39
40#if SDRAM_DDR
41 /* set mode register: extended mode */
42 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
43 __asm__ volatile ("sync");
44
45 /* set mode register: reset DLL */
46 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
47 __asm__ volatile ("sync");
48#endif
49
50 /* precharge all banks */
51 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
52 __asm__ volatile ("sync");
53
54 /* auto refresh */
55 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
56 __asm__ volatile ("sync");
57
58 /* set mode register */
59 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
60 __asm__ volatile ("sync");
61
62 /* normal operation */
63 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
64 __asm__ volatile ("sync");
65}
66#endif
67
68/*
69 * ATTENTION: Although partially referenced initdram does NOT make real use
70 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
71 * is something else than 0x00000000.
72 */
73
74phys_size_t initdram (int board_type)
75{
76 ulong dramsize = 0;
77 uint svr, pvr;
78
79#ifndef CONFIG_SYS_RAMBOOT
80 ulong test1, test2;
81
82 /* setup SDRAM chip selects */
83 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
84 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
85 __asm__ volatile ("sync");
86
87 /* setup config registers */
88 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
89 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
90 __asm__ volatile ("sync");
91
92#if SDRAM_DDR
93 /* set tap delay */
94 out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
95 __asm__ volatile ("sync");
96#endif
97
98 /* find RAM size using SDRAM CS0 only */
99 sdram_start(0);
100 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
101 sdram_start(1);
102 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
103 if (test1 > test2) {
104 sdram_start(0);
105 dramsize = test1;
106 } else {
107 dramsize = test2;
108 }
109
110 /* memory smaller than 1MB is impossible */
111 if (dramsize < (1 << 20)) {
112 dramsize = 0;
113 }
114
115 /* set SDRAM CS0 size according to the amount of RAM found */
116 if (dramsize > 0) {
117 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
118 0x13 + __builtin_ffs(dramsize >> 20) - 1);
119 } else {
120 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
121 }
122
123#else /* CONFIG_SYS_RAMBOOT */
124
125 /* retrieve size of memory connected to SDRAM CS0 */
126 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
127 if (dramsize >= 0x13) {
128 dramsize = (1 << (dramsize - 0x13)) << 20;
129 } else {
130 dramsize = 0;
131 }
132
133#endif /* CONFIG_SYS_RAMBOOT */
134
135 /*
136 * On MPC5200B we need to set the special configuration delay in the
137 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
138 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
139 *
140 * "The SDelay should be written to a value of 0x00000004. It is
141 * required to account for changes caused by normal wafer processing
142 * parameters."
143 */
144 svr = get_svr();
145 pvr = get_pvr();
146 if ((SVR_MJREV(svr) >= 2) &&
147 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
148
149 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
150 __asm__ volatile ("sync");
151 }
152
153 return dramsize;
154}
155
156int checkboard (void)
157{
158 puts ("Board: A4M072\n");
159 return 0;
160}
161
162#ifdef CONFIG_PCI
163static struct pci_controller hose;
164
165extern void pci_mpc5xxx_init(struct pci_controller *);
166
167void pci_init_board(void)
168{
169 pci_mpc5xxx_init(&hose);
170}
171#endif
172
173#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
174void
175ft_board_setup(void *blob, bd_t *bd)
176{
177 ft_cpu_setup(blob, bd);
178}
179#endif
180
181int board_eth_init(bd_t *bis)
182{
183 int rv, num_if = 0;
184
185 /* Initialize TSECs first */
186 if ((rv = cpu_eth_init(bis)) >= 0)
187 num_if += rv;
188 else
189 printf("ERROR: failed to initialize FEC.\n");
190
191 if ((rv = pci_eth_init(bis)) >= 0)
192 num_if += rv;
193 else
194 printf("ERROR: failed to initialize PCI Ethernet.\n");
195
196 return num_if;
197}
198/*
199 * Miscellaneous late-boot configurations
200 *
201 * Initialize EEPROM write-protect GPIO pin.
202 */
203int misc_init_r(void)
204{
205#if defined(CONFIG_SYS_EEPROM_WREN)
206 /* Enable GPIO pin */
207 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
208 /* Set direction, output */
209 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
210 /* De-assert write enable */
211 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
212#endif
213 return 0;
214}
215#if defined(CONFIG_SYS_EEPROM_WREN)
216/* Input: <dev_addr> I2C address of EEPROM device to enable.
217 * <state> -1: deliver current state
218 * 0: disable write
219 * 1: enable write
220 * Returns: -1: wrong device address
221 * 0: dis-/en- able done
222 * 0/1: current state if <state> was -1.
223 */
224int eeprom_write_enable (unsigned dev_addr, int state)
225{
226 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
227 return -1;
228 } else {
229 switch (state) {
230 case 1:
231 /* Enable write access */
232 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
233 state = 0;
234 break;
235 case 0:
236 /* Disable write access */
237 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
238 state = 0;
239 break;
240 default:
241 /* Read current status back. */
242 state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
243 CONFIG_SYS_EEPROM_WP));
244 break;
245 }
246 }
247 return state;
248}
249#endif
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200250
251#ifdef CONFIG_CMD_DISPLAY
252#define DISPLAY_BUF_SIZE 2
253static u8 display_buf[DISPLAY_BUF_SIZE];
254static u8 display_putc_pos;
255static u8 display_out_pos;
256
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200257void display_set(int cmd) {
258
259 if (cmd & DISPLAY_CLEAR) {
260 display_buf[0] = display_buf[1] = 0;
261 }
262
263 if (cmd & DISPLAY_HOME) {
264 display_putc_pos = 0;
265 }
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200266}
267
268#define SEG_A (1<<0)
269#define SEG_B (1<<1)
270#define SEG_C (1<<2)
271#define SEG_D (1<<3)
272#define SEG_E (1<<4)
273#define SEG_F (1<<5)
274#define SEG_G (1<<6)
275#define SEG_P (1<<7)
276#define SEG__ 0
277
278/*
279 * +- A -+
280 * | |
281 * F B
282 * | |
283 * +- G -+
284 * | |
285 * E C
286 * | |
287 * +- D -+ P
288 *
289 * 0..9 index 0..9
290 * A..Z index 10..35
291 * - index 36
292 * _ index 37
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200293 * . index 38
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200294 */
295
296#define SYMBOL_DASH (36)
297#define SYMBOL_UNDERLINE (37)
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200298#define SYMBOL_DOT (38)
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200299
300static u8 display_char2seg7_tbl[]=
301{
302 SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */
303 SEG_B | SEG_C, /* 1 */
304 SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */
305 SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */
306 SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */
307 SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */
308 SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */
309 SEG_A | SEG_B | SEG_C, /* 7 */
310 SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */
311 SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */
312 SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */
313 SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */
314 SEG_A | SEG_D | SEG_E | SEG_F, /* C */
315 SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */
316 SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */
317 SEG_A | SEG_E | SEG_F | SEG_G, /* F */
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200318 0, /* g - not displayed */
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200319 SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200320 SEG_B | SEG_C, /* I */
321 0, /* J - not displayed */
322 0, /* K - not displayed */
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200323 SEG_D | SEG_E | SEG_F, /* L */
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200324 0, /* m - not displayed */
325 0, /* n - not displayed */
326 SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200327 SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200328 0, /* q - not displayed */
329 0, /* r - not displayed */
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200330 SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */
331 SEG_D | SEG_E | SEG_F | SEG_G, /* t */
332 SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200333 0, /* V - not displayed */
334 0, /* w - not displayed */
335 0, /* X - not displayed */
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200336 SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200337 0, /* Z - not displayed */
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200338 SEG_G, /* - */
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200339 SEG_D, /* _ */
340 SEG_P /* . */
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200341};
342
343/* Convert char to the LED segments representation */
344static u8 display_char2seg7(char c)
345{
346 u8 val = 0;
347
348 if (c >= '0' && c <= '9')
349 c -= '0';
350 else if (c >= 'a' && c <= 'z')
351 c -= 'a' - 10;
352 else if (c >= 'A' && c <= 'Z')
353 c -= 'A' - 10;
354 else if (c == '-')
355 c = SYMBOL_DASH;
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200356 else if (c == '_')
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200357 c = SYMBOL_UNDERLINE;
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200358 else if (c == '.')
359 c = SYMBOL_DOT;
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200360 else
361 c = ' '; /* display unsupported symbols as space */
362
363 if (c != ' ')
364 val = display_char2seg7_tbl[(int)c];
365
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200366 return val;
367}
368
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200369int display_putc(char c)
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200370{
371 if (display_putc_pos >= DISPLAY_BUF_SIZE)
372 return -1;
373
374 display_buf[display_putc_pos++] = display_char2seg7(c);
375 /* one-symbol message should be steady */
376 if (display_putc_pos == 1)
377 display_buf[display_putc_pos] = display_char2seg7(c);
378
379 return c;
380}
381
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200382/*
Ilya Yanok92d1a402010-09-09 23:03:34 +0200383 * Flush current symbol to the LED display hardware
384 */
385static inline void display_flush(void)
386{
387 u32 val = display_buf[display_out_pos];
388
389 val |= (val << 8) | (val << 16) | (val << 24);
390 out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
391}
392
393/*
394 * Output contents of the software display buffer to the LED display every 0.5s
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200395 */
396void board_show_activity(ulong timestamp)
397{
398 static ulong last;
399 static u8 once;
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200400
401 if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
Ilya Yanok92d1a402010-09-09 23:03:34 +0200402 display_flush();
Ilya Yanokcb5639c2010-09-09 23:03:33 +0200403 display_out_pos ^= 1;
404 last = timestamp;
405 once = 1;
406 }
407}
408
409/*
410 * Empty fake function
411 */
412void show_activity(int arg)
413{
414}
415#endif
Ilya Yanok92d1a402010-09-09 23:03:34 +0200416#if defined (CONFIG_SHOW_BOOT_PROGRESS)
417static int a4m072_status2code(int status, char *buf)
418{
419 char c = 0;
420
421 if (((status > 0) && (status <= 8)) ||
422 ((status >= 100) && (status <= 108)) ||
423 ((status < 0) && (status >= -9)) ||
424 (status == -100) || (status == -101) ||
425 ((status <= -103) && (status >= -113))) {
426 c = '5';
427 } else if (((status >= 9) && (status <= 14)) ||
428 ((status >= 120) && (status <= 123)) ||
429 ((status >= 125) && (status <= 129)) ||
430 ((status >= -13) && (status <= -10)) ||
431 (status == -120) || (status == -122) ||
432 ((status <= -124) && (status >= -127)) ||
433 (status == -129)) {
434 c = '8';
435 } else if (status == 15) {
436 c = '9';
437 } else if ((status <= -30) && (status >= -32)) {
438 c = 'A';
439 } else if (((status <= -35) && (status >= -40)) ||
440 ((status <= -42) && (status >= -51)) ||
441 ((status <= -53) && (status >= -58)) ||
442 (status == -64) ||
443 ((status <= -80) && (status >= -83)) ||
444 (status == -130) || (status == -140) ||
445 (status == -150)) {
446 c = 'B';
447 }
448
449 if (c == 0)
450 return -EINVAL;
451
452 buf[0] = (status < 0) ? '-' : c;
453 buf[1] = c;
454
455 return 0;
456}
457
458void show_boot_progress(int status)
459{
460 char buf[2];
461
462 if (a4m072_status2code(status, buf) < 0)
463 return;
464
Ilya Yanok8f54dd42010-10-21 17:20:10 +0200465 display_putc(buf[0]);
466 display_putc(buf[1]);
Ilya Yanok92d1a402010-09-09 23:03:34 +0200467 display_set(DISPLAY_HOME);
468 display_out_pos = 0; /* reset output position */
469
470 /* we want to flush status 15 now */
Simon Glass578ac1e2011-12-10 11:07:54 +0000471 if (status == BOOTSTAGE_ID_RUN_OS)
Ilya Yanok92d1a402010-09-09 23:03:34 +0200472 display_flush();
473}
474#endif