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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
Paul Gortmakerb30d41c2011-09-17 13:47:47 +000013 * Configuration settings for the SACSng 8260 board.
wdenkfe8c2802002-11-03 00:38:21 +000014 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
Wolfgang Denk2ae18242010-10-06 09:05:45 +020037#define CONFIG_SYS_TEXT_BASE 0x40000000
38
wdenkfe8c2802002-11-03 00:38:21 +000039#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
40
wdenk78137c32003-09-15 18:00:00 +000041#undef CONFIG_LOGBUFFER /* External logbuffer support */
42
wdenkfe8c2802002-11-03 00:38:21 +000043/*****************************************************************************
44 *
45 * These settings must match the way _your_ board is set up
46 *
47 *****************************************************************************/
48
49/* What is the oscillator's (UX2) frequency in Hz? */
50#define CONFIG_8260_CLKIN 66666600
51
52/*-----------------------------------------------------------------------
53 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
54 *-----------------------------------------------------------------------
55 * What should MODCK_H be? It is dependent on the oscillator
56 * frequency, MODCK[1-3], and desired CPM and core frequencies.
57 * Here are some example values (all frequencies are in MHz):
58 *
59 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
60 * ------- ---------- --- --- ---- ----- ----- -----
61 * 0x1 0x5 33 100 133 Open Close Open
62 * 0x1 0x6 33 100 166 Open Open Close
63 * 0x1 0x7 33 100 200 Open Open Open
64 *
65 * 0x2 0x2 33 133 133 Close Open Close
66 * 0x2 0x3 33 133 166 Close Open Open
67 * 0x2 0x4 33 133 200 Open Close Close
68 * 0x2 0x5 33 133 233 Open Close Open
69 * 0x2 0x6 33 133 266 Open Open Close
70 *
71 * 0x5 0x5 66 133 133 Open Close Open
72 * 0x5 0x6 66 133 166 Open Open Close
73 * 0x5 0x7 66 133 200 Open Open Open
74 * 0x6 0x0 66 133 233 Close Close Close
75 * 0x6 0x1 66 133 266 Close Close Open
76 * 0x6 0x2 66 133 300 Close Open Close
77 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_SBC_MODCK_H 0x05
wdenkfe8c2802002-11-03 00:38:21 +000079
80/* Define this if you want to boot from 0x00000100. If you don't define
81 * this, you will need to program the bootloader to 0xfff00000, and
82 * get the hardware reset config words at 0xfe000000. The simplest
83 * way to do that is to program the bootloader at both addresses.
84 * It is suggested that you just let U-Boot live at 0x00000000.
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_SBC_BOOT_LOW 1
wdenkfe8c2802002-11-03 00:38:21 +000087
88/* What should the base address of the main FLASH be and how big is
Wolfgang Denk14d0a022010-10-07 21:51:12 +020089 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk
wdenkfe8c2802002-11-03 00:38:21 +000090 * The main FLASH is whichever is connected to *CS0.
91 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_FLASH0_BASE 0x40000000
93#define CONFIG_SYS_FLASH0_SIZE 2
wdenkfe8c2802002-11-03 00:38:21 +000094
95/* What should the base address of the secondary FLASH be and how big
96 * is it (in Mbytes)? The secondary FLASH is whichever is connected
97 * to *CS6.
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_FLASH1_BASE 0x60000000
100#define CONFIG_SYS_FLASH1_SIZE 2
wdenkfe8c2802002-11-03 00:38:21 +0000101
102/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
103 */
104#define CONFIG_VERY_BIG_RAM 1
105
106/* What should be the base address of SDRAM DIMM and how big is
107 * it (in Mbytes)? This will normally auto-configure via the SPD.
108*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_SDRAM0_BASE 0x00000000
110#define CONFIG_SYS_SDRAM0_SIZE 64
wdenkfe8c2802002-11-03 00:38:21 +0000111
112/*
113 * Memory map example with 64 MB DIMM:
114 *
115 * 0x0000 0000 Exception Vector code, 8k
116 * :
117 * 0x0000 1FFF
118 * 0x0000 2000 Free for Application Use
119 * :
120 * :
121 *
122 * :
123 * :
124 * 0x03F5 FF30 Monitor Stack (Growing downward)
125 * Monitor Stack Buffer (0x80)
126 * 0x03F5 FFB0 Board Info Data
127 * 0x03F6 0000 Malloc Arena
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200128 * : CONFIG_ENV_SECT_SIZE, 16k
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 * : CONFIG_SYS_MALLOC_LEN, 128k
wdenkfe8c2802002-11-03 00:38:21 +0000130 * 0x03FC 0000 RAM Copy of Monitor Code
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 * : CONFIG_SYS_MONITOR_LEN, 256k
132 * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
wdenkfe8c2802002-11-03 00:38:21 +0000133 */
134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
136 CONFIG_SYS_POST_CPU)
wdenkfe8c2802002-11-03 00:38:21 +0000137
138
139/*
140 * select serial console configuration
141 *
142 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
143 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
144 * for SCC).
145 *
146 * if CONFIG_CONS_NONE is defined, then the serial console routines must
147 * defined elsewhere.
148 */
149#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
150#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
151#undef CONFIG_CONS_NONE /* define if console on neither */
152#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
153
154/*
155 * select ethernet configuration
156 *
157 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
158 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
159 * for FCC)
160 *
161 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500162 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkfe8c2802002-11-03 00:38:21 +0000163 */
164
165#undef CONFIG_ETHER_ON_SCC
166#define CONFIG_ETHER_ON_FCC
167#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
168
169#ifdef CONFIG_ETHER_ON_SCC
170#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
171#endif /* CONFIG_ETHER_ON_SCC */
172
173#ifdef CONFIG_ETHER_ON_FCC
174#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
wdenk78137c32003-09-15 18:00:00 +0000175#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
wdenkfe8c2802002-11-03 00:38:21 +0000176#define CONFIG_MII /* MII PHY management */
177#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
178/*
179 * Port pins used for bit-banged MII communictions (if applicable).
180 */
181
182#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200183#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
184 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
185#define MDC_DECLARE MDIO_DECLARE
186
wdenkfe8c2802002-11-03 00:38:21 +0000187#define MDIO_ACTIVE (iop->pdir |= 0x40000000)
188#define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
189#define MDIO_READ ((iop->pdat & 0x40000000) != 0)
190
191#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
192 else iop->pdat &= ~0x40000000
193
194#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
195 else iop->pdat &= ~0x80000000
196
197#define MIIDELAY udelay(50)
198#endif /* CONFIG_ETHER_ON_FCC */
199
200#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
201
202/*
203 * - RX clk is CLK11
204 * - TX clk is CLK12
205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
wdenkfe8c2802002-11-03 00:38:21 +0000207
208#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
209
210/*
211 * - Rx-CLK is CLK13
212 * - Tx-CLK is CLK14
213 * - Select bus for bd/buffers (see 28-13)
214 * - Enable Full Duplex in FSMR
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
217# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
218# define CONFIG_SYS_CPMFCR_RAMTYPE 0
219# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkfe8c2802002-11-03 00:38:21 +0000220
221#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
222
223#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
224
225/*
226 * Configure for RAM tests.
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#undef CONFIG_SYS_DRAM_TEST /* calls other tests in board.c */
wdenkfe8c2802002-11-03 00:38:21 +0000229
230
231/*
232 * Status LED for power up status feedback.
233 */
234#define CONFIG_STATUS_LED 1 /* Status LED enabled */
235
236#define STATUS_LED_PAR im_ioport.iop_ppara
237#define STATUS_LED_DIR im_ioport.iop_pdira
238#define STATUS_LED_ODR im_ioport.iop_podra
239#define STATUS_LED_DAT im_ioport.iop_pdata
240
241#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define STATUS_LED_PERIOD (CONFIG_SYS_HZ)
wdenkfe8c2802002-11-03 00:38:21 +0000243#define STATUS_LED_STATE STATUS_LED_OFF
244#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
wdenkfe8c2802002-11-03 00:38:21 +0000246#define STATUS_LED_STATE1 STATUS_LED_OFF
247#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ/2)
wdenkfe8c2802002-11-03 00:38:21 +0000249#define STATUS_LED_STATE2 STATUS_LED_ON
250
251#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
252
253#define STATUS_LED_YELLOW 0
254#define STATUS_LED_GREEN 1
255#define STATUS_LED_RED 2
256#define STATUS_LED_BOOT 1
257
258
259/*
wdenk1d0350e2002-11-11 21:14:20 +0000260 * Select SPI support configuration
wdenkfe8c2802002-11-03 00:38:21 +0000261 */
wdenk1d0350e2002-11-11 21:14:20 +0000262#define CONFIG_SOFT_SPI /* Enable SPI driver */
263#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */
wdenk8bde7f72003-06-27 21:31:46 +0000264#undef DEBUG_SPI /* Disable SPI debugging */
265
wdenkfe8c2802002-11-03 00:38:21 +0000266/*
267 * Software (bit-bang) SPI driver configuration
268 */
269#ifdef CONFIG_SOFT_SPI
270
271/*
272 * Software (bit-bang) SPI driver configuration
273 */
274#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
275#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
276#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
277
278#undef SPI_INIT /* no port initialization needed */
279#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
Wolfgang Denkced209c2008-07-03 22:39:21 +0200280#define SPI_SDA(bit) do { \
281 if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
282 else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \
283 } while (0)
284#define SPI_SCL(bit) do { \
285 if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
286 else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \
287 } while (0)
wdenk1d0350e2002-11-11 21:14:20 +0000288#define SPI_DELAY /* No delay is needed */
wdenkfe8c2802002-11-03 00:38:21 +0000289#endif /* CONFIG_SOFT_SPI */
290
291
292/*
293 * select I2C support configuration
294 *
295 * Supported configurations are {none, software, hardware} drivers.
296 * If the software driver is chosen, there are some additional
297 * configuration items that the driver uses to drive the port pins.
298 */
299#undef CONFIG_HARD_I2C /* I2C with hardware support */
300#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
302#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkfe8c2802002-11-03 00:38:21 +0000303
304/*
305 * Software (bit-bang) I2C driver configuration
306 */
307#ifdef CONFIG_SOFT_I2C
308#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
309#define I2C_ACTIVE (iop->pdir |= 0x00010000)
310#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
311#define I2C_READ ((iop->pdat & 0x00010000) != 0)
312#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
313 else iop->pdat &= ~0x00010000
314#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
315 else iop->pdat &= ~0x00020000
316#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
317#endif /* CONFIG_SOFT_I2C */
318
319/* Define this to reserve an entire FLASH sector for
320 * environment variables. Otherwise, the environment will be
321 * put in the same sector as U-Boot, and changing variables
322 * will erase U-Boot temporarily
323 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200324#define CONFIG_ENV_IN_OWN_SECT 1
wdenkfe8c2802002-11-03 00:38:21 +0000325
326/* Define this to contain any number of null terminated strings that
327 * will be part of the default enviroment compiled into the boot image.
328 */
329#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk78137c32003-09-15 18:00:00 +0000330"quiet=0\0" \
331"serverip=192.168.123.205\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000332"ipaddr=192.168.123.203\0" \
333"checkhostname=VR8500\0" \
334"reprog="\
wdenk78137c32003-09-15 18:00:00 +0000335 "bootp; " \
wdenkfe8c2802002-11-03 00:38:21 +0000336 "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
337 "protect off 60000000 6003FFFF; " \
338 "erase 60000000 6003FFFF; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100339 "cp.b 140000 60000000 ${filesize}; " \
wdenkfe8c2802002-11-03 00:38:21 +0000340 "protect on 60000000 6003FFFF\0" \
341"copyenv="\
342 "protect off 60040000 6004FFFF; " \
343 "erase 60040000 6004FFFF; " \
344 "cp.b 40040000 60040000 10000; " \
345 "protect on 60040000 6004FFFF\0" \
346"copyprog="\
347 "protect off 60000000 6003FFFF; " \
348 "erase 60000000 6003FFFF; " \
349 "cp.b 40000000 60000000 40000; " \
350 "protect on 60000000 6003FFFF\0" \
351"zapenv="\
352 "protect off 40040000 4004FFFF; " \
353 "erase 40040000 4004FFFF; " \
354 "protect on 40040000 4004FFFF\0" \
355"zapotherenv="\
356 "protect off 60040000 6004FFFF; " \
357 "erase 60040000 6004FFFF; " \
358 "protect on 60040000 6004FFFF\0" \
359"root-on-initrd="\
360 "setenv bootcmd "\
361 "version\\;" \
362 "echo\\;" \
363 "bootp\\;" \
364 "setenv bootargs root=/dev/ram0 rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100365 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000366 "run boot-hook\\;" \
367 "bootm\0" \
368"root-on-initrd-debug="\
369 "setenv bootcmd "\
370 "version\\;" \
371 "echo\\;" \
372 "bootp\\;" \
373 "setenv bootargs root=/dev/ram0 rw debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100374 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000375 "run debug-hook\\;" \
376 "run boot-hook\\;" \
377 "bootm\0" \
378"root-on-nfs="\
379 "setenv bootcmd "\
380 "version\\;" \
381 "echo\\;" \
382 "bootp\\;" \
383 "setenv bootargs root=/dev/nfs rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100384 "nfsroot=\\${serverip}:\\${rootpath} " \
385 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000386 "run boot-hook\\;" \
387 "bootm\0" \
388"root-on-nfs-debug="\
389 "setenv bootcmd "\
390 "version\\;" \
391 "echo\\;" \
392 "bootp\\;" \
393 "setenv bootargs root=/dev/nfs rw debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100394 "nfsroot=\\${serverip}:\\${rootpath} " \
395 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000396 "run debug-hook\\;" \
397 "run boot-hook\\;" \
398 "bootm\0" \
399"debug-checkout="\
400 "setenv checkhostname;" \
401 "setenv ethaddr 00:09:70:00:00:01;" \
402 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100403 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
404 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000405 "run debug-hook;" \
406 "run boot-hook;" \
407 "bootm\0" \
408"debug-hook="\
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100409 "echo ipaddr ${ipaddr};" \
410 "echo serverip ${serverip};" \
411 "echo gatewayip ${gatewayip};" \
412 "echo netmask ${netmask};" \
413 "echo hostname ${hostname}\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000414"ana=run adc ; run dac\0" \
415"adc=run adc-12 ; run adc-34\0" \
Peter Tyser0f89c542009-04-18 22:34:03 -0500416"adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \
417"adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \
418"dac=echo ### DAC ; i2c md 11 81 5\0" \
wdenk78137c32003-09-15 18:00:00 +0000419"boot-hook=echo\0"
wdenkfe8c2802002-11-03 00:38:21 +0000420
421/* What should the console's baud rate be? */
422#define CONFIG_BAUDRATE 9600
423
424/* Ethernet MAC address */
425#define CONFIG_ETHADDR 00:09:70:00:00:00
426
427/* The default Ethernet MAC address can be overwritten just once */
428#ifdef CONFIG_ETHADDR
429#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
430#endif
431
432/*
433 * Define this to do some miscellaneous board-specific initialization.
434 */
435#define CONFIG_MISC_INIT_R
436
437/* Set to a positive value to delay for running BOOTCOMMAND */
438#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
439
440/* Be selective on what keys can delay or stop the autoboot process
441 * To stop use: " "
442 */
443#define CONFIG_AUTOBOOT_KEYED
Stefan Roesef2302d42008-08-06 14:05:38 +0200444#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
wdenkfe8c2802002-11-03 00:38:21 +0000445#define CONFIG_AUTOBOOT_STOP_STR " "
446#undef CONFIG_AUTOBOOT_DELAY_STR
447#define CONFIG_ZERO_BOOTDELAY_CHECK
448#define DEBUG_BOOTKEYS 0
449
450/* Define a command string that is automatically executed when no character
451 * is read on the console interface withing "Boot Delay" after reset.
452 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200453#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
wdenkb79a11c2004-03-25 15:14:43 +0000454#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenkfe8c2802002-11-03 00:38:21 +0000455
wdenk42dfe7a2004-03-14 22:25:36 +0000456#ifdef CONFIG_BOOT_ROOT_INITRD
wdenkfe8c2802002-11-03 00:38:21 +0000457#define CONFIG_BOOTCOMMAND \
458 "version;" \
459 "echo;" \
460 "bootp;" \
461 "setenv bootargs root=/dev/ram0 rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100462 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000463 "run boot-hook;" \
464 "bootm"
465#endif /* CONFIG_BOOT_ROOT_INITRD */
466
wdenk42dfe7a2004-03-14 22:25:36 +0000467#ifdef CONFIG_BOOT_ROOT_NFS
wdenkfe8c2802002-11-03 00:38:21 +0000468#define CONFIG_BOOTCOMMAND \
469 "version;" \
470 "echo;" \
471 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100472 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
473 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000474 "run boot-hook;" \
475 "bootm"
476#endif /* CONFIG_BOOT_ROOT_NFS */
477
478#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
479
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500480/*
481 * BOOTP options
wdenkfe8c2802002-11-03 00:38:21 +0000482 */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500483#define CONFIG_BOOTP_SUBNETMASK
484#define CONFIG_BOOTP_GATEWAY
485#define CONFIG_BOOTP_HOSTNAME
486#define CONFIG_BOOTP_BOOTPATH
487#define CONFIG_BOOTP_BOOTFILESIZE
488#define CONFIG_BOOTP_DNS
489#define CONFIG_BOOTP_DNS2
490#define CONFIG_BOOTP_SEND_HOSTNAME
491
wdenkfe8c2802002-11-03 00:38:21 +0000492
493/* undef this to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_LONGHELP
wdenkfe8c2802002-11-03 00:38:21 +0000495
496/* Monitor Command Prompt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_PROMPT "=> "
wdenkfe8c2802002-11-03 00:38:21 +0000498
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#undef CONFIG_SYS_HUSH_PARSER
500#ifdef CONFIG_SYS_HUSH_PARSER
501#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkfe8c2802002-11-03 00:38:21 +0000502#endif
503
wdenk1d0350e2002-11-11 21:14:20 +0000504/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
505 * of an image is printed by image commands like bootm or iminfo.
506 */
507#define CONFIG_TIMESTAMP
508
wdenk42d1f032003-10-15 23:53:47 +0000509/* If this variable is defined, an environment variable named "ver"
wdenk78137c32003-09-15 18:00:00 +0000510 * is created by U-Boot showing the U-Boot version.
511 */
512#define CONFIG_VERSION_VARIABLE
513
Jon Loeliger46da1e92007-07-04 22:33:30 -0500514
515/*
516 * Command line configuration.
517 */
518#include <config_cmd_default.h>
519
520#define CONFIG_CMD_ELF
521#define CONFIG_CMD_ASKENV
522#define CONFIG_CMD_I2C
523#define CONFIG_CMD_SPI
524#define CONFIG_CMD_SDRAM
525#define CONFIG_CMD_REGINFO
526#define CONFIG_CMD_IMMAP
527#define CONFIG_CMD_IRQ
528#define CONFIG_CMD_PING
529
530#undef CONFIG_CMD_KGDB
531
wdenkfe8c2802002-11-03 00:38:21 +0000532#ifdef CONFIG_ETHER_ON_FCC
Jon Loeliger46da1e92007-07-04 22:33:30 -0500533#define CONFIG_CMD_MII
534#endif
535
wdenkfe8c2802002-11-03 00:38:21 +0000536
537/* Where do the internal registers live? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200538#define CONFIG_SYS_IMMR 0xF0000000
wdenkfe8c2802002-11-03 00:38:21 +0000539
wdenk78137c32003-09-15 18:00:00 +0000540#undef CONFIG_WATCHDOG /* disable the watchdog */
541
wdenkfe8c2802002-11-03 00:38:21 +0000542/*****************************************************************************
543 *
544 * You should not have to modify any of the following settings
545 *
546 *****************************************************************************/
547
548#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
wdenkfe8c2802002-11-03 00:38:21 +0000549#define CONFIG_SACSng 1 /* munged for the SACSng */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500550#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000551
wdenkfe8c2802002-11-03 00:38:21 +0000552/*
553 * Miscellaneous configurable options
554 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
wdenk42d1f032003-10-15 23:53:47 +0000556 /* in the bootm command. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
wdenk42d1f032003-10-15 23:53:47 +0000558 /* "## <message>" from the bootm cmd */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200559#define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
wdenk42d1f032003-10-15 23:53:47 +0000560 /* defined, then the hostname param */
561 /* validated against checkhostname. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
563#define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
wdenk42d1f032003-10-15 23:53:47 +0000564 /* (limited to maximum of 1024 msec) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565#define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
wdenk42d1f032003-10-15 23:53:47 +0000566 /* Check for abort key presses */
567 /* at least once in dependent of the */
568 /* CONFIG_BOOTDELAY value. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200569#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
570#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
wdenk42d1f032003-10-15 23:53:47 +0000571 /* state to the fault LED. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200572#define CONFIG_SYS_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
wdenk42d1f032003-10-15 23:53:47 +0000573 /* the Ethernet link state. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200574#define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
wdenk42d1f032003-10-15 23:53:47 +0000575 /* until the TFTP is successful. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200576#define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
wdenk42d1f032003-10-15 23:53:47 +0000577 /* turn off the STATUS LEDs. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
wdenk42d1f032003-10-15 23:53:47 +0000579 /* incoming data. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
wdenk42d1f032003-10-15 23:53:47 +0000581 /* to signify that tftp is moving. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200582#define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
wdenk42d1f032003-10-15 23:53:47 +0000583 /* flash the status LED. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200584#define CONFIG_SYS_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
wdenk42d1f032003-10-15 23:53:47 +0000585 /* during the tftp file transfer. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200586#define CONFIG_SYS_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
wdenk42d1f032003-10-15 23:53:47 +0000587 /* '#'s from the tftp command. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200588#define CONFIG_SYS_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
wdenk42d1f032003-10-15 23:53:47 +0000589 /* issued during the tftp command. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590#define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
wdenk78137c32003-09-15 18:00:00 +0000591 /* before it gives up. */
592
Jon Loeliger46da1e92007-07-04 22:33:30 -0500593#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200594# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000595#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000597#endif
598
599/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200600#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
wdenkfe8c2802002-11-03 00:38:21 +0000601
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
wdenkfe8c2802002-11-03 00:38:21 +0000603
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000605
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200606#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
607#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkfe8c2802002-11-03 00:38:21 +0000608
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */
610#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
wdenkfe8c2802002-11-03 00:38:21 +0000611 /* the exception vector table */
612 /* to the end of the DRAM */
613 /* less monitor and malloc area */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
615#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
616 + CONFIG_SYS_MALLOC_LEN \
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200617 + CONFIG_ENV_SECT_SIZE \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618 + CONFIG_SYS_STACK_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000619
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
621 - CONFIG_SYS_MEM_END_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000622
623/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200624#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkfe8c2802002-11-03 00:38:21 +0000625
626/*
627 * Low Level Configuration Settings
628 * (address mappings, register initial values, etc.)
629 * You should know what you are doing if you make changes here.
630 */
631
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200632#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
633#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
634#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
635#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
wdenkfe8c2802002-11-03 00:38:21 +0000636
637/*-----------------------------------------------------------------------
638 * Hard Reset Configuration Words
639 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200640#if defined(CONFIG_SYS_SBC_BOOT_LOW)
641# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenkfe8c2802002-11-03 00:38:21 +0000642#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200643# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
644#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
wdenkfe8c2802002-11-03 00:38:21 +0000645
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200646/* get the HRCW ISB field from CONFIG_SYS_IMMR */
647#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
648 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
649 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenkfe8c2802002-11-03 00:38:21 +0000650
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200651#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS10 | \
wdenkfe8c2802002-11-03 00:38:21 +0000652 HRCW_DPPC11 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200653 CONFIG_SYS_SBC_HRCW_IMMR | \
wdenkfe8c2802002-11-03 00:38:21 +0000654 HRCW_MMR00 | \
655 HRCW_LBPC11 | \
656 HRCW_APPC10 | \
657 HRCW_CS10PC00 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200658 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
659 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
wdenkfe8c2802002-11-03 00:38:21 +0000660
661/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200662#define CONFIG_SYS_HRCW_SLAVE1 0
663#define CONFIG_SYS_HRCW_SLAVE2 0
664#define CONFIG_SYS_HRCW_SLAVE3 0
665#define CONFIG_SYS_HRCW_SLAVE4 0
666#define CONFIG_SYS_HRCW_SLAVE5 0
667#define CONFIG_SYS_HRCW_SLAVE6 0
668#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkfe8c2802002-11-03 00:38:21 +0000669
670/*-----------------------------------------------------------------------
671 * Definitions for initial stack pointer and data area (in DPRAM)
672 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200673#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200674#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200675#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200676#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkfe8c2802002-11-03 00:38:21 +0000677
678/*-----------------------------------------------------------------------
679 * Start addresses for the final memory configuration
680 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200681 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
682 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
wdenkfe8c2802002-11-03 00:38:21 +0000683 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200684#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000685
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200686#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
687# define CONFIG_SYS_RAMBOOT
wdenkfe8c2802002-11-03 00:38:21 +0000688#endif
689
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200690#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
691#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000692
693/*
694 * For booting Linux, the board info and command line data
695 * have to be in the first 8 MB of memory, since this is
696 * the maximum mapped by the Linux kernel during initialization.
697 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200698#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000699
700/*-----------------------------------------------------------------------
701 * FLASH and environment organization
702 */
703
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200704#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
705#undef CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
706#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
707#define CONFIG_SYS_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
wdenkfe8c2802002-11-03 00:38:21 +0000708
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200709#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
710#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
wdenkfe8c2802002-11-03 00:38:21 +0000711
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200712#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200713# define CONFIG_ENV_IS_IN_FLASH 1
wdenkfe8c2802002-11-03 00:38:21 +0000714
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200715# ifdef CONFIG_ENV_IN_OWN_SECT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200716# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200717# define CONFIG_ENV_SECT_SIZE 0x10000
wdenkfe8c2802002-11-03 00:38:21 +0000718# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200719# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200720# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
721# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
722# endif /* CONFIG_ENV_IN_OWN_SECT */
wdenkfe8c2802002-11-03 00:38:21 +0000723
724#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200725# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200726# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200727# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200728#endif /* CONFIG_SYS_RAMBOOT */
wdenkfe8c2802002-11-03 00:38:21 +0000729
730/*-----------------------------------------------------------------------
731 * Cache Configuration
732 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200733#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
wdenkfe8c2802002-11-03 00:38:21 +0000734
Jon Loeliger46da1e92007-07-04 22:33:30 -0500735#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200736# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkfe8c2802002-11-03 00:38:21 +0000737#endif
738
739/*-----------------------------------------------------------------------
740 * HIDx - Hardware Implementation-dependent Registers 2-11
741 *-----------------------------------------------------------------------
742 * HID0 also contains cache control - initially enable both caches and
743 * invalidate contents, then the final state leaves only the instruction
744 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
745 * but Soft reset does not.
746 *
747 * HID1 has only read-only information - nothing to set.
748 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200749#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenkfe8c2802002-11-03 00:38:21 +0000750 HID0_DCE |\
751 HID0_ICFI |\
752 HID0_DCI |\
753 HID0_IFEM |\
754 HID0_ABE)
755
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200756#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
wdenkfe8c2802002-11-03 00:38:21 +0000757 HID0_IFEM |\
758 HID0_ABE |\
759 HID0_EMCP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200760#define CONFIG_SYS_HID2 0
wdenkfe8c2802002-11-03 00:38:21 +0000761
762/*-----------------------------------------------------------------------
763 * RMR - Reset Mode Register
764 *-----------------------------------------------------------------------
765 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200766#define CONFIG_SYS_RMR 0
wdenkfe8c2802002-11-03 00:38:21 +0000767
768/*-----------------------------------------------------------------------
769 * BCR - Bus Configuration 4-25
770 *-----------------------------------------------------------------------
771 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200772#define CONFIG_SYS_BCR (BCR_ETM)
wdenkfe8c2802002-11-03 00:38:21 +0000773
774/*-----------------------------------------------------------------------
775 * SIUMCR - SIU Module Configuration 4-31
776 *-----------------------------------------------------------------------
777 */
778
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200779#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
wdenkfe8c2802002-11-03 00:38:21 +0000780 SIUMCR_L2CPC00 |\
781 SIUMCR_APPC10 |\
782 SIUMCR_MMR00)
783
784
785/*-----------------------------------------------------------------------
786 * SYPCR - System Protection Control 11-9
787 * SYPCR can only be written once after reset!
788 *-----------------------------------------------------------------------
789 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
790 */
wdenk78137c32003-09-15 18:00:00 +0000791#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200792#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
wdenk78137c32003-09-15 18:00:00 +0000793 SYPCR_BMT |\
794 SYPCR_PBME |\
795 SYPCR_LBME |\
796 SYPCR_SWRI |\
797 SYPCR_SWP |\
wdenk42d1f032003-10-15 23:53:47 +0000798 SYPCR_SWE)
wdenk78137c32003-09-15 18:00:00 +0000799#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200800#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
wdenkfe8c2802002-11-03 00:38:21 +0000801 SYPCR_BMT |\
802 SYPCR_PBME |\
803 SYPCR_LBME |\
804 SYPCR_SWRI |\
805 SYPCR_SWP)
wdenk78137c32003-09-15 18:00:00 +0000806#endif /* CONFIG_WATCHDOG */
wdenkfe8c2802002-11-03 00:38:21 +0000807
808/*-----------------------------------------------------------------------
809 * TMCNTSC - Time Counter Status and Control 4-40
810 *-----------------------------------------------------------------------
811 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
812 * and enable Time Counter
813 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200814#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
wdenkfe8c2802002-11-03 00:38:21 +0000815 TMCNTSC_ALR |\
816 TMCNTSC_TCF |\
817 TMCNTSC_TCE)
818
819/*-----------------------------------------------------------------------
820 * PISCR - Periodic Interrupt Status and Control 4-42
821 *-----------------------------------------------------------------------
822 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
823 * Periodic timer
824 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200825#define CONFIG_SYS_PISCR (PISCR_PS |\
wdenkfe8c2802002-11-03 00:38:21 +0000826 PISCR_PTF |\
827 PISCR_PTE)
828
829/*-----------------------------------------------------------------------
830 * SCCR - System Clock Control 9-8
831 *-----------------------------------------------------------------------
832 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200833#define CONFIG_SYS_SCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000834
835/*-----------------------------------------------------------------------
836 * RCCR - RISC Controller Configuration 13-7
837 *-----------------------------------------------------------------------
838 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200839#define CONFIG_SYS_RCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000840
841/*
842 * Initialize Memory Controller:
843 *
844 * Bank Bus Machine PortSz Device
845 * ---- --- ------- ------ ------
846 * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
847 * 1 60x GPCM -- bit (Unused)
848 * 2 60x SDRAM 64 bit SDRAM (DIMM)
849 * 3 60x SDRAM 64 bit SDRAM (DIMM)
850 * 4 60x GPCM -- bit (Unused)
851 * 5 60x GPCM -- bit (Unused)
852 * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
853 */
854
855/*-----------------------------------------------------------------------
856 * BR0,BR1 - Base Register
857 * Ref: Section 10.3.1 on page 10-14
858 * OR0,OR1 - Option Register
859 * Ref: Section 10.3.2 on page 10-18
860 *-----------------------------------------------------------------------
861 */
862
863/* Bank 0 - Primary FLASH
864 */
865
866/* BR0 is configured as follows:
867 *
868 * - Base address of 0x40000000
869 * - 16 bit port size
870 * - Data errors checking is disabled
871 * - Read and write access
872 * - GPCM 60x bus
873 * - Access are handled by the memory controller according to MSEL
874 * - Not used for atomic operations
875 * - No data pipelining is done
876 * - Valid
877 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200878#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000879 BRx_PS_16 |\
880 BRx_MS_GPCM_P |\
881 BRx_V)
882
883/* OR0 is configured as follows:
884 *
885 * - 4 MB
886 * - *BCTL0 is asserted upon access to the current memory bank
887 * - *CW / *WE are negated a quarter of a clock earlier
888 * - *CS is output at the same time as the address lines
889 * - Uses a clock cycle length of 5
890 * - *PSDVAL is generated internally by the memory controller
891 * unless *GTA is asserted earlier externally.
892 * - Relaxed timing is generated by the GPCM for accesses
893 * initiated to this memory region.
894 * - One idle clock is inserted between a read access from the
895 * current bank and the next access.
896 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200897#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000898 ORxG_CSNT |\
899 ORxG_ACS_DIV1 |\
900 ORxG_SCY_5_CLK |\
901 ORxG_TRLX |\
902 ORxG_EHTR)
903
904/*-----------------------------------------------------------------------
905 * BR2,BR3 - Base Register
906 * Ref: Section 10.3.1 on page 10-14
907 * OR2,OR3 - Option Register
908 * Ref: Section 10.3.2 on page 10-16
909 *-----------------------------------------------------------------------
910 */
911
912/* Bank 2,3 - SDRAM DIMM
913 */
914
915/* The BR2 is configured as follows:
916 *
917 * - Base address of 0x00000000
918 * - 64 bit port size (60x bus only)
919 * - Data errors checking is disabled
920 * - Read and write access
921 * - SDRAM 60x bus
922 * - Access are handled by the memory controller according to MSEL
923 * - Not used for atomic operations
924 * - No data pipelining is done
925 * - Valid
926 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200927#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000928 BRx_PS_64 |\
929 BRx_MS_SDRAM_P |\
930 BRx_V)
931
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200932#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000933 BRx_PS_64 |\
934 BRx_MS_SDRAM_P |\
935 BRx_V)
936
937/* With a 64 MB DIMM, the OR2 is configured as follows:
938 *
939 * - 64 MB
940 * - 4 internal banks per device
941 * - Row start address bit is A8 with PSDMR[PBI] = 0
942 * - 12 row address lines
943 * - Back-to-back page mode
944 * - Internal bank interleaving within save device enabled
945 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200946#if (CONFIG_SYS_SDRAM0_SIZE == 64)
947#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000948 ORxS_BPD_4 |\
949 ORxS_ROWST_PBI0_A8 |\
950 ORxS_NUMR_12)
951#else
952#error "INVALID SDRAM CONFIGURATION"
953#endif
954
955/*-----------------------------------------------------------------------
956 * PSDMR - 60x Bus SDRAM Mode Register
957 * Ref: Section 10.3.3 on page 10-21
958 *-----------------------------------------------------------------------
959 */
960
961/* Address that the DIMM SPD memory lives at.
962 */
963#define SDRAM_SPD_ADDR 0x50
964
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200965#if (CONFIG_SYS_SDRAM0_SIZE == 64)
wdenkfe8c2802002-11-03 00:38:21 +0000966/* With a 64 MB DIMM, the PSDMR is configured as follows:
967 *
968 * - Bank Based Interleaving,
969 * - Refresh Enable,
970 * - Address Multiplexing where A5 is output on A14 pin
971 * (A6 on A15, and so on),
972 * - use address pins A14-A16 as bank select,
973 * - A9 is output on SDA10 during an ACTIVATE command,
974 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
975 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
976 * is 3 clocks,
977 * - earliest timing for READ/WRITE command after ACTIVATE command is
978 * 2 clocks,
979 * - earliest timing for PRECHARGE after last data was read is 1 clock,
980 * - earliest timing for PRECHARGE after last data was written is 1 clock,
981 * - CAS Latency is 2.
982 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200983#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenkfe8c2802002-11-03 00:38:21 +0000984 PSDMR_SDAM_A14_IS_A5 |\
985 PSDMR_BSMA_A14_A16 |\
986 PSDMR_SDA10_PBI0_A9 |\
987 PSDMR_RFRC_7_CLK |\
988 PSDMR_PRETOACT_3W |\
989 PSDMR_ACTTORW_2W |\
990 PSDMR_LDOTOPRE_1C |\
991 PSDMR_WRC_1C |\
992 PSDMR_CL_2)
993#else
994#error "INVALID SDRAM CONFIGURATION"
995#endif
996
997/*
998 * Shoot for approximately 1MHz on the prescaler.
999 */
1000#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001001#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64
wdenkfe8c2802002-11-03 00:38:21 +00001002#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001003#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
wdenkfe8c2802002-11-03 00:38:21 +00001004#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001005#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
1006#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
wdenkfe8c2802002-11-03 00:38:21 +00001007#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001008#define CONFIG_SYS_PSRT 14
wdenkfe8c2802002-11-03 00:38:21 +00001009
1010
1011/*-----------------------------------------------------------------------
1012 * BR6 - Base Register
1013 * Ref: Section 10.3.1 on page 10-14
1014 * OR6 - Option Register
1015 * Ref: Section 10.3.2 on page 10-18
1016 *-----------------------------------------------------------------------
1017 */
1018
1019/* Bank 6 - Secondary FLASH
1020 *
1021 * The secondary FLASH is connected to *CS6
1022 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001023#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
wdenkfe8c2802002-11-03 00:38:21 +00001024
1025/* BR6 is configured as follows:
1026 *
1027 * - Base address of 0x60000000
1028 * - 16 bit port size
1029 * - Data errors checking is disabled
1030 * - Read and write access
1031 * - GPCM 60x bus
1032 * - Access are handled by the memory controller according to MSEL
1033 * - Not used for atomic operations
1034 * - No data pipelining is done
1035 * - Valid
1036 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001037# define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +00001038 BRx_PS_16 |\
1039 BRx_MS_GPCM_P |\
1040 BRx_V)
1041
1042/* OR6 is configured as follows:
1043 *
1044 * - 2 MB
1045 * - *BCTL0 is asserted upon access to the current memory bank
1046 * - *CW / *WE are negated a quarter of a clock earlier
1047 * - *CS is output at the same time as the address lines
1048 * - Uses a clock cycle length of 5
1049 * - *PSDVAL is generated internally by the memory controller
1050 * unless *GTA is asserted earlier externally.
1051 * - Relaxed timing is generated by the GPCM for accesses
1052 * initiated to this memory region.
1053 * - One idle clock is inserted between a read access from the
1054 * current bank and the next access.
1055 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001056# define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +00001057 ORxG_CSNT |\
1058 ORxG_ACS_DIV1 |\
1059 ORxG_SCY_5_CLK |\
1060 ORxG_TRLX |\
1061 ORxG_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001062#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
wdenkfe8c2802002-11-03 00:38:21 +00001063
wdenkfe8c2802002-11-03 00:38:21 +00001064#endif /* __CONFIG_H */