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wdenk4e5ca3e2003-12-08 01:34:36 +00001/*
wdenkbf9e3b32004-02-12 00:47:09 +00002 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 *
4 * (C) Copyright 2000
wdenk4e5ca3e2003-12-08 01:34:36 +00005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkbf9e3b32004-02-12 00:47:09 +000017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk4e5ca3e2003-12-08 01:34:36 +000018 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27
TsiChungLiew52b01762007-07-05 23:36:16 -050028#include <asm/timer.h>
29#include <asm/immap.h>
Richard Retanubun42a83762009-03-20 15:30:10 -040030#include <watchdog.h>
wdenk4e5ca3e2003-12-08 01:34:36 +000031
TsiChungLiew99c03c12007-08-05 03:58:52 -050032DECLARE_GLOBAL_DATA_PTR;
33
Richard Retanubun42a83762009-03-20 15:30:10 -040034static volatile ulong timestamp = 0;
35
36#ifndef CONFIG_SYS_WATCHDOG_FREQ
37#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
38#endif
stroesecd42dee2004-12-16 17:56:09 +000039
TsiChung Liew8e585f02007-06-18 13:50:13 -050040#if defined(CONFIG_MCFTMR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#ifndef CONFIG_SYS_UDELAY_BASE
TsiChung Liew8e585f02007-06-18 13:50:13 -050042# error "uDelay base not defined!"
43#endif
44
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
TsiChung Liew8e585f02007-06-18 13:50:13 -050046# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
47#endif
TsiChungLiew52b01762007-07-05 23:36:16 -050048extern void dtimer_intr_setup(void);
TsiChung Liew8e585f02007-06-18 13:50:13 -050049
Ingo van Lil3eb90ba2009-11-24 14:09:21 +010050void __udelay(unsigned long usec)
TsiChung Liew8e585f02007-06-18 13:50:13 -050051{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050053 uint start, now, tmp;
54
55 while (usec > 0) {
56 if (usec > 65000)
57 tmp = 65000;
58 else
59 tmp = usec;
60 usec = usec - tmp;
61
62 /* Set up TIMER 3 as timebase clock */
63 timerp->tmr = DTIM_DTMR_RST_RST;
64 timerp->tcn = 0;
65 /* set period to 1 us */
66 timerp->tmr =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067 CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
TsiChungLiew52b01762007-07-05 23:36:16 -050068 DTIM_DTMR_RST_EN;
TsiChung Liew8e585f02007-06-18 13:50:13 -050069
70 start = now = timerp->tcn;
71 while (now < start + tmp)
72 now = timerp->tcn;
73 }
74}
75
76void dtimer_interrupt(void *not_used)
77{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050079
80 /* check for timer interrupt asserted */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081 if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
TsiChung Liew8e585f02007-06-18 13:50:13 -050082 timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
83 timestamp++;
Richard Retanubun42a83762009-03-20 15:30:10 -040084
85 #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
86 if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
87 WATCHDOG_RESET ();
88 }
89 #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
TsiChung Liew8e585f02007-06-18 13:50:13 -050090 return;
91 }
92}
93
Jason Jin444ddfc2011-08-19 10:02:32 +080094int timer_init(void)
TsiChung Liew8e585f02007-06-18 13:50:13 -050095{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050097
98 timestamp = 0;
99
100 timerp->tcn = 0;
101 timerp->trr = 0;
102
103 /* Set up TIMER 4 as clock */
104 timerp->tmr = DTIM_DTMR_RST_RST;
105
TsiChungLiew52b01762007-07-05 23:36:16 -0500106 /* initialize and enable timer interrupt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107 irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500108
109 timerp->tcn = 0;
110 timerp->trr = 1000; /* Interrupt every ms */
111
TsiChungLiew52b01762007-07-05 23:36:16 -0500112 dtimer_intr_setup();
TsiChung Liew8e585f02007-06-18 13:50:13 -0500113
114 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
TsiChung Liew8e585f02007-06-18 13:50:13 -0500116 DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
Jason Jin444ddfc2011-08-19 10:02:32 +0800117
118 return 0;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500119}
120
TsiChung Liew8e585f02007-06-18 13:50:13 -0500121ulong get_timer(ulong base)
122{
123 return (timestamp - base);
124}
125
TsiChung Liew8e585f02007-06-18 13:50:13 -0500126#endif /* CONFIG_MCFTMR */
127
128#if defined(CONFIG_MCFPIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#if !defined(CONFIG_SYS_PIT_BASE)
130# error "CONFIG_SYS_PIT_BASE not defined!"
TsiChung Liew8e585f02007-06-18 13:50:13 -0500131#endif
132
133static unsigned short lastinc;
134
Ingo van Lil3eb90ba2009-11-24 14:09:21 +0100135void __udelay(unsigned long usec)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500136{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500138 uint tmp;
139
140 while (usec > 0) {
141 if (usec > 65000)
142 tmp = 65000;
143 else
144 tmp = usec;
145 usec = usec - tmp;
146
147 /* Set up TIMER 3 as timebase clock */
148 timerp->pcsr = PIT_PCSR_OVW;
149 timerp->pmr = 0;
150 /* set period to 1 us */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500152
153 timerp->pmr = tmp;
154 while (timerp->pcntr > 0) ;
155 }
156}
157
158void timer_init(void)
159{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500161 timestamp = 0;
162
163 /* Set up TIMER 4 as poll clock */
164 timerp->pcsr = PIT_PCSR_OVW;
165 timerp->pmr = lastinc = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
Jason Jin444ddfc2011-08-19 10:02:32 +0800167
168 return 0;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500169}
170
TsiChung Liew8e585f02007-06-18 13:50:13 -0500171ulong get_timer(ulong base)
172{
173 unsigned short now, diff;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500175
176 now = timerp->pcntr;
177 diff = -(now - lastinc);
178
179 timestamp += diff;
180 lastinc = now;
181 return timestamp - base;
182}
183
184void wait_ticks(unsigned long ticks)
185{
Graeme Russ5c8404a2011-07-15 02:18:12 +0000186 u32 start = get_timer(0);
187 while (get_timer(start) < ticks) ;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500188}
189#endif /* CONFIG_MCFPIT */
stroesecd42dee2004-12-16 17:56:09 +0000190
wdenk70f05ac2004-06-09 15:24:18 +0000191/*
192 * This function is derived from PowerPC code (read timebase as long long).
193 * On M68K it just returns the timer value.
194 */
195unsigned long long get_ticks(void)
196{
197 return get_timer(0);
198}
199
Stefan Roesef2302d42008-08-06 14:05:38 +0200200unsigned long usec2ticks(unsigned long usec)
201{
202 return get_timer(usec);
203}
204
wdenk70f05ac2004-06-09 15:24:18 +0000205/*
206 * This function is derived from PowerPC code (timebase clock frequency).
207 * On M68K it returns the number of timer ticks per second.
208 */
TsiChungLiew52b01762007-07-05 23:36:16 -0500209ulong get_tbclk(void)
wdenk70f05ac2004-06-09 15:24:18 +0000210{
211 ulong tbclk;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 tbclk = CONFIG_SYS_HZ;
wdenk70f05ac2004-06-09 15:24:18 +0000213 return tbclk;
214}