blob: 3f2fadbb589a16a91cc83596fc93c0a6cdb3ab7b [file] [log] [blame]
Julien May5c374c92008-06-23 13:57:52 +02001/*
2 * Copyright (C) 2008 Miromico AG
3 *
4 * Configuration settings for the Miromico Hammerhead AVR32 board
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Julien May5c374c92008-06-23 13:57:52 +02007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmannbf018332011-04-18 04:12:41 +000011#define CONFIG_AVR32
12#define CONFIG_AT32AP
13#define CONFIG_AT32AP7000
14#define CONFIG_HAMMERHEAD
Julien May5c374c92008-06-23 13:57:52 +020015
Julien May5c374c92008-06-23 13:57:52 +020016/*
17 * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
18 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
19 * and the PBA bus to run at 1/4 the PLL frequency.
20 */
Andreas Bießmannbf018332011-04-18 04:12:41 +000021#define CONFIG_PLL
22#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_OSC0_HZ 25000000
24#define CONFIG_SYS_PLL0_DIV 1
25#define CONFIG_SYS_PLL0_MUL 5
26#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
27#define CONFIG_SYS_CLKDIV_CPU 0
28#define CONFIG_SYS_CLKDIV_HSB 1
29#define CONFIG_SYS_CLKDIV_PBA 2
30#define CONFIG_SYS_CLKDIV_PBB 1
Julien May5c374c92008-06-23 13:57:52 +020031
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070032/* Reserve VM regions for SDRAM and NOR flash */
33#define CONFIG_SYS_NR_VM_REGIONS 2
34
Julien May5c374c92008-06-23 13:57:52 +020035/*
36 * The PLLOPT register controls the PLL like this:
37 * icp = PLLOPT<2>
38 * ivco = PLLOPT<1:0>
39 *
40 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
41 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_PLL0_OPT 0x04
Julien May5c374c92008-06-23 13:57:52 +020043
Andreas Bießmannf4278b72010-11-04 23:15:31 +000044#define CONFIG_USART_BASE ATMEL_BASE_USART1
45#define CONFIG_USART_ID 1
Julien May5c374c92008-06-23 13:57:52 +020046
47#define CONFIG_HOSTNAME hammerhead
48
49/* User serviceable stuff */
Andreas Bießmannbf018332011-04-18 04:12:41 +000050#define CONFIG_DOS_PARTITION
Julien May5c374c92008-06-23 13:57:52 +020051
Andreas Bießmannbf018332011-04-18 04:12:41 +000052#define CONFIG_CMDLINE_TAG
53#define CONFIG_SETUP_MEMORY_TAGS
54#define CONFIG_INITRD_TAG
Julien May5c374c92008-06-23 13:57:52 +020055
56#define CONFIG_STACKSIZE (2048)
57
58#define CONFIG_BAUDRATE 115200
59#define CONFIG_BOOTARGS \
60 "console=ttyS0 root=mtd1 rootfstype=jffs2"
61#define CONFIG_BOOTCOMMAND \
62 "fsload; bootm"
63
64/*
65 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
66 * data on the serial line may interrupt the boot sequence.
67 */
68#define CONFIG_BOOTDELAY 1
Andreas Bießmannbf018332011-04-18 04:12:41 +000069#define CONFIG_AUTOBOOT
70#define CONFIG_AUTOBOOT_KEYED
Julien May5c374c92008-06-23 13:57:52 +020071#define CONFIG_AUTOBOOT_PROMPT \
Haavard Skinnemoen33eac2b2008-08-20 09:28:36 +020072 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Julien May5c374c92008-06-23 13:57:52 +020073#define CONFIG_AUTOBOOT_DELAY_STR "d"
74#define CONFIG_AUTOBOOT_STOP_STR " "
75
76/*
77 * After booting the board for the first time, new ethernet address
78 * should be generated and assigned to the environment variables
79 * "ethaddr". This is normally done during production.
80 */
Andreas Bießmannbf018332011-04-18 04:12:41 +000081#define CONFIG_OVERWRITE_ETHADDR_ONCE
Julien May5c374c92008-06-23 13:57:52 +020082
83/*
84 * BOOTP/DHCP options
85 */
86#define CONFIG_BOOTP_SUBNETMASK
87#define CONFIG_BOOTP_GATEWAY
88
89/*
90 * Command line configuration.
91 */
92#include <config_cmd_default.h>
93
94#define CONFIG_CMD_ASKENV
95#define CONFIG_CMD_DHCP
96#define CONFIG_CMD_EXT2
97#define CONFIG_CMD_FAT
98#define CONFIG_CMD_JFFS2
99#define CONFIG_CMD_MMC
100#undef CONFIG_CMD_FPGA
101#undef CONFIG_CMD_SETGETDCR
102
Andreas Bießmannbf018332011-04-18 04:12:41 +0000103#define CONFIG_ATMEL_USART
104#define CONFIG_MACB
105#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmannbf018332011-04-18 04:12:41 +0000107#define CONFIG_SYS_HSDRAMC
108#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200109#define CONFIG_GENERIC_ATMEL_MCI
110#define CONFIG_GENERIC_MMC
Julien May5c374c92008-06-23 13:57:52 +0200111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_DCACHE_LINESZ 32
113#define CONFIG_SYS_ICACHE_LINESZ 32
Julien May5c374c92008-06-23 13:57:52 +0200114
115#define CONFIG_NR_DRAM_BANKS 1
116
Andreas Bießmannbf018332011-04-18 04:12:41 +0000117#define CONFIG_SYS_FLASH_CFI
118#define CONFIG_FLASH_CFI_DRIVER
Julien May5c374c92008-06-23 13:57:52 +0200119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_BASE 0x00000000
121#define CONFIG_SYS_FLASH_SIZE 0x800000
122#define CONFIG_SYS_MAX_FLASH_BANKS 1
123#define CONFIG_SYS_MAX_FLASH_SECT 135
Julien May5c374c92008-06-23 13:57:52 +0200124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann15cc55a2011-04-18 04:12:47 +0000126#define CONFIG_SYS_TEXT_BASE 0x00000000
Julien May5c374c92008-06-23 13:57:52 +0200127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_INTRAM_BASE 0x24000000
129#define CONFIG_SYS_INTRAM_SIZE 0x8000
Julien May5c374c92008-06-23 13:57:52 +0200130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_SDRAM_BASE 0x10000000
Julien May5c374c92008-06-23 13:57:52 +0200132
Andreas Bießmannbf018332011-04-18 04:12:41 +0000133#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200134#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Julien May5c374c92008-06-23 13:57:52 +0200136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Julien May5c374c92008-06-23 13:57:52 +0200138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MALLOC_LEN (256*1024)
Julien May5c374c92008-06-23 13:57:52 +0200140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
Julien May5c374c92008-06-23 13:57:52 +0200142
143/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)
145#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Julien May5c374c92008-06-23 13:57:52 +0200146
147/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_PROMPT "Hammerhead> "
149#define CONFIG_SYS_CBSIZE 256
150#define CONFIG_SYS_MAXARGS 16
151#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmannbf018332011-04-18 04:12:41 +0000152#define CONFIG_SYS_LONGHELP
Julien May5c374c92008-06-23 13:57:52 +0200153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
155#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
Julien May5c374c92008-06-23 13:57:52 +0200156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Julien May5c374c92008-06-23 13:57:52 +0200158
159#endif /* __CONFIG_H */