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Marek Vasutfb8ddc22013-04-28 09:20:03 +00001/*
2 * Freescale i.MX23/i.MX28 LCDIF driver
3 *
4 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Marek Vasutfb8ddc22013-04-28 09:20:03 +00007 */
8#include <common.h>
9#include <malloc.h>
10#include <video_fb.h>
11
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/sys_proto.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090015#include <linux/errno.h>
Marek Vasutfb8ddc22013-04-28 09:20:03 +000016#include <asm/io.h>
17
Stefano Babic552a8482017-06-29 10:16:06 +020018#include <asm/mach-imx/dma.h>
Marek Vasut84f957f2013-07-30 23:37:54 +020019
Marek Vasutfb8ddc22013-04-28 09:20:03 +000020#include "videomodes.h"
21
22#define PS2KHZ(ps) (1000000000UL / (ps))
23
24static GraphicDevice panel;
Marek Vasut84f957f2013-07-30 23:37:54 +020025struct mxs_dma_desc desc;
Marek Vasutfb8ddc22013-04-28 09:20:03 +000026
Marek Vasut9de4b722013-07-30 23:37:53 +020027/**
28 * mxsfb_system_setup() - Fine-tune LCDIF configuration
29 *
30 * This function is used to adjust the LCDIF configuration. This is usually
31 * needed when driving the controller in System-Mode to operate an 8080 or
32 * 6800 connected SmartLCD.
33 */
34__weak void mxsfb_system_setup(void)
35{
36}
37
Marek Vasutfb8ddc22013-04-28 09:20:03 +000038/*
Marek Vasutfcea4802017-04-05 13:31:01 +020039 * ARIES M28EVK:
Marek Vasutfb8ddc22013-04-28 09:20:03 +000040 * setenv videomode
41 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
42 * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
Fabio Estevam11f98d12013-05-10 09:14:11 +000043 *
44 * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
45 * setenv videomode
46 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
47 * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
Marek Vasutfb8ddc22013-04-28 09:20:03 +000048 */
49
50static void mxs_lcd_init(GraphicDevice *panel,
51 struct ctfb_res_modes *mode, int bpp)
52{
53 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
54 uint32_t word_len = 0, bus_width = 0;
55 uint8_t valid_data = 0;
56
57 /* Kick in the LCDIF clock */
Peng Fan95ae7002015-10-29 15:54:39 +080058 mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
Marek Vasutfb8ddc22013-04-28 09:20:03 +000059
60 /* Restart the LCDIF block */
61 mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
62
63 switch (bpp) {
64 case 24:
65 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
66 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
67 valid_data = 0x7;
68 break;
69 case 18:
70 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
71 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
72 valid_data = 0x7;
73 break;
74 case 16:
75 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
76 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
77 valid_data = 0xf;
78 break;
79 case 8:
80 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
81 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
82 valid_data = 0xf;
83 break;
84 }
85
86 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
87 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
88 &regs->hw_lcdif_ctrl);
89
90 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
91 &regs->hw_lcdif_ctrl1);
Marek Vasut9de4b722013-07-30 23:37:53 +020092
93 mxsfb_system_setup();
94
Marek Vasutfb8ddc22013-04-28 09:20:03 +000095 writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
96 &regs->hw_lcdif_transfer_count);
97
98 writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
99 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
100 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
101 mode->vsync_len, &regs->hw_lcdif_vdctrl0);
102 writel(mode->upper_margin + mode->lower_margin +
103 mode->vsync_len + mode->yres,
104 &regs->hw_lcdif_vdctrl1);
105 writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
106 (mode->left_margin + mode->right_margin +
107 mode->hsync_len + mode->xres),
108 &regs->hw_lcdif_vdctrl2);
109 writel(((mode->left_margin + mode->hsync_len) <<
110 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
111 (mode->upper_margin + mode->vsync_len),
112 &regs->hw_lcdif_vdctrl3);
113 writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
114 &regs->hw_lcdif_vdctrl4);
115
116 writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
117 writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);
118
119 /* Flush FIFO first */
120 writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
121
Marek Vasut9de4b722013-07-30 23:37:53 +0200122#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
Marek Vasutfb8ddc22013-04-28 09:20:03 +0000123 /* Sync signals ON */
124 setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
Marek Vasut9de4b722013-07-30 23:37:53 +0200125#endif
Marek Vasutfb8ddc22013-04-28 09:20:03 +0000126
127 /* FIFO cleared */
128 writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
129
130 /* RUN! */
131 writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
132}
133
Peng Fana3c252d2015-10-29 15:54:49 +0800134void lcdif_power_down(void)
135{
136 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
137 int timeout = 1000000;
138
Fabio Estevamb24cf852017-02-22 10:40:22 -0300139 if (!panel.frameAdrs)
140 return;
141
Peng Fana3c252d2015-10-29 15:54:49 +0800142 writel(panel.frameAdrs, &regs->hw_lcdif_cur_buf_reg);
143 writel(panel.frameAdrs, &regs->hw_lcdif_next_buf_reg);
144 writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
145 while (--timeout) {
146 if (readl(&regs->hw_lcdif_ctrl1_reg) &
147 LCDIF_CTRL1_VSYNC_EDGE_IRQ)
148 break;
149 udelay(1);
150 }
151 mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
152}
153
Marek Vasutfb8ddc22013-04-28 09:20:03 +0000154void *video_hw_init(void)
155{
156 int bpp = -1;
157 char *penv;
158 void *fb;
159 struct ctfb_res_modes mode;
160
161 puts("Video: ");
162
163 /* Suck display configuration from "videomode" variable */
Simon Glass00caae62017-08-03 12:22:12 -0600164 penv = env_get("videomode");
Marek Vasutfb8ddc22013-04-28 09:20:03 +0000165 if (!penv) {
Fabio Estevam620ca1c2013-06-26 16:08:13 -0300166 puts("MXSFB: 'videomode' variable not set!\n");
Marek Vasutfb8ddc22013-04-28 09:20:03 +0000167 return NULL;
168 }
169
170 bpp = video_get_params(&mode, penv);
171
172 /* fill in Graphic device struct */
173 sprintf(panel.modeIdent, "%dx%dx%d",
174 mode.xres, mode.yres, bpp);
175
176 panel.winSizeX = mode.xres;
177 panel.winSizeY = mode.yres;
178 panel.plnSizeX = mode.xres;
179 panel.plnSizeY = mode.yres;
180
181 switch (bpp) {
182 case 24:
183 case 18:
184 panel.gdfBytesPP = 4;
185 panel.gdfIndex = GDF_32BIT_X888RGB;
186 break;
187 case 16:
188 panel.gdfBytesPP = 2;
189 panel.gdfIndex = GDF_16BIT_565RGB;
190 break;
191 case 8:
192 panel.gdfBytesPP = 1;
193 panel.gdfIndex = GDF__8BIT_INDEX;
194 break;
195 default:
196 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
197 return NULL;
198 }
199
200 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
201
202 /* Allocate framebuffer */
Marek Vasute57baf52013-07-30 23:37:52 +0200203 fb = memalign(ARCH_DMA_MINALIGN,
204 roundup(panel.memSize, ARCH_DMA_MINALIGN));
Marek Vasutfb8ddc22013-04-28 09:20:03 +0000205 if (!fb) {
206 printf("MXSFB: Error allocating framebuffer!\n");
207 return NULL;
208 }
209
210 /* Wipe framebuffer */
211 memset(fb, 0, panel.memSize);
212
213 panel.frameAdrs = (u32)fb;
214
215 printf("%s\n", panel.modeIdent);
216
217 /* Start framebuffer */
218 mxs_lcd_init(&panel, &mode, bpp);
219
Marek Vasut84f957f2013-07-30 23:37:54 +0200220#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
221 /*
222 * If the LCD runs in system mode, the LCD refresh has to be triggered
223 * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
224 * having to set this bit manually after every single change in the
225 * framebuffer memory, we set up specially crafted circular DMA, which
226 * sets the RUN bit, then waits until it gets cleared and repeats this
227 * infinitelly. This way, we get smooth continuous updates of the LCD.
228 */
229 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
230
231 memset(&desc, 0, sizeof(struct mxs_dma_desc));
232 desc.address = (dma_addr_t)&desc;
233 desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
234 MXS_DMA_DESC_WAIT4END |
235 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
236 desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
237 desc.cmd.next = (uint32_t)&desc.cmd;
238
239 /* Execute the DMA chain. */
240 mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
241#endif
242
Marek Vasutfb8ddc22013-04-28 09:20:03 +0000243 return (void *)&panel;
244}