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Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +09001/*
2 * Configuation settings for the Renesas SH7763RDP board
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +09008 */
9
10#ifndef __SH7763RDP_H
11#define __SH7763RDP_H
12
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090013#define CONFIG_CPU_SH7763 1
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090014#define __LITTLE_ENDIAN 1
15
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090016#define CONFIG_ENV_OVERWRITE 1
17
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020018#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090019#undef CONFIG_SHOW_BOOT_PROGRESS
20
21/* SCIF */
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090022#define CONFIG_CONS_SCIF2 1
23
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090026 settings for this board */
27
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090028/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
30#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
31#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
32#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090033
34/* Flash(NOR) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_FLASH_BASE (0xA0000000)
36#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
37#define CONFIG_SYS_MAX_FLASH_BANKS (1)
38#define CONFIG_SYS_MAX_FLASH_SECT (520)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090039
Bin Menga1875592016-02-05 19:30:11 -080040/* U-Boot setting */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
42#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
43#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090044/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090047
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020049#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#undef CONFIG_SYS_FLASH_QUIET_TEST
51#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090052/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090054/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090056/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090058/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090060/* Use hardware flash sectors protection instead of U-Boot software protection */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#undef CONFIG_SYS_FLASH_PROTECTION
62#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020063#define CONFIG_ENV_SECT_SIZE (128 * 1024)
64#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
66/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
67#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020068#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090070
71/* Clock */
72#define CONFIG_SYS_CLK_FREQ 66666666
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090073#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
74#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020075#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090076
Nobuhiro Iwamatsuba932442008-08-08 16:30:23 +090077/* Ether */
Nobuhiro Iwamatsuba932442008-08-08 16:30:23 +090078#define CONFIG_SH_ETHER_USE_PORT (1)
79#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
Yoshihiro Shimodac8ceca92011-10-31 10:44:18 +090080#define CONFIG_BITBANGMII
81#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsua80a6612012-05-16 10:23:21 +090082#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Nobuhiro Iwamatsuba932442008-08-08 16:30:23 +090083
Nobuhiro Iwamatsu7faddae2008-06-09 13:39:57 +090084#endif /* __SH7763RDP_H */