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Phil Edworthy99744b72012-05-15 22:15:51 +00001/*
2 * Configuation settings for the Renesas RSK2+SH7269 board
3 *
4 * Copyright (C) 2012 Renesas Electronics Europe Ltd.
5 * Copyright (C) 2012 Phil Edworthy
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Phil Edworthy99744b72012-05-15 22:15:51 +00008 */
9
10#ifndef __RSK7269_H
11#define __RSK7269_H
12
Phil Edworthy99744b72012-05-15 22:15:51 +000013#define CONFIG_CPU_SH7269 1
Phil Edworthy99744b72012-05-15 22:15:51 +000014
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020015#define CONFIG_DISPLAY_BOARDINFO
16
Phil Edworthy99744b72012-05-15 22:15:51 +000017#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
18
19#define CONFIG_SYS_LONGHELP /* undef to save memory */
Phil Edworthy99744b72012-05-15 22:15:51 +000020#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */
Phil Edworthy99744b72012-05-15 22:15:51 +000021
22/* Serial */
Phil Edworthy99744b72012-05-15 22:15:51 +000023#define CONFIG_CONS_SCIF7
24
25/* Memory */
26/* u-boot relocated to top 256KB of ram */
27#define CONFIG_SYS_TEXT_BASE 0x0DFC0000
28#define CONFIG_SYS_SDRAM_BASE 0x0C000000
29#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
30
31#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
32#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
33#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
34#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
35#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
36
37/* NOR Flash */
38#define CONFIG_FLASH_CFI_DRIVER
39#define CONFIG_SYS_FLASH_CFI
40#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
41#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
42#define CONFIG_SYS_MAX_FLASH_BANKS 1
43#define CONFIG_SYS_MAX_FLASH_SECT 512
44
Phil Edworthy99744b72012-05-15 22:15:51 +000045#define CONFIG_ENV_OFFSET (128 * 1024)
46#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
47#define CONFIG_ENV_SECT_SIZE (64 * 1024)
48#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
49
50/* Board Clock */
51#define CONFIG_SYS_CLK_FREQ 66125000
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090052#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
53#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Phil Edworthy99744b72012-05-15 22:15:51 +000054#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
Nobuhiro Iwamatsu8f0960e2014-01-08 14:57:30 +090055#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
Phil Edworthy99744b72012-05-15 22:15:51 +000056
Phil Edworthy99744b72012-05-15 22:15:51 +000057#endif /* __RSK7269_H */