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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
4 *
5 * (C) Copyright 2001
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * Configuation settings for the miniHiPerCam.
9 *
10 * -----------------------------------------------------------------
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkc837dcb2004-01-20 23:12:12 +000021 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenke2211742002-11-02 23:30:20 +000022 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/*
31 * board/config.h - configuration options, board specific
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_MHPC 1 /* on a miniHiPerCam */
43#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */
44#define CONFIG_MISC_INIT_R 1
wdenke2211742002-11-02 23:30:20 +000045
46#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
47#undef CONFIG_8xx_CONS_SMC1
wdenkc837dcb2004-01-20 23:12:12 +000048#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
wdenke2211742002-11-02 23:30:20 +000049#undef CONFIG_8xx_CONS_NONE
50#define CONFIG_BAUDRATE 9600
51#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52
wdenkc837dcb2004-01-20 23:12:12 +000053#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
wdenke2211742002-11-02 23:30:20 +000054
wdenkc837dcb2004-01-20 23:12:12 +000055#define CONFIG_ENV_OVERWRITE 1
56#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
wdenke2211742002-11-02 23:30:20 +000057
wdenkc837dcb2004-01-20 23:12:12 +000058#undef CONFIG_BOOTARGS
wdenke2211742002-11-02 23:30:20 +000059#define CONFIG_BOOTCOMMAND \
60 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenke2211742002-11-02 23:30:20 +000063 "bootm"
64
65#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
66#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
67
68#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc837dcb2004-01-20 23:12:12 +000069#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
wdenke2211742002-11-02 23:30:20 +000070
wdenkc837dcb2004-01-20 23:12:12 +000071#undef CONFIG_UCODE_PATCH
wdenke2211742002-11-02 23:30:20 +000072
73/* enable I2C and select the hardware/software driver */
wdenkc837dcb2004-01-20 23:12:12 +000074#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenke2211742002-11-02 23:30:20 +000075#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
76/*
77 * Software (bit-bang) I2C driver configuration
78 */
79#define PB_SCL 0x00000020 /* PB 26 */
80#define PB_SDA 0x00000010 /* PB 27 */
81
82#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
83#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
84#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
85#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
86#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenkc837dcb2004-01-20 23:12:12 +000087 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenke2211742002-11-02 23:30:20 +000088#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenkc837dcb2004-01-20 23:12:12 +000089 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenke2211742002-11-02 23:30:20 +000090#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
91
wdenkc837dcb2004-01-20 23:12:12 +000092#define CFG_I2C_SPEED 50000
93#define CFG_I2C_SLAVE 0xFE
94#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */
95#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
96/* mask of address bits that overflow into the "EEPROM chip address" */
97#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
98#define CFG_EEPROM_PAGE_WRITE_BITS 3
99#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenke2211742002-11-02 23:30:20 +0000100
wdenkc837dcb2004-01-20 23:12:12 +0000101#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
102#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */
103#define LCD_VIDEO_COLS 640
104#define LCD_VIDEO_ROWS 480
105#define LCD_VIDEO_FG 255
106#define LCD_VIDEO_BG 0
wdenke2211742002-11-02 23:30:20 +0000107
wdenkc837dcb2004-01-20 23:12:12 +0000108#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */
109#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */
wdenke2211742002-11-02 23:30:20 +0000110#define CONFIG_VIDEO_LOGO
111
wdenkc837dcb2004-01-20 23:12:12 +0000112#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */
113#define VIDEO_TSTC_FCT serial_tstc
114#define VIDEO_GETC_FCT serial_getc
wdenke2211742002-11-02 23:30:20 +0000115
wdenkc837dcb2004-01-20 23:12:12 +0000116#define CONFIG_BR0_WORKAROUND 1
wdenke2211742002-11-02 23:30:20 +0000117
118#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk8bde7f72003-06-27 21:31:46 +0000119 CFG_CMD_DATE | \
120 CFG_CMD_EEPROM | \
121 CFG_CMD_ELF | \
122 CFG_CMD_I2C | \
123 CFG_CMD_JFFS2 | \
124 CFG_CMD_REGINFO )
wdenke2211742002-11-02 23:30:20 +0000125
126#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
127
128/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
129#include <cmd_confdefs.h>
130
131/*
132 * Miscellaneous configurable options
133 */
wdenkc837dcb2004-01-20 23:12:12 +0000134#define CFG_LONGHELP /* undef to save memory */
135#define CFG_PROMPT "=> " /* Monitor Command Prompt */
wdenke2211742002-11-02 23:30:20 +0000136#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +0000137#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000138#else
wdenkc837dcb2004-01-20 23:12:12 +0000139#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000140#endif
wdenkc837dcb2004-01-20 23:12:12 +0000141#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
142#define CFG_MAXARGS 16 /* max number of command args */
wdenke2211742002-11-02 23:30:20 +0000143#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
144
145#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
146#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
147
wdenkc837dcb2004-01-20 23:12:12 +0000148#define CFG_LOAD_ADDR 0x300000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000149
wdenkc837dcb2004-01-20 23:12:12 +0000150#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000151
152#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
153
154/*
155 * Low Level Configuration Settings
156 * (address mappings, register initial values, etc.)
157 * You should know what you are doing if you make changes here.
158 */
159
160/*-----------------------------------------------------------------------
161 * Physical memory map
162 */
163#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/
164
165/*-----------------------------------------------------------------------
166 * Definitions for initial stack pointer and data area (in DPRAM)
167 */
168#define CFG_INIT_RAM_ADDR CFG_IMMR
wdenkc837dcb2004-01-20 23:12:12 +0000169#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
170#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
171#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
172#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000173
174/*-----------------------------------------------------------------------
175 * Start addresses for the final memory configuration
176 * (Set up by the startup code)
177 * Please note that CFG_SDRAM_BASE _must_ start at 0
178 */
wdenkc837dcb2004-01-20 23:12:12 +0000179#define CFG_SDRAM_BASE 0x00000000
wdenke2211742002-11-02 23:30:20 +0000180#define CFG_FLASH_BASE 0xfe000000
181
wdenkc837dcb2004-01-20 23:12:12 +0000182#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
183#undef CFG_MONITOR_BASE /* to run U-Boot from RAM */
wdenke2211742002-11-02 23:30:20 +0000184#define CFG_MONITOR_BASE CFG_FLASH_BASE
wdenkc837dcb2004-01-20 23:12:12 +0000185#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000186
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200187/*
188 * JFFS2 partitions
189 *
190 */
191/* No command line, one static partition, whole device */
192#undef CONFIG_JFFS2_CMDLINE
193#define CONFIG_JFFS2_DEV "nor0"
194#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
195#define CONFIG_JFFS2_PART_OFFSET 0x00000000
196
197/* mtdparts command line support */
198/* Note: fake mtd_id used, no linux mtd map file */
199/*
200#define CONFIG_JFFS2_CMDLINE
201#define MTDIDS_DEFAULT "nor0=mhpc-0"
202#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)"
203*/
wdenke2211742002-11-02 23:30:20 +0000204
205/*
206 * For booting Linux, the board info and command line data
207 * have to be in the first 8 MB of memory, since this is
208 * the maximum mapped by the Linux kernel during initialization.
209 */
wdenkc837dcb2004-01-20 23:12:12 +0000210#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */
wdenke2211742002-11-02 23:30:20 +0000211
212/*-----------------------------------------------------------------------
213 * FLASH organization
214 */
215#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
216#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
217
218#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
219#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc837dcb2004-01-20 23:12:12 +0000220#define CFG_ENV_IS_IN_FLASH 1
221#define CFG_ENV_OFFSET CFG_MONITOR_LEN /* Offset of Environment */
222#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */
wdenke2211742002-11-02 23:30:20 +0000223
224/*-----------------------------------------------------------------------
225 * Cache Configuration
226 */
227#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
228#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
229#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
230#endif
231
232/*-----------------------------------------------------------------------
233 * SYPCR - System Protection Control 11-9
234 * SYPCR can only be written once after reset!
235 *-----------------------------------------------------------------------
236 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
237 */
238#if defined(CONFIG_WATCHDOG)
239#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
240 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
241#else
242#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8bde7f72003-06-27 21:31:46 +0000243 SYPCR_SWP)
wdenke2211742002-11-02 23:30:20 +0000244#endif
245
246/*-----------------------------------------------------------------------
247 * SIUMCR - SIU Module Configuration 11-6
248 *-----------------------------------------------------------------------
249 * PCMCIA config., multi-function pin tri-state
250 */
251#define CFG_SIUMCR (SIUMCR_SEME)
252
253/*-----------------------------------------------------------------------
254 * TBSCR - Time Base Status and Control 11-26
255 *-----------------------------------------------------------------------
256 * Clear Reference Interrupt Status, Timebase freezing enabled
257 */
258#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
259
260/*-----------------------------------------------------------------------
261 * PISCR - Periodic Interrupt Status and Control 11-31
262 *-----------------------------------------------------------------------
263 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
264 */
265#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
266
267/*-----------------------------------------------------------------------
268 * RTCSC - Real-Time Clock Status and Control Register 12-18
269 *-----------------------------------------------------------------------
270 */
271#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
272
273/*-----------------------------------------------------------------------
274 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
275 *-----------------------------------------------------------------------
276 * Reset PLL lock status sticky bit, timer expired status bit and timer
277 * interrupt status bit - leave PLL multiplication factor unchanged !
278 */
279#define MPC8XX_SPEED 50000000L
wdenkc837dcb2004-01-20 23:12:12 +0000280#define MPC8XX_XIN 5000000L /* ref clk */
wdenke2211742002-11-02 23:30:20 +0000281#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
282#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
wdenk8bde7f72003-06-27 21:31:46 +0000283 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenke2211742002-11-02 23:30:20 +0000284
285/*-----------------------------------------------------------------------
286 * SCCR - System Clock and reset Control Register 15-27
287 *-----------------------------------------------------------------------
288 * Set clock output, timebase and RTC source and divider,
289 * power management and some other internal clocks
290 */
291
292#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */
293#define CFG_SCCR (SCCR_TBS | SCCR_DFLCD001)
294
295
296/*-----------------------------------------------------------------------
297 * MAMR settings for SDRAM - 16-14
298 * => 0xC080200F
299 *-----------------------------------------------------------------------
300 * periodic timer for refresh
301 */
302#define CFG_MAMR_PTA 0xC0
303#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
304
305/*
306 * BR0 and OR0 (FLASH) used to re-map FLASH
307 */
308
309/* allow for max 8 MB of Flash */
310#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/
311#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/
312#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
313#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
314
315#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
316
317#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
318#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
319#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
320
321/*
322 * BR1 and OR1 (SDRAM)
323 */
324#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
wdenkc837dcb2004-01-20 23:12:12 +0000325#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
326#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */
wdenke2211742002-11-02 23:30:20 +0000327
328/* SDRAM timing: drive GPL5 high on first cycle */
329#define CFG_OR_TIMING_SDRAM (OR_G5LS)
330
331#define CFG_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM )
332#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
333
334/*
335 * BR2/OR2 - DIMM
336 */
337#define CFG_OR2 (OR_ACS_DIV4)
338#define CFG_BR2 (BR_MS_UPMA)
339
340/*
341 * BR3/OR3 - DIMM
342 */
343#define CFG_OR3 (OR_ACS_DIV4)
344#define CFG_BR3 (BR_MS_UPMA)
345
346/*
347 * BR4/OR4
348 */
349#define CFG_OR4 0
350#define CFG_BR4 0
351
352/*
353 * BR5/OR5
354 */
355#define CFG_OR5 0
356#define CFG_BR5 0
357
358/*
359 * BR6/OR6
360 */
361#define CFG_OR6 0
362#define CFG_BR6 0
363
364/*
365 * BR7/OR7
366 */
367#define CFG_OR7 0
368#define CFG_BR7 0
369
370
371/*-----------------------------------------------------------------------
372 * Debug Entry Mode
373 *-----------------------------------------------------------------------
374 *
375 */
wdenkc837dcb2004-01-20 23:12:12 +0000376#define CFG_DER 0
wdenke2211742002-11-02 23:30:20 +0000377
378/*
379 * Internal Definitions
380 *
381 * Boot Flags
382 */
wdenkc837dcb2004-01-20 23:12:12 +0000383#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenke2211742002-11-02 23:30:20 +0000384#define BOOTFLAG_WARM 0x02 /* Software reboot */
385
386#endif /* __CONFIG_H */