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wdenk652a10c2005-01-09 23:48:14 +00001/*
2 * (C) Copyright 2001
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * board/config.h - configuration options, board specific
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35#define CONFIG_405GP 1 /* This is a PPC405 CPU */
36#define CONFIG_4xx 1 /* ...member of PPC4xx family */
37#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */
38
39#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
40#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
41
42#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
43
44#define CONFIG_BAUDRATE 9600
45
46#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
47
48#define CONFIG_RAMBOOT \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010049 "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
50 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk652a10c2005-01-09 23:48:14 +000051 "bootm ffc00000 ffca0000"
52#define CONFIG_NFSBOOT \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010053 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
54 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk652a10c2005-01-09 23:48:14 +000055 "bootm ffc00000"
56
57#undef CONFIG_BOOTARGS
Wolfgang Denkfe126d82005-11-20 21:40:11 +010058#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */
wdenk652a10c2005-01-09 23:48:14 +000059
60
61#define CONFIG_MII 1 /* MII PHY management */
62#define CONFIG_PHY_ADDR 0 /* PHY address */
63#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
64
65#define CONFIG_EXTRA_ENV_SETTINGS \
66 "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
67 "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
68 "f=0x08 tn=sbc405 o=emac \0" \
69 "env_startaddr=FF000000\0" \
70 "env_endaddr=FF03FFFF\0" \
71 "loadfile=vxWorks.st\0" \
72 "loadaddr=0x01000000\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010073 "net_load=tftpboot ${loadaddr} ${loadfile}\0" \
wdenk652a10c2005-01-09 23:48:14 +000074 "uboot_startaddr=FFFC0000\0" \
75 "uboot_endaddr=FFFFFFFF\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010076 "update=tftp ${loadaddr} u-boot.bin;" \
77 "protect off ${uboot_startaddr} ${uboot_endaddr};" \
78 "era ${uboot_startaddr} ${uboot_endaddr};" \
79 "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
80 "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
81 "zapenv=protect off ${env_startaddr} ${env_endaddr};" \
82 "era ${env_startaddr} ${env_endaddr};" \
83 "protect on ${env_startaddr} ${env_endaddr}\0"
wdenk652a10c2005-01-09 23:48:14 +000084
85#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
86
87#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
88
89#define CONFIG_ENV_OVERWRITE
90
91#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
92 CFG_CMD_BSP | \
93 CFG_CMD_ELF | \
94 CFG_CMD_I2C | \
95 CFG_CMD_IRQ | \
96 CFG_CMD_MII | \
97 CFG_CMD_PCI | \
98 CFG_CMD_PING | \
99 CFG_CMD_SDRAM | \
100 0 )
101
102/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
103#include <cmd_confdefs.h>
104
105#undef CONFIG_WATCHDOG /* watchdog disabled */
106
107#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
108
109#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
110#define CONFIG_IPADDR 192.168.193.102
111#define CONFIG_NETMASK 255.255.255.224
112#define CONFIG_SERVERIP 192.168.193.119
113#define CONFIG_GATEWAYIP 192.168.193.97
114
115/*
116 * Miscellaneous configurable options
117 */
118#define CFG_LONGHELP /* undef to save memory */
119#define CFG_PROMPT "=> " /* Monitor Command Prompt */
120
121#undef CFG_HUSH_PARSER /* use "hush" command parser */
122#ifdef CFG_HUSH_PARSER
123#define CFG_PROMPT_HUSH_PS2 "> "
124#endif
125
126#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
127#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
128#else
129#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
130#endif
131#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
132#define CFG_MAXARGS 16 /* max number of command args */
133#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
134
135#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
136#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
137
138#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
139#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
140#define CFG_BASE_BAUD 691200
141
142/* The following table includes the supported baudrates */
143#define CFG_BAUDRATE_TABLE \
144 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
145 57600, 115200, 230400, 460800, 921600 }
146
147#define CFG_LOAD_ADDR 0x100000 /* default load address */
148#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
149
150#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
151
152#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
153
154#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
155
156#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
157#undef CONFIG_SOFT_I2C /* I2C bit-banged */
158#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
159#define CFG_I2C_SLAVE 0x7F
160
161/*-----------------------------------------------------------------------
162 * PCI stuff
163 *-----------------------------------------------------------------------
164 */
165#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
166#define PCI_HOST_FORCE 1 /* configure as pci host */
167#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
168
169#define CONFIG_PCI /* include pci support */
170#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
171#define CONFIG_PCI_PNP /* do pci plug-and-play */
172 /* resource configuration */
173
174#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
175
176#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
177#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
178#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
179#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
180#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
181#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
182#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
183#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
184#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
185
186/*-----------------------------------------------------------------------
187 * Start addresses for the final memory configuration
188 * (Set up by the startup code)
189 * Please note that CFG_SDRAM_BASE _must_ start at 0
190 */
191#define CFG_SDRAM_BASE 0x00000000
192#define CFG_MONITOR_BASE 0xFFFC0000
193#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
194#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
195
196/*
197 * For booting Linux, the board info and command line data
198 * have to be in the first 8 MB of memory, since this is
199 * the maximum mapped by the Linux kernel during initialization.
200 */
201#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
202
203/*-----------------------------------------------------------------------
204 * FLASH organization
205 */
206#define CFG_FLASH_BASE 0xFF000000
207#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
208#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
209#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
210#define CFG_FLASH_INCREMENT 0x01000000
211#undef CFG_FLASH_PROTECTION /* don't use hardware protection */
212#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
213#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
214#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
215#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
216
217/*-----------------------------------------------------------------------
218 * Environment Variable setup
219 */
220#define CFG_ENV_ADDR CFG_FLASH_BASE /* starting right at the beginning */
221#define CFG_ENV_IS_IN_FLASH 1
222#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
223#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
224#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
225
226/*-----------------------------------------------------------------------
227 * Cache Configuration
228 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200229#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
wdenk652a10c2005-01-09 23:48:14 +0000230 /* have only 8kB, 16kB is save here */
231#define CFG_CACHELINE_SIZE 32 /* ... */
232#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
233#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
234#endif
235
236/*-----------------------------------------------------------------------
237 * External Bus Controller (EBC) Setup
238 */
239#define FLASH0_BA CFG_FLASH_BASE /* FLASH 0 Base Address */
240
241/* Memory Bank 0 (Flash Bank 0) initialization */
242#define CFG_EBC_PB0AP 0x92015480
243#define CFG_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
244
245/*-----------------------------------------------------------------------
246 * Definitions for initial stack pointer and data area (in data cache)
247 */
248
249/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
250#define CFG_TEMP_STACK_OCM 1
251
252/* On Chip Memory location */
253#define CFG_OCM_DATA_ADDR 0xF8000000
254#define CFG_OCM_DATA_SIZE 0x1000
255
256#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
257#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
258#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
259#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
260#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
261
262/*-----------------------------------------------------------------------
263 * Definitions for Serial Presence Detect EEPROM address
264 * (to get SDRAM settings)
265 */
266#define SPD_EEPROM_ADDRESS 0x50
267#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
268
269/*
270 * Internal Definitions
271 *
272 * Boot Flags
273 */
274#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
275#define BOOTFLAG_WARM 0x02 /* Software reboot */
276
277#endif /* __CONFIG_H */