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Reinhard Arltc2e49f72009-07-25 06:19:12 +02001/*
2 * esd vme8349 U-Boot configuration file
3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
4 *
Wolfgang Denk2ae18242010-10-06 09:05:45 +02005 * (C) Copyright 2006-2010
Reinhard Arltc2e49f72009-07-25 06:19:12 +02006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * reinhard.arlt@esd-electronics.de
9 * Based on the MPC8349EMDS config.
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Reinhard Arltc2e49f72009-07-25 06:19:12 +020012 */
13
14/*
15 * vme8349 board configuration file.
16 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
Kim Phillipsfdfaa292015-03-17 12:00:45 -050021#define CONFIG_DISPLAY_BOARDINFO
22
Reinhard Arltc2e49f72009-07-25 06:19:12 +020023/*
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010024 * Top level Makefile configuration choices
25 */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026#ifdef CONFIG_CADDY2
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010027#define VME_CADDY2
28#endif
29
30/*
Reinhard Arltc2e49f72009-07-25 06:19:12 +020031 * High Level Configuration Options
32 */
33#define CONFIG_E300 1 /* E300 Family */
Reinhard Arltc2e49f72009-07-25 06:19:12 +020034#define CONFIG_MPC834x 1 /* MPC834x family */
35#define CONFIG_MPC8349 1 /* MPC8349 specific */
36#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
37
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038#define CONFIG_SYS_TEXT_BASE 0xFFF00000
39
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010040#define CONFIG_MISC_INIT_R
41
Reinhard Arltc2e49f72009-07-25 06:19:12 +020042#define CONFIG_PCI
43/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
44#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
45
Wolfgang Denk2ae18242010-10-06 09:05:45 +020046#define CONFIG_PCI_66M
47#ifdef CONFIG_PCI_66M
Reinhard Arltc2e49f72009-07-25 06:19:12 +020048#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
49#else
50#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
51#endif
52
53#ifndef CONFIG_SYS_CLK_FREQ
Wolfgang Denk2ae18242010-10-06 09:05:45 +020054#ifdef CONFIG_PCI_66M
Reinhard Arltc2e49f72009-07-25 06:19:12 +020055#define CONFIG_SYS_CLK_FREQ 66000000
56#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
57#else
58#define CONFIG_SYS_CLK_FREQ 33000000
59#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
60#endif
61#endif
62
63#define CONFIG_SYS_IMMR 0xE0000000
64
65#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
66#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
67#define CONFIG_SYS_MEMTEST_END 0x00100000
68
69/*
70 * DDR Setup
71 */
72#define CONFIG_DDR_ECC /* only for ECC DDR module */
73#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010074#define CONFIG_SPD_EEPROM
75#define SPD_EEPROM_ADDRESS 0x54
76#define CONFIG_SYS_READ_SPD vme8349_read_spd
Reinhard Arltc2e49f72009-07-25 06:19:12 +020077#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
78
79/*
80 * 32-bit data path mode.
81 *
82 * Please note that using this mode for devices with the real density of 64-bit
83 * effectively reduces the amount of available memory due to the effect of
84 * wrapping around while translating address to row/columns, for example in the
85 * 256MB module the upper 128MB get aliased with contents of the lower
86 * 128MB); normally this define should be used for devices with real 32-bit
87 * data path.
88 */
89#undef CONFIG_DDR_32BIT
90
91#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
92#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
93#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershberger2fef4022011-10-11 23:57:29 -050094#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
95 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
Reinhard Arltc2e49f72009-07-25 06:19:12 +020096#define CONFIG_DDR_2T_TIMING
Joe Hershberger2fef4022011-10-11 23:57:29 -050097#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
98 | DDRCDR_ODT \
99 | DDRCDR_Q_DRN)
100 /* 0x80080001 */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200101
102/*
103 * FLASH on the Local Bus
104 */
105#define CONFIG_SYS_FLASH_CFI
106#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100107#ifdef VME_CADDY2
108#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
109#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200110#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500111 BR_PS_16 | /* 16bit */ \
112 BR_MS_GPCM | /* MSEL = GPCM */ \
113 BR_V) /* valid */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200114
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500115#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
116 | OR_GPCM_XAM \
117 | OR_GPCM_CSNT \
118 | OR_GPCM_ACS_DIV2 \
119 | OR_GPCM_XACS \
120 | OR_GPCM_SCY_15 \
121 | OR_GPCM_TRLX_SET \
122 | OR_GPCM_EHTR_SET \
123 | OR_GPCM_EAD)
124 /* 0xffc06ff7 */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200125#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500126#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100127#else
128#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
129#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
130#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500131 BR_PS_16 | /* 16bit */ \
132 BR_MS_GPCM | /* MSEL = GPCM */ \
133 BR_V) /* valid */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100134
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500135#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
136 | OR_GPCM_XAM \
137 | OR_GPCM_CSNT \
138 | OR_GPCM_ACS_DIV2 \
139 | OR_GPCM_XACS \
140 | OR_GPCM_SCY_15 \
141 | OR_GPCM_TRLX_SET \
142 | OR_GPCM_EHTR_SET \
143 | OR_GPCM_EAD)
144 /* 0xf8006ff7 */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100145#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500146#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100147#endif
148/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200149
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500150#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
151#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
152 | BR_PS_32 \
153 | BR_MS_GPCM \
154 | BR_V)
155 /* 0xF0001801 */
156#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
157 | OR_GPCM_SETA)
158 /* 0xfffc0208 */
159#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
160#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200161
162#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
163#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
164
165#undef CONFIG_SYS_FLASH_CHECKSUM
166#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
167#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
168
Joe Hershbergerc7357a22011-10-11 23:57:27 -0500169#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200170
171#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
172#define CONFIG_SYS_RAMBOOT
173#else
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100174#undef CONFIG_SYS_RAMBOOT
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200175#endif
176
177#define CONFIG_SYS_INIT_RAM_LOCK 1
178#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200179#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200180
Wolfgang Denk553f0982010-10-26 13:32:32 +0200181#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200182 GENERATED_GBL_DATA_SIZE)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200183#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
184
185#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500186#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200187
188/*
189 * Local Bus LCRR and LBCR regs
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100190 * LCRR: no DLL bypass, Clock divider is 4
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200191 * External Local Bus rate is
192 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
193 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500194#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200195#define CONFIG_SYS_LBC_LBCR 0x00000000
196
197#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
198
199/*
200 * Serial Port
201 */
202#define CONFIG_CONS_INDEX 1
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200203#define CONFIG_SYS_NS16550_SERIAL
204#define CONFIG_SYS_NS16550_REG_SIZE 1
205#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
206
207#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershbergerc7357a22011-10-11 23:57:27 -0500208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200209
210#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
211#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
212
213#define CONFIG_CMDLINE_EDITING /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500214#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200215/* Use the HUSH parser */
216#define CONFIG_SYS_HUSH_PARSER
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200217
218/* pass open firmware flat tree */
219#define CONFIG_OF_LIBFDT
220#define CONFIG_OF_BOARD_SETUP
221#define CONFIG_OF_STDOUT_VIA_ALIAS
222
223/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200224#define CONFIG_SYS_I2C
225#define CONFIG_SYS_I2C_FSL
226#define CONFIG_SYS_FSL_I2C_SPEED 400000
227#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
228#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
229#define CONFIG_SYS_FSL_I2C2_SPEED 400000
230#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
231#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
232#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Paul Gortmakerefaf6f12009-10-02 18:54:20 -0400233/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200234
235#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
236
237/* TSEC */
238#define CONFIG_SYS_TSEC1_OFFSET 0x24000
239#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
240#define CONFIG_SYS_TSEC2_OFFSET 0x25000
241#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
242
243/*
244 * General PCI
245 * Addresses are mapped 1-1.
246 */
247#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
248#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
249#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
250#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
251#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
252#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
253#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
254#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
255#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
256
257#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
258#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
259#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
260#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
261#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
262#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
263#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
264#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
265#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
266
267#if defined(CONFIG_PCI)
268
269#define PCI_64BIT
270#define PCI_ONE_PCI1
271#if defined(PCI_64BIT)
272#undef PCI_ALL_PCI1
273#undef PCI_TWO_PCI1
274#undef PCI_ONE_PCI1
275#endif
276
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100277#ifndef VME_CADDY2
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100278#endif
279#define CONFIG_PCI_PNP /* do pci plug-and-play */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200280
281#undef CONFIG_EEPRO100
282#undef CONFIG_TULIP
283
284#if !defined(CONFIG_PCI_PNP)
285 #define PCI_ENET0_IOADDR 0xFIXME
286 #define PCI_ENET0_MEMADDR 0xFIXME
287 #define PCI_IDSEL_NUMBER 0xFIXME
288#endif
289
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100290#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
291#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
292
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200293#endif /* CONFIG_PCI */
294
295/*
296 * TSEC configuration
297 */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100298#ifdef VME_CADDY2
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100299#else
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200300#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100301#endif
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200302
303#if defined(CONFIG_TSEC_ENET)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200304
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100305#define CONFIG_GMII /* MII PHY management */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200306#define CONFIG_TSEC1
307#define CONFIG_TSEC1_NAME "TSEC0"
308#define CONFIG_TSEC2
309#define CONFIG_TSEC2_NAME "TSEC1"
310#define CONFIG_PHY_M88E1111
311#define TSEC1_PHY_ADDR 0x08
312#define TSEC2_PHY_ADDR 0x10
313#define TSEC1_PHYIDX 0
314#define TSEC2_PHYIDX 0
315#define TSEC1_FLAGS TSEC_GIGABIT
316#define TSEC2_FLAGS TSEC_GIGABIT
317
318/* Options are: TSEC[0-1] */
319#define CONFIG_ETHPRIME "TSEC0"
320
321#endif /* CONFIG_TSEC_ENET */
322
323/*
324 * Environment
325 */
326#ifndef CONFIG_SYS_RAMBOOT
327 #define CONFIG_ENV_IS_IN_FLASH
328 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
329 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
330 #define CONFIG_ENV_SIZE 0x2000
331
332/* Address and size of Redundant Environment Sector */
333#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
334#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
335
336#else
337 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
338 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
339 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
340 #define CONFIG_ENV_SIZE 0x2000
341#endif
342
343#define CONFIG_LOADS_ECHO /* echo on for serial download */
344#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
345
346/*
347 * BOOTP options
348 */
349#define CONFIG_BOOTP_BOOTFILESIZE
350#define CONFIG_BOOTP_BOOTPATH
351#define CONFIG_BOOTP_GATEWAY
352#define CONFIG_BOOTP_HOSTNAME
353
354/*
355 * Command line configuration.
356 */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200357#define CONFIG_CMD_I2C
358#define CONFIG_CMD_MII
359#define CONFIG_CMD_PING
360#define CONFIG_CMD_DATE
361#define CONFIG_SYS_RTC_BUS_NUM 0x01
362#define CONFIG_SYS_I2C_RTC_ADDR 0x32
363#define CONFIG_RTC_RX8025
364#define CONFIG_CMD_TSI148
365
366#if defined(CONFIG_PCI)
367 #define CONFIG_CMD_PCI
368#endif
369
370#if defined(CONFIG_SYS_RAMBOOT)
371 #undef CONFIG_CMD_ENV
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200372#endif
373
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200374/* Pass Ethernet MAC to VxWorks */
375#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
376
377#undef CONFIG_WATCHDOG /* watchdog disabled */
378
379/*
380 * Miscellaneous configurable options
381 */
382#define CONFIG_SYS_LONGHELP /* undef to save memory */
383#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200384
385#if defined(CONFIG_CMD_KGDB)
386 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
387#else
388 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
389#endif
390
391#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
392#define CONFIG_SYS_MAXARGS 16 /* max num of command args */
393#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200394
395/*
396 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700397 * have to be in the first 256 MB of memory, since this is
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200398 * the maximum mapped by the Linux kernel during initialization.
399 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700400#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200401
402#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
403
404#define CONFIG_SYS_HRCW_LOW (\
405 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
406 HRCWL_DDR_TO_SCB_CLK_1X1 |\
407 HRCWL_CSB_TO_CLKIN |\
408 HRCWL_VCO_1X2 |\
409 HRCWL_CORE_TO_CSB_2X1)
410
411#if defined(PCI_64BIT)
412#define CONFIG_SYS_HRCW_HIGH (\
413 HRCWH_PCI_HOST |\
414 HRCWH_64_BIT_PCI |\
415 HRCWH_PCI1_ARBITER_ENABLE |\
416 HRCWH_PCI2_ARBITER_DISABLE |\
417 HRCWH_CORE_ENABLE |\
418 HRCWH_FROM_0X00000100 |\
419 HRCWH_BOOTSEQ_DISABLE |\
420 HRCWH_SW_WATCHDOG_DISABLE |\
421 HRCWH_ROM_LOC_LOCAL_16BIT |\
422 HRCWH_TSEC1M_IN_GMII |\
423 HRCWH_TSEC2M_IN_GMII)
424#else
425#define CONFIG_SYS_HRCW_HIGH (\
426 HRCWH_PCI_HOST |\
427 HRCWH_32_BIT_PCI |\
428 HRCWH_PCI1_ARBITER_ENABLE |\
429 HRCWH_PCI2_ARBITER_ENABLE |\
430 HRCWH_CORE_ENABLE |\
431 HRCWH_FROM_0X00000100 |\
432 HRCWH_BOOTSEQ_DISABLE |\
433 HRCWH_SW_WATCHDOG_DISABLE |\
434 HRCWH_ROM_LOC_LOCAL_16BIT |\
435 HRCWH_TSEC1M_IN_GMII |\
436 HRCWH_TSEC2M_IN_GMII)
437#endif
438
439/* System IO Config */
440#define CONFIG_SYS_SICRH 0
441#define CONFIG_SYS_SICRL SICRL_LDP_A
442
443#define CONFIG_SYS_HID0_INIT 0x000000000
Kim Phillips1a2e2032010-04-20 19:37:54 -0500444#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
445 HID0_ENABLE_INSTRUCTION_CACHE)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200446
447#define CONFIG_SYS_HID2 HID2_HBE
448
449#define CONFIG_SYS_GPIO1_PRELIM
450#define CONFIG_SYS_GPIO1_DIR 0x00100000
451#define CONFIG_SYS_GPIO1_DAT 0x00100000
452
453#define CONFIG_SYS_GPIO2_PRELIM
454#define CONFIG_SYS_GPIO2_DIR 0x78900000
455#define CONFIG_SYS_GPIO2_DAT 0x70100000
456
457#define CONFIG_HIGH_BATS /* High BATs supported */
458
459/* DDR @ 0x00000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500460#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200461 BATL_MEMCOHERENCE)
462#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
463 BATU_VS | BATU_VP)
464
465/* PCI @ 0x80000000 */
466#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000467#define CONFIG_PCI_INDIRECT_BRIDGE
Joe Hershberger72cd4082011-10-11 23:57:28 -0500468#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200469 BATL_MEMCOHERENCE)
470#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
471 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -0500472#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200473 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
474#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
475 BATU_VS | BATU_VP)
476#else
477#define CONFIG_SYS_IBAT1L (0)
478#define CONFIG_SYS_IBAT1U (0)
479#define CONFIG_SYS_IBAT2L (0)
480#define CONFIG_SYS_IBAT2U (0)
481#endif
482
483#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger72cd4082011-10-11 23:57:28 -0500484#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200485 BATL_MEMCOHERENCE)
486#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
487 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -0500488#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200489 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
490#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
491 BATU_VS | BATU_VP)
492#else
493#define CONFIG_SYS_IBAT3L (0)
494#define CONFIG_SYS_IBAT3U (0)
495#define CONFIG_SYS_IBAT4L (0)
496#define CONFIG_SYS_IBAT4U (0)
497#endif
498
499/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500500#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200501 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
502#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
503 BATU_VS | BATU_VP)
504
Joe Hershberger72cd4082011-10-11 23:57:28 -0500505#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200506#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
507
508#if (CONFIG_SYS_DDR_SIZE == 512)
509#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500510 BATL_PP_RW | BATL_MEMCOHERENCE)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200511#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
512 BATU_BL_256M | BATU_VS | BATU_VP)
513#else
514#define CONFIG_SYS_IBAT7L (0)
515#define CONFIG_SYS_IBAT7U (0)
516#endif
517
518#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
519#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
520#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
521#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
522#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
523#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
524#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
525#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
526#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
527#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
528#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
529#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
530#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
531#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
532#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
533#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
534
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200535#if defined(CONFIG_CMD_KGDB)
536#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200537#endif
538
539/*
540 * Environment Configuration
541 */
542#define CONFIG_ENV_OVERWRITE
543
544#if defined(CONFIG_TSEC_ENET)
545#define CONFIG_HAS_ETH0
546#define CONFIG_HAS_ETH1
547#endif
548
549#define CONFIG_HOSTNAME VME8349
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000550#define CONFIG_ROOTPATH "/tftpboot/rootfs"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000551#define CONFIG_BOOTFILE "uImage"
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200552
Kim Phillips79f516b2009-08-21 16:34:38 -0500553#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200554
555#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
556#undef CONFIG_BOOTARGS /* boot command will set bootargs */
557
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100558#define CONFIG_BAUDRATE 9600
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200559
560#define CONFIG_EXTRA_ENV_SETTINGS \
561 "netdev=eth0\0" \
562 "hostname=vme8349\0" \
563 "nfsargs=setenv bootargs root=/dev/nfs rw " \
564 "nfsroot=${serverip}:${rootpath}\0" \
565 "ramargs=setenv bootargs root=/dev/ram rw\0" \
566 "addip=setenv bootargs ${bootargs} " \
567 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
568 ":${hostname}:${netdev}:off panic=1\0" \
569 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
570 "flash_nfs=run nfsargs addip addtty;" \
571 "bootm ${kernel_addr}\0" \
572 "flash_self=run ramargs addip addtty;" \
573 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
574 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
575 "bootm\0" \
576 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
577 "update=protect off fff00000 fff3ffff; " \
578 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
579 "upd=run load update\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500580 "fdtaddr=780000\0" \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200581 "fdtfile=vme8349.dtb\0" \
582 ""
583
Joe Hershbergerc7357a22011-10-11 23:57:27 -0500584#define CONFIG_NFSBOOTCOMMAND \
585 "setenv bootargs root=/dev/nfs rw " \
586 "nfsroot=$serverip:$rootpath " \
587 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
588 "$netdev:off " \
589 "console=$consoledev,$baudrate $othbootargs;" \
590 "tftp $loadaddr $bootfile;" \
591 "tftp $fdtaddr $fdtfile;" \
592 "bootm $loadaddr - $fdtaddr"
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200593
594#define CONFIG_RAMBOOTCOMMAND \
Joe Hershbergerc7357a22011-10-11 23:57:27 -0500595 "setenv bootargs root=/dev/ram rw " \
596 "console=$consoledev,$baudrate $othbootargs;" \
597 "tftp $ramdiskaddr $ramdiskfile;" \
598 "tftp $loadaddr $bootfile;" \
599 "tftp $fdtaddr $fdtfile;" \
600 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200601
602#define CONFIG_BOOTCOMMAND "run flash_self"
603
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100604#ifndef __ASSEMBLY__
605int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
606 unsigned char *buffer, int len);
607#endif
608
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200609#endif /* __CONFIG_H */