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Stefan Roese4745aca2007-02-20 10:57:08 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/************************************************************************
27 * katmai.h - configuration for AMCC Katmai (440SPe)
28 ***********************************************************************/
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020032
Stefan Roese4745aca2007-02-20 10:57:08 +010033/*-----------------------------------------------------------------------
34 * High Level Configuration Options
35 *----------------------------------------------------------------------*/
36#define CONFIG_KATMAI 1 /* Board is Katmai */
37#define CONFIG_4xx 1 /* ... PPC4xx family */
38#define CONFIG_440 1 /* ... PPC440 family */
39#define CONFIG_440SPE 1 /* Specifc SPe support */
Stefan Roese2a72e9e2010-04-09 14:03:59 +020040#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
Stefan Roese4745aca2007-02-20 10:57:08 +010041#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
Stefan Roese490f2042008-06-06 15:55:03 +020043
Wolfgang Denk2ae18242010-10-06 09:05:45 +020044#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
45
Stefan Roese490f2042008-06-06 15:55:03 +020046/*
Stefan Roese5d812b82008-07-09 17:33:57 +020047 * Enable this board for more than 2GB of SDRAM
48 */
49#define CONFIG_PHYS_64BIT
50#define CONFIG_VERY_BIG_RAM
Stefan Roese5d812b82008-07-09 17:33:57 +020051
52/*
Stefan Roese490f2042008-06-06 15:55:03 +020053 * Include common defines/options for all AMCC eval boards
54 */
55#define CONFIG_HOSTNAME katmai
56#include "amcc-common.h"
Stefan Roese4745aca2007-02-20 10:57:08 +010057
58#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Stefan Roese4745aca2007-02-20 10:57:08 +010059#undef CONFIG_SHOW_BOOT_PROGRESS
60
61/*-----------------------------------------------------------------------
62 * Base addresses -- Note these are effective addresses where the
63 * actual resources get mapped (not physical addresses)
64 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
Stefan Roese4745aca2007-02-20 10:57:08 +010067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
69#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
70#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
Stefan Roese4745aca2007-02-20 10:57:08 +010071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
73#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
74#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
Stefan Roese4745aca2007-02-20 10:57:08 +010075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
77#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
78#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
79#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
80#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
81#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
Stefan Roese4745aca2007-02-20 10:57:08 +010082
Stefan Roese97923772007-10-05 09:18:23 +020083/* base address of inbound PCIe window */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
Stefan Roese97923772007-10-05 09:18:23 +020085
Stefan Roese4745aca2007-02-20 10:57:08 +010086/* System RAM mapped to PCI space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
88#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
Stefan Roese4745aca2007-02-20 10:57:08 +010089#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
90
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
Stefan Roese4745aca2007-02-20 10:57:08 +010092
93/*-----------------------------------------------------------------------
94 * Initial RAM & stack pointer (placed in internal SRAM)
95 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_TEMP_STACK_OCM 1
97#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
98#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +020099#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Stefan Roese4745aca2007-02-20 10:57:08 +0100100
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200101#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +0200102#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Stefan Roese4745aca2007-02-20 10:57:08 +0100103
104/*-----------------------------------------------------------------------
105 * Serial Port
106 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +0200107#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Stefan Roese4745aca2007-02-20 10:57:08 +0100109
110/*-----------------------------------------------------------------------
111 * DDR SDRAM
112 *----------------------------------------------------------------------*/
113#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100114#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
Stefan Roese2721a682007-03-08 10:07:18 +0100115#define CONFIG_DDR_ECC 1 /* with ECC support */
Stefan Roese845c6c92008-01-05 09:12:41 +0100116#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
Stefan Roese4745aca2007-02-20 10:57:08 +0100117#undef CONFIG_STRESS
Stefan Roese4745aca2007-02-20 10:57:08 +0100118
119/*-----------------------------------------------------------------------
120 * I2C
121 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
Stefan Roese4745aca2007-02-20 10:57:08 +0100123
124#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
Stefan Roese4745aca2007-02-20 10:57:08 +0100126
127#define IIC0_BOOTPROM_ADDR 0x50
128#define IIC0_ALT_BOOTPROM_ADDR 0x54
129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_I2C_MULTI_EEPROMS
131#define CONFIG_SYS_I2C_EEPROM_ADDR (0x50)
132#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
133#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
134#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese4745aca2007-02-20 10:57:08 +0100135
Stefan Roeseefe12bc2009-11-09 14:15:42 +0100136/* I2C bootstrap EEPROM */
137#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
138#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
139#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
140
Stefan Roese4745aca2007-02-20 10:57:08 +0100141/* I2C RTC */
142#define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
144#define CONFIG_SYS_I2C_RTC_ADDR 0x68
145#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
Stefan Roese4745aca2007-02-20 10:57:08 +0100146
147/* I2C DTT */
148#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
Stefan Roese4745aca2007-02-20 10:57:08 +0100150/*
151 * standard dtt sensor configuration - bottom bit will determine local or
152 * remote sensor of the ADM1021, the rest determines index into
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153 * CONFIG_SYS_DTT_ADM1021 array below.
Stefan Roese4745aca2007-02-20 10:57:08 +0100154 */
155#define CONFIG_DTT_SENSORS { 0, 1 }
156
157/*
158 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
159 * there will be one entry in this array for each two (dummy) sensors in
160 * CONFIG_DTT_SENSORS.
161 *
162 * For Katmai board:
163 * - only one ADM1021
164 * - i2c addr 0x18
165 * - conversion rate 0x02 = 0.25 conversions/second
166 * - ALERT ouput disabled
167 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
168 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
Stefan Roese4745aca2007-02-20 10:57:08 +0100171
172/*-----------------------------------------------------------------------
173 * Environment
174 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200175#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
Stefan Roese4745aca2007-02-20 10:57:08 +0100176
Stefan Roese490f2042008-06-06 15:55:03 +0200177/*
178 * Default environment variables
179 */
Stefan Roese4745aca2007-02-20 10:57:08 +0100180#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200181 CONFIG_AMCC_DEF_ENV \
182 CONFIG_AMCC_DEF_ENV_POWERPC \
Stefan Roese490f2042008-06-06 15:55:03 +0200183 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roesefc21cd52010-08-03 10:29:50 +0200184 "kernel_addr=ff000000\0" \
185 "fdt_addr=ff1e0000\0" \
186 "ramdisk_addr=ff200000\0" \
Grzegorz Bernacki6efc1fc2007-09-07 18:35:37 +0200187 "pciconfighost=1\0" \
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200188 "pcie_mode=RP:RP:RP\0" \
Stefan Roese4745aca2007-02-20 10:57:08 +0100189 ""
Stefan Roese4745aca2007-02-20 10:57:08 +0100190
Jon Loeligerbc234c12007-07-04 22:32:51 -0500191/*
Stefan Roese490f2042008-06-06 15:55:03 +0200192 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger079a1362007-07-10 10:12:10 -0500193 */
Stefan Roeseefe12bc2009-11-09 14:15:42 +0100194#define CONFIG_CMD_CHIP_CONFIG
Jon Loeligerbc234c12007-07-04 22:32:51 -0500195#define CONFIG_CMD_DATE
Stefan Roesee3722862010-07-22 19:06:14 +0200196#define CONFIG_CMD_ECCTEST
Stefan Roeseefe12bc2009-11-09 14:15:42 +0100197#define CONFIG_CMD_EXT2
198#define CONFIG_CMD_FAT
Jon Loeligerbc234c12007-07-04 22:32:51 -0500199#define CONFIG_CMD_PCI
Jon Loeligerbc234c12007-07-04 22:32:51 -0500200#define CONFIG_CMD_SDRAM
Stefan Roeseafe9fa52007-10-22 16:24:44 +0200201#define CONFIG_CMD_SNTP
Stefan Roese4745aca2007-02-20 10:57:08 +0100202
203#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
Stefan Roese4745aca2007-02-20 10:57:08 +0100204#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
205#define CONFIG_HAS_ETH0
206#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
207#define CONFIG_PHY_RESET_DELAY 1000
208#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
209#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Stefan Roese4745aca2007-02-20 10:57:08 +0100210
211/*-----------------------------------------------------------------------
212 * FLASH related
213 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200215#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
217#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Stefan Roese4745aca2007-02-20 10:57:08 +0100218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
220#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
221#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Stefan Roese4745aca2007-02-20 10:57:08 +0100222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#undef CONFIG_SYS_FLASH_CHECKSUM
224#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
225#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese4745aca2007-02-20 10:57:08 +0100226
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200227#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200229#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese4745aca2007-02-20 10:57:08 +0100230
231/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200232#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
233#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese4745aca2007-02-20 10:57:08 +0100234
235/*-----------------------------------------------------------------------
236 * PCI stuff
237 *-----------------------------------------------------------------------
238 */
239/* General PCI */
240#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000241#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese4745aca2007-02-20 10:57:08 +0100242#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
243#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
Grzegorz Bernacki6efc1fc2007-09-07 18:35:37 +0200244#define CONFIG_PCI_CONFIG_HOST_BRIDGE
Stefan Roese4745aca2007-02-20 10:57:08 +0100245
246/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
248#undef CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese4745aca2007-02-20 10:57:08 +0100249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
251#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
252/* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */
Stefan Roese4745aca2007-02-20 10:57:08 +0100253
254/*
255 * NETWORK Support (PCI):
256 */
257/* Support for Intel 82557/82559/82559ER chips. */
258#define CONFIG_EEPRO100
259
260/*-----------------------------------------------------------------------
261 * Xilinx System ACE support
262 *----------------------------------------------------------------------*/
263#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
265#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
Stefan Roese4745aca2007-02-20 10:57:08 +0100266#define CONFIG_DOS_PARTITION 1
267
268/*-----------------------------------------------------------------------
269 * External Bus Controller (EBC) Setup
270 *----------------------------------------------------------------------*/
271
272/* Memory Bank 0 (Flash) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100274 EBC_BXAP_TWT_ENCODE(7) | \
275 EBC_BXAP_BCE_DISABLE | \
276 EBC_BXAP_BCT_2TRANS | \
277 EBC_BXAP_CSN_ENCODE(0) | \
278 EBC_BXAP_OEN_ENCODE(0) | \
279 EBC_BXAP_WBN_ENCODE(0) | \
280 EBC_BXAP_WBF_ENCODE(0) | \
281 EBC_BXAP_TH_ENCODE(0) | \
282 EBC_BXAP_RE_DISABLED | \
283 EBC_BXAP_SOR_DELAYED | \
284 EBC_BXAP_BEM_WRITEONLY | \
285 EBC_BXAP_PEN_DISABLED)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100287 EBC_BXCR_BS_16MB | \
288 EBC_BXCR_BU_RW | \
289 EBC_BXCR_BW_16BIT)
290
291/* Memory Bank 1 (Xilinx System ACE controller) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
Stefan Roesed2168622007-04-19 09:53:52 +0200293 EBC_BXAP_TWT_ENCODE(4) | \
294 EBC_BXAP_BCE_DISABLE | \
295 EBC_BXAP_BCT_2TRANS | \
296 EBC_BXAP_CSN_ENCODE(0) | \
297 EBC_BXAP_OEN_ENCODE(0) | \
298 EBC_BXAP_WBN_ENCODE(0) | \
299 EBC_BXAP_WBF_ENCODE(0) | \
300 EBC_BXAP_TH_ENCODE(0) | \
301 EBC_BXAP_RE_DISABLED | \
302 EBC_BXAP_SOR_NONDELAYED | \
303 EBC_BXAP_BEM_WRITEONLY | \
304 EBC_BXAP_PEN_DISABLED)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE) | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100306 EBC_BXCR_BS_1MB | \
307 EBC_BXCR_BU_RW | \
308 EBC_BXCR_BW_16BIT)
309
310/*-------------------------------------------------------------------------
311 * Initialize EBC CONFIG -
312 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
313 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
314 *-------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100316 EBC_CFG_PTD_ENABLE | \
317 EBC_CFG_RTC_16PERCLK | \
318 EBC_CFG_ATC_PREVIOUS | \
319 EBC_CFG_DTC_PREVIOUS | \
320 EBC_CFG_CTC_PREVIOUS | \
321 EBC_CFG_OEO_PREVIOUS | \
322 EBC_CFG_EMC_DEFAULT | \
323 EBC_CFG_PME_DISABLE | \
324 EBC_CFG_PR_16)
325
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100326/*-----------------------------------------------------------------------
327 * GPIO Setup
328 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
330#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
331#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
332#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
335 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
336 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
337 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
338#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
339#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
340#define CONFIG_SYS_GPIO_ODR 0
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100341
Stefan Roese4745aca2007-02-20 10:57:08 +0100342#endif /* __CONFIG_H */