blob: e96a7427e5864c64280e0c3dc2eb38f0645ef484 [file] [log] [blame]
Harald Krapfenbauer2aeda2d2010-01-13 09:04:53 -05001/*
2 * U-boot - Configuration file for Bluetechnix TCM-BF518 board
3 */
4
5#ifndef __CONFIG_TCM_BF518_H__
6#define __CONFIG_TCM_BF518_H__
7
8#include <asm/config-pre.h>
9
10
11/*
12 * Processor Settings
13 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf518-0.0
Harald Krapfenbauer2aeda2d2010-01-13 09:04:53 -050015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 16
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
41
42/*
43 * Memory Settings
44 */
45/* This board has a 32meg MT48H16M16 */
46#define CONFIG_MEM_ADD_WDTH 9
47#define CONFIG_MEM_SIZE 32
48
49#define CONFIG_EBIU_SDRRC_VAL 0x3f8
50#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
51
52#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
53#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
54#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
55
56#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
57#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
58
59
60/*
61 * Network Settings
62 */
63#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
64#define ADI_CMDS_NETWORK 1
65#define CONFIG_BFIN_MAC
66#define CONFIG_NETCONSOLE 1
Harald Krapfenbauer2aeda2d2010-01-13 09:04:53 -050067#endif
68#define CONFIG_HOSTNAME tcm-bf518
69/* Uncomment next line to use fixed MAC address */
70/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
Masahiro Yamadac42f56d2014-04-18 19:09:49 +090071#define CONFIG_LIB_RAND
Harald Krapfenbauer2aeda2d2010-01-13 09:04:53 -050072
73/*
74 * Flash Settings
75 */
76#define CONFIG_FLASH_CFI_DRIVER
77#define CONFIG_SYS_FLASH_BASE 0x20000000
78#define CONFIG_SYS_FLASH_CFI
79#define CONFIG_SYS_FLASH_PROTECTION
80#define CONFIG_SYS_MAX_FLASH_BANKS 1
81#define CONFIG_SYS_MAX_FLASH_SECT 19
82
83
84/*
85 * SPI Settings
86 */
87#define CONFIG_BFIN_SPI
88#define CONFIG_ENV_SPI_MAX_HZ 30000000
89#define CONFIG_SF_DEFAULT_SPEED 30000000
90
91
92/*
93 * Env Storage Settings
94 */
95#define CONFIG_ENV_IS_IN_FLASH
96#define CONFIG_ENV_OFFSET 0x8000
97#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
98#define CONFIG_ENV_SIZE 0x2000
99#define CONFIG_ENV_SECT_SIZE 0x8000
100#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
101
102
103/*
104 * I2C Settings
105 */
Scott Jiangc4697032014-11-13 15:30:55 +0800106#define CONFIG_SYS_I2C
Scott Jiangfea9b692014-11-13 15:30:53 +0800107#define CONFIG_SYS_I2C_ADI
Harald Krapfenbauer2aeda2d2010-01-13 09:04:53 -0500108
109
110/*
111 * Misc Settings
112 */
113#define CONFIG_BAUDRATE 115200
114#define CONFIG_MISC_INIT_R
115#define CONFIG_RTC_BFIN
116#define CONFIG_UART_CONSOLE 0
117#define CONFIG_BOOTCOMMAND "run flashboot"
118#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
Harald Krapfenbauer2aeda2d2010-01-13 09:04:53 -0500119
120/*
121 * Pull in common ADI header for remaining command/environment setup
122 */
123#include <configs/bfin_adi_common.h>
124
125#endif