Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 1 | /* |
| 2 | * ti_armv7_common.h |
| 3 | * |
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | * |
| 8 | * The various ARMv7 SoCs from TI all share a number of IP blocks when |
| 9 | * implementing a given feature. Rather than define these in every |
| 10 | * board or even SoC common file, we define a common file to be re-used |
| 11 | * in all cases. While technically true that some of these details are |
| 12 | * configurable at the board design, they are common throughout SoC |
| 13 | * reference platforms as well as custom designs and become de facto |
| 14 | * standards. |
| 15 | */ |
| 16 | |
| 17 | #ifndef __CONFIG_TI_ARMV7_COMMON_H__ |
| 18 | #define __CONFIG_TI_ARMV7_COMMON_H__ |
| 19 | |
| 20 | /* Common define for many platforms. */ |
| 21 | #define CONFIG_OMAP |
| 22 | #define CONFIG_OMAP_COMMON |
Tom Rini | 0dd5461 | 2014-04-03 15:17:14 -0400 | [diff] [blame] | 23 | #define CONFIG_SYS_GENERIC_BOARD |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 24 | |
| 25 | /* |
| 26 | * We typically do not contain NOR flash. In the cases where we do, we |
| 27 | * undefine this later. |
| 28 | */ |
| 29 | #define CONFIG_SYS_NO_FLASH |
| 30 | |
| 31 | /* Support both device trees and ATAGs. */ |
| 32 | #define CONFIG_OF_LIBFDT |
| 33 | #define CONFIG_CMDLINE_TAG |
| 34 | #define CONFIG_SETUP_MEMORY_TAGS |
| 35 | #define CONFIG_INITRD_TAG |
| 36 | |
| 37 | /* |
| 38 | * Our DDR memory always starts at 0x80000000 and U-Boot shall have |
| 39 | * relocated itself to higher in memory by the time this value is used. |
Tom Rini | fb3ad9b | 2014-03-28 15:03:29 -0400 | [diff] [blame] | 40 | * However, set this to a 32MB offset to allow for easier Linux kernel |
| 41 | * booting as the default is often used as the kernel load address. |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 42 | */ |
Tom Rini | fb3ad9b | 2014-03-28 15:03:29 -0400 | [diff] [blame] | 43 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 |
| 44 | |
| 45 | /* |
| 46 | * We setup defaults based on constraints from the Linux kernel, which should |
| 47 | * also be safe elsewhere. We have the default load at 32MB into DDR (for |
| 48 | * the kernel), FDT above 128MB (the maximum location for the end of the |
| 49 | * kernel), and the ramdisk 512KB above that (allowing for hopefully never |
| 50 | * seen large trees). We say all of this must be within the first 256MB |
| 51 | * as that will normally be within the kernel lowmem and thus visible via |
| 52 | * bootm_size and we only run on platforms with 256MB or more of memory. |
| 53 | */ |
| 54 | #define DEFAULT_LINUX_BOOT_ENV \ |
| 55 | "loadaddr=0x82000000\0" \ |
| 56 | "kernel_addr_r=0x82000000\0" \ |
| 57 | "fdtaddr=0x88000000\0" \ |
| 58 | "fdt_addr_r=0x88000000\0" \ |
| 59 | "rdaddr=0x88080000\0" \ |
| 60 | "ramdisk_addr_r=0x88080000\0" \ |
| 61 | "bootm_size=0x10000000\0" |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 62 | |
| 63 | /* |
| 64 | * Default to a quick boot delay. |
| 65 | */ |
| 66 | #define CONFIG_BOOTDELAY 1 |
| 67 | |
| 68 | /* |
Enric Balletbò i Serra | c6a7fce | 2013-12-06 21:30:21 +0100 | [diff] [blame] | 69 | * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, |
| 70 | * we say (for simplicity) that we have 1 bank, always, even when |
| 71 | * we have more. We always start at 0x80000000, and we place the |
| 72 | * initial stack pointer in our SRAM. Otherwise, we can define |
| 73 | * CONFIG_NR_DRAM_BANKS before including this file. |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 74 | */ |
Enric Balletbò i Serra | c6a7fce | 2013-12-06 21:30:21 +0100 | [diff] [blame] | 75 | #ifndef CONFIG_NR_DRAM_BANKS |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 76 | #define CONFIG_NR_DRAM_BANKS 1 |
Enric Balletbò i Serra | c6a7fce | 2013-12-06 21:30:21 +0100 | [diff] [blame] | 77 | #endif |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 78 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
| 79 | #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ |
| 80 | GENERATED_GBL_DATA_SIZE) |
| 81 | |
| 82 | /* Timer information. */ |
| 83 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 84 | |
| 85 | /* I2C IP block */ |
| 86 | #define CONFIG_I2C |
Tom Rini | 1dd44e5 | 2013-08-20 08:53:49 -0400 | [diff] [blame] | 87 | #define CONFIG_CMD_I2C |
Heiko Schocher | 6789e84 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 88 | #define CONFIG_SYS_I2C |
| 89 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 |
| 90 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 |
| 91 | #define CONFIG_SYS_I2C_OMAP24XX |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 92 | |
| 93 | /* MMC/SD IP block */ |
| 94 | #define CONFIG_MMC |
| 95 | #define CONFIG_GENERIC_MMC |
| 96 | #define CONFIG_OMAP_HSMMC |
| 97 | #define CONFIG_CMD_MMC |
| 98 | |
| 99 | /* McSPI IP block */ |
| 100 | #define CONFIG_SPI |
| 101 | #define CONFIG_OMAP3_SPI |
Tom Rini | 0fedc4a | 2013-08-09 11:22:19 -0400 | [diff] [blame] | 102 | #define CONFIG_CMD_SPI |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 103 | |
| 104 | /* GPIO block */ |
| 105 | #define CONFIG_OMAP_GPIO |
Tom Rini | a1665ed | 2013-08-09 11:22:20 -0400 | [diff] [blame] | 106 | #define CONFIG_CMD_GPIO |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 107 | |
| 108 | /* |
| 109 | * GPMC NAND block. We support 1 device and the physical address to |
| 110 | * access CS0 at is 0x8000000. |
| 111 | */ |
| 112 | #ifdef CONFIG_NAND |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 113 | #define CONFIG_NAND_OMAP_GPMC |
Tom Rini | df4dbb5 | 2014-04-03 15:17:15 -0400 | [diff] [blame] | 114 | #ifndef CONFIG_SYS_NAND_BASE |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 115 | #define CONFIG_SYS_NAND_BASE 0x8000000 |
Tom Rini | df4dbb5 | 2014-04-03 15:17:15 -0400 | [diff] [blame] | 116 | #endif |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 117 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Tom Rini | 1dd44e5 | 2013-08-20 08:53:49 -0400 | [diff] [blame] | 118 | #define CONFIG_CMD_NAND |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 119 | #endif |
| 120 | |
| 121 | /* |
| 122 | * The following are general good-enough settings for U-Boot. We set a |
| 123 | * large malloc pool as we generally have a lot of DDR, and we opt for |
| 124 | * function over binary size in the main portion of U-Boot as this is |
| 125 | * generally easily constrained later if needed. We enable the config |
| 126 | * options that give us information in the environment about what board |
| 127 | * we are on so we do not need to rely on the command prompt. We set a |
| 128 | * console baudrate of 115200 and use the default baud rate table. |
| 129 | */ |
Simon Glass | 0e1612a | 2014-06-02 22:04:54 -0600 | [diff] [blame] | 130 | #define CONFIG_SYS_MALLOC_LEN (16 << 20) |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 131 | #define CONFIG_SYS_HUSH_PARSER |
Tom Rini | 1dd44e5 | 2013-08-20 08:53:49 -0400 | [diff] [blame] | 132 | #define CONFIG_SYS_PROMPT "U-Boot# " |
| 133 | #define CONFIG_SYS_CONSOLE_INFO_QUIET |
| 134 | #define CONFIG_BAUDRATE 115200 |
| 135 | #define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */ |
| 136 | #define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ |
| 137 | |
| 138 | /* As stated above, the following choices are optional. */ |
| 139 | #define CONFIG_SYS_LONGHELP |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 140 | #define CONFIG_AUTO_COMPLETE |
| 141 | #define CONFIG_CMDLINE_EDITING |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 142 | #define CONFIG_VERSION_VARIABLE |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 143 | |
| 144 | /* We set the max number of command args high to avoid HUSH bugs. */ |
| 145 | #define CONFIG_SYS_MAXARGS 64 |
| 146 | |
| 147 | /* Console I/O Buffer Size */ |
| 148 | #define CONFIG_SYS_CBSIZE 512 |
| 149 | /* Print Buffer Size */ |
| 150 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
| 151 | + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 152 | /* Boot Argument Buffer Size */ |
| 153 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 154 | |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 155 | /* |
| 156 | * When we have SPI, NOR or NAND flash we expect to be making use of |
| 157 | * mtdparts, both for ease of use in U-Boot and for passing information |
| 158 | * on to the Linux kernel. |
| 159 | */ |
| 160 | #if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND) |
| 161 | #define CONFIG_MTD_DEVICE /* Required for mtdparts */ |
| 162 | #define CONFIG_CMD_MTDPARTS |
| 163 | #endif |
| 164 | |
| 165 | /* |
| 166 | * For commands to use, we take the default list and add a few other |
| 167 | * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH |
| 168 | * prior to this include, in order to skip a few commands. When we do |
| 169 | * have flash, if we expect these commands they must be enabled in that |
Tom Rini | 1dd44e5 | 2013-08-20 08:53:49 -0400 | [diff] [blame] | 170 | * config. If desired, a specific list of desired commands can be used |
| 171 | * instead. |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 172 | */ |
| 173 | #include <config_cmd_default.h> |
| 174 | #define CONFIG_CMD_ASKENV |
| 175 | #define CONFIG_CMD_ECHO |
| 176 | #define CONFIG_CMD_BOOTZ |
Guillaume GARDET | 6440b80 | 2014-11-03 14:26:17 +0100 | [diff] [blame] | 177 | #define CONFIG_SUPPORT_RAW_INITRD |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 178 | |
| 179 | /* |
| 180 | * Common filesystems support. When we have removable storage we |
| 181 | * enabled a number of useful commands and support. |
| 182 | */ |
| 183 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) |
| 184 | #define CONFIG_DOS_PARTITION |
| 185 | #define CONFIG_CMD_FAT |
| 186 | #define CONFIG_FAT_WRITE |
| 187 | #define CONFIG_CMD_EXT2 |
| 188 | #define CONFIG_CMD_EXT4 |
| 189 | #define CONFIG_CMD_FS_GENERIC |
| 190 | #endif |
| 191 | |
| 192 | /* |
| 193 | * Our platforms make use of SPL to initalize the hardware (primarily |
| 194 | * memory) enough for full U-Boot to be loaded. We also support Falcon |
| 195 | * Mode so that the Linux kernel can be booted directly from SPL |
| 196 | * instead, if desired. We make use of the general SPL framework found |
| 197 | * under common/spl/. Given our generally common memory map, we set a |
| 198 | * number of related defaults and sizes here. |
| 199 | */ |
Sourav Poddar | 7a5f71b | 2014-05-19 16:53:37 -0400 | [diff] [blame] | 200 | #if !defined(CONFIG_NOR_BOOT) && \ |
| 201 | !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX)) |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 202 | #define CONFIG_SPL_FRAMEWORK |
| 203 | #define CONFIG_SPL_OS_BOOT |
| 204 | |
| 205 | /* |
Tom Rini | 865813e | 2014-07-18 11:51:32 -0400 | [diff] [blame] | 206 | * Place the image at the start of the ROM defined image space (per |
| 207 | * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined |
| 208 | * downloaded image area. We initalize DRAM as soon as we can so that |
| 209 | * we can place stack, malloc and BSS there. We load U-Boot itself into |
| 210 | * memory at 0x80800000 for legacy reasons (to not conflict with older |
| 211 | * SPLs). We have our BSS be placed 2MiB after this, to allow for the |
| 212 | * default Linux kernel address of 0x80008000 to work with most sized |
| 213 | * kernels, in the Falcon Mode case. We have the SPL malloc pool at the |
| 214 | * end of the BSS area. We place our stack at 32MiB after the start of |
| 215 | * DRAM to allow room for all of the above. |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 216 | */ |
Tom Rini | 865813e | 2014-07-18 11:51:32 -0400 | [diff] [blame] | 217 | #define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20)) |
Tom Rini | df4dbb5 | 2014-04-03 15:17:15 -0400 | [diff] [blame] | 218 | #ifndef CONFIG_SYS_TEXT_BASE |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 219 | #define CONFIG_SYS_TEXT_BASE 0x80800000 |
Tom Rini | df4dbb5 | 2014-04-03 15:17:15 -0400 | [diff] [blame] | 220 | #endif |
| 221 | #ifndef CONFIG_SPL_BSS_START_ADDR |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 222 | #define CONFIG_SPL_BSS_START_ADDR 0x80a00000 |
| 223 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ |
Tom Rini | df4dbb5 | 2014-04-03 15:17:15 -0400 | [diff] [blame] | 224 | #endif |
| 225 | #ifndef CONFIG_SYS_SPL_MALLOC_START |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 226 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ |
| 227 | CONFIG_SPL_BSS_MAX_SIZE) |
| 228 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN |
Tom Rini | df4dbb5 | 2014-04-03 15:17:15 -0400 | [diff] [blame] | 229 | #endif |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 230 | |
| 231 | /* RAW SD card / eMMC locations. */ |
| 232 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ |
| 233 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ |
| 234 | |
| 235 | /* FAT sd card locations. */ |
Guillaume GARDET | 205b4f3 | 2014-10-15 17:53:11 +0200 | [diff] [blame] | 236 | #define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 |
| 237 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 238 | |
| 239 | #ifdef CONFIG_SPL_OS_BOOT |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 240 | /* FAT */ |
Guillaume GARDET | 205b4f3 | 2014-10-15 17:53:11 +0200 | [diff] [blame] | 241 | #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" |
| 242 | #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 243 | |
| 244 | /* RAW SD card / eMMC */ |
| 245 | #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ |
| 246 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ |
| 247 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ |
| 248 | |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 249 | /* spl export command */ |
| 250 | #define CONFIG_CMD_SPL |
| 251 | #endif |
| 252 | |
| 253 | #ifdef CONFIG_MMC |
Tom Rini | a7142dd | 2013-08-20 08:53:44 -0400 | [diff] [blame] | 254 | #define CONFIG_SPL_LIBDISK_SUPPORT |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 255 | #define CONFIG_SPL_MMC_SUPPORT |
| 256 | #define CONFIG_SPL_FAT_SUPPORT |
| 257 | #endif |
| 258 | |
Tom Rini | a7142dd | 2013-08-20 08:53:44 -0400 | [diff] [blame] | 259 | /* General parts of the framework, required. */ |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 260 | #define CONFIG_SPL_I2C_SUPPORT |
| 261 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 262 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
| 263 | #define CONFIG_SPL_SERIAL_SUPPORT |
| 264 | #define CONFIG_SPL_GPIO_SUPPORT |
| 265 | #define CONFIG_SPL_BOARD_INIT |
| 266 | |
| 267 | #ifdef CONFIG_NAND |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 268 | #define CONFIG_SPL_NAND_SUPPORT |
| 269 | #define CONFIG_SPL_NAND_BASE |
| 270 | #define CONFIG_SPL_NAND_DRIVERS |
| 271 | #define CONFIG_SPL_NAND_ECC |
Tom Rini | 6dd3b56 | 2014-03-28 12:03:36 -0400 | [diff] [blame] | 272 | #define CONFIG_SPL_MTD_SUPPORT |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 273 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
Tom Rini | 8769455 | 2013-08-09 11:22:17 -0400 | [diff] [blame] | 274 | #endif |
| 275 | #endif /* !CONFIG_NOR_BOOT */ |
| 276 | |
| 277 | #endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ |