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Tom Rixe63e5902009-10-17 12:41:06 -05001/*
2 * (C) Copyright 2006-2009
3 * Texas Instruments Incorporated.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
7 *
8 * Configuration settings for the 3430 TI SDP3430 board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* TODO: REMOVE THE FOLLOWING
33 * Retained the following till size.h is removed in u-boot
34 */
35#include <asm/sizes.h>
36/*
37 * High Level Configuration Options
38 */
Tom Rixe63e5902009-10-17 12:41:06 -050039#define CONFIG_OMAP 1 /* in a TI OMAP core */
40#define CONFIG_OMAP34XX 1 /* which is a 34XX */
Tom Rixe63e5902009-10-17 12:41:06 -050041#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
42
Vaibhav Hiremathcae377b2010-06-07 15:20:34 -040043#define CONFIG_SDRC /* The chip has SDRC controller */
44
Tom Rixe63e5902009-10-17 12:41:06 -050045#include <asm/arch/cpu.h> /* get chip and board defs */
46#include <asm/arch/omap3.h>
47
48/*
49 * NOTE: these #defines presume standard SDP jumper settings.
50 * In particular:
51 * - 26 MHz clock (not 19.2 or 38.4 MHz)
52 * - Boot from 128MB NOR, not NAND or OneNAND
53 *
54 * At this writing, OMAP3 U-Boot support doesn't permit concurrent
55 * support for all the flash types the board supports.
56 */
57#define CONFIG_DISPLAY_CPUINFO 1
58#define CONFIG_DISPLAY_BOARDINFO 1
59
60/* Clock Defines */
61#define V_OSCK 26000000 /* Clock output from T2 */
62#define V_SCLK (V_OSCK >> 1)
63
Tom Rixe63e5902009-10-17 12:41:06 -050064#define CONFIG_MISC_INIT_R
65
66#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
67#define CONFIG_SETUP_MEMORY_TAGS 1
68#define CONFIG_INITRD_TAG 1
69#define CONFIG_REVISION_TAG 1
70
Grant Likely2fa8ca92011-03-28 09:59:07 +000071#define CONFIG_OF_LIBFDT 1
72
Tom Rixe63e5902009-10-17 12:41:06 -050073/*
74 * Size of malloc() pool
75 * Total Size Environment - 256k
76 * Malloc - add 256k
77 */
78#define CONFIG_ENV_SIZE (256 << 10)
79#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
Tom Rixe63e5902009-10-17 12:41:06 -050080
81/*--------------------------------------------------------------------------*/
82
83/*
84 * Hardware drivers
85 */
86
87/*
88 * TWL4030
89 */
90#define CONFIG_TWL4030_POWER 1
91
92/*
93 * serial port - NS16550 compatible
94 */
95#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
96
97#define CONFIG_SYS_NS16550
98#define CONFIG_SYS_NS16550_SERIAL
99#define CONFIG_SYS_NS16550_REG_SIZE (-4)
100#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
101
102/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
103 * swapped with UART2 via jumpering. Downsides of using J8: it doesn't
104 * support UART boot (that's only for UART3); it prevents sharing a Linux
105 * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
106 *
107 * UART boot uses UART3 on J9, and the SDP user's guide says to use
108 * that for console. Downsides of using J9: you can't use IRDA too;
109 * since UART3 isn't in the CORE power domain, it may be a bit less
110 * usable in certain PM-sensitive debug scenarios.
111 */
112#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
113
114#ifdef CONSOLE_J9
115#define CONFIG_CONS_INDEX 3
116#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
117#define CONFIG_SERIAL3 3 /* UART3 */
118#else
119#define CONFIG_CONS_INDEX 1
120#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
121#define CONFIG_SERIAL1 1 /* UART1 */
122#endif
123
124#define CONFIG_ENV_OVERWRITE
125#define CONFIG_BAUDRATE 115200
126#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
127 115200}
128
129/*
130 * I2C for power management setup
131 */
132#define CONFIG_HARD_I2C 1
133#define CONFIG_SYS_I2C_SPEED 100000
134#define CONFIG_SYS_I2C_SLAVE 1
135#define CONFIG_SYS_I2C_BUS 0
136#define CONFIG_SYS_I2C_BUS_SELECT 1
137#define CONFIG_DRIVER_OMAP34XX_I2C 1
138
Tom Rixe63e5902009-10-17 12:41:06 -0500139/* OMITTED: single 1 Gbit MT29F1G NAND flash */
140
141/*
142 * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
143 */
144#define CONFIG_SYS_FLASH_BASE 0x10000000
145#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
146#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
147#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
148#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
149#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
150#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
151#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
152
153#define CONFIG_SYS_FLASH_CFI_WIDTH 2
154#define PHYS_FLASH_SIZE (128 << 20)
155#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
156
Tom Rixe63e5902009-10-17 12:41:06 -0500157/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
158
159#define CONFIG_ENV_IS_IN_FLASH 1
160#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
161#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
162#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
163/*--------------------------------------------------------------------------*/
164
165/* commands to include */
166#include <config_cmd_default.h>
167
168/* Enabled commands */
169#define CONFIG_CMD_DHCP /* DHCP Support */
170#define CONFIG_CMD_EXT2 /* EXT2 Support */
171#define CONFIG_CMD_FAT /* FAT support */
172#define CONFIG_CMD_I2C /* I2C serial bus support */
173#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
174#define CONFIG_CMD_MMC /* MMC support */
175#define CONFIG_CMD_NET
176
177/* Disabled commands */
178#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
179#undef CONFIG_CMD_IMLS /* List all found images */
180
181/*--------------------------------------------------------------------------*/
182/*
183 * MMC boot support
184 */
185
186#if defined(CONFIG_CMD_MMC)
Tom Rini7cc862b2011-09-03 21:52:21 -0400187#define CONFIG_GENERIC_MMC 1
Tom Rixe63e5902009-10-17 12:41:06 -0500188#define CONFIG_MMC 1
Tom Rini7cc862b2011-09-03 21:52:21 -0400189#define CONFIG_OMAP_HSMMC 1
Tom Rixe63e5902009-10-17 12:41:06 -0500190#define CONFIG_DOS_PARTITION 1
191#endif
192
193/*----------------------------------------------------------------------------
194 * SMSC9115 Ethernet from SMSC9118 family
195 *----------------------------------------------------------------------------
196 */
197#if defined(CONFIG_CMD_NET)
198
Nishanth Menona1725992009-10-16 00:06:36 -0500199#define CONFIG_LAN91C96
Tom Rixe63e5902009-10-17 12:41:06 -0500200#define CONFIG_LAN91C96_BASE DEBUG_BASE
201#define CONFIG_LAN91C96_EXT_PHY
202
203#define CONFIG_BOOTP_SEND_HOSTNAME
204/*
205 * BOOTP fields
206 */
207#define CONFIG_BOOTP_SUBNETMASK 0x00000001
208#define CONFIG_BOOTP_GATEWAY 0x00000002
209#define CONFIG_BOOTP_HOSTNAME 0x00000004
210#define CONFIG_BOOTP_BOOTPATH 0x00000010
211#endif /* (CONFIG_CMD_NET) */
212
213/*
214 * Environment setup
215 *
216 * Default boot order: mmc bootscript, MMC uImage, NOR image.
217 * Network booting environment must be configured at site.
218 */
219
220/* allow overwriting serial config and ethaddr */
221#define CONFIG_ENV_OVERWRITE
222
223#define CONFIG_EXTRA_ENV_SETTINGS \
224 "loadaddr=0x82000000\0" \
225 "console=ttyS0,115200n8\0" \
226 "mmcargs=setenv bootargs console=${console} " \
227 "root=/dev/mmcblk0p2 rw " \
228 "rootfstype=ext3 rootwait\0" \
229 "norargs=setenv bootargs console=${console} " \
230 "root=/dev/mtdblock3 rw " \
231 "rootfstype=jffs2\0" \
232 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
233 "bootscript=echo Running bootscript from MMC/SD ...; " \
234 "autoscr ${loadaddr}\0" \
235 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
236 "mmcboot=echo Booting from MMC/SD ...; " \
237 "run mmcargs; " \
238 "bootm ${loadaddr}\0" \
239 "norboot=echo Booting from NOR ...; " \
240 "run norargs; " \
241 "bootm 0x80000\0" \
242
243#define CONFIG_BOOTCOMMAND \
244 "if mmcinit; then " \
245 "if run loadbootscript; then " \
246 "run bootscript; " \
247 "else " \
248 "if run loaduimage; then " \
249 "run mmcboot; " \
250 "else run norboot; " \
251 "fi; " \
252 "fi; " \
253 "else run norboot; fi"
254
255#define CONFIG_AUTO_COMPLETE 1
256
257/*--------------------------------------------------------------------------*/
258
259/*
260 * Miscellaneous configurable options
261 */
Tom Rixe63e5902009-10-17 12:41:06 -0500262
263#define CONFIG_SYS_LONGHELP /* undef to save memory */
264#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Robert P. J. Day1270ec12009-12-12 12:10:33 -0500265#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
Vaibhav Hiremathf62b1252011-09-03 21:24:19 -0400266#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Tom Rixe63e5902009-10-17 12:41:06 -0500267/* Print Buffer Size */
268#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
269 sizeof(CONFIG_SYS_PROMPT) + 16)
270#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
271/* Boot Argument Buffer Size */
272#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
273
274/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
275 * a basic sanity check ONLY
276 * IF you would like to increase coverage, increase the end address
277 * or run the test with custom options
278 */
279#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
280#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
281
282/* Default load address */
283#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
284
285/*--------------------------------------------------------------------------*/
286
287/*
288 * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
289 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
290 */
291#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
292#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
293#define CONFIG_SYS_HZ 1000
294
Dirk Behme5ec789f2010-11-30 11:10:40 -0500295#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
296#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
297#define CONFIG_SYS_INIT_RAM_SIZE 0x800
298#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
299 CONFIG_SYS_INIT_RAM_SIZE - \
300 GENERATED_GBL_DATA_SIZE)
Tom Rixe63e5902009-10-17 12:41:06 -0500301/*
302 * SDRAM Memory Map
303 */
304#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
305#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
306#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
307#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
308
Tom Rixe63e5902009-10-17 12:41:06 -0500309/*--------------------------------------------------------------------------*/
310
311/*
312 * NOR FLASH usage ... default nCS0:
313 * - one 256KB sector for U-Boot
314 * - one 256KB sector for its parameters (not all used)
315 * - eight sectors (2 MB) for kernel
316 * - rest for JFFS2
317 */
318
319/* Monitor at start of flash */
320#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
321#define CONFIG_SYS_MONITOR_LEN (256 << 10)
322
Tom Rixe63e5902009-10-17 12:41:06 -0500323/*
324 * NAND FLASH usage ... default nCS1:
325 * - four 128KB sectors for X-Loader
326 * - four 128KB sectors for U-Boot
327 * - two 128KB sector for its parameters
328 * - 32 sectors (4 MB) for kernel
329 * - rest for filesystem
330 */
331
332/*
333 * OneNAND FLASH usage ... default nCS2:
334 * - four 128KB sectors for X-Loader
335 * - two 128KB sectors for U-Boot
336 * - one 128KB sector for its parameters
337 * - sixteen sectors (2 MB) for kernel
338 * - rest for filesystem
339 */
340
Aneesh V8e408522011-11-21 23:38:59 +0000341#define CONFIG_SYS_CACHELINE_SIZE 64
342
Tom Rixe63e5902009-10-17 12:41:06 -0500343#endif /* __CONFIG_H */