wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 1 | /* |
wdenk | 414eec3 | 2005-04-02 22:37:54 +0000 | [diff] [blame] | 2 | * (C) Copyright 2003-2005 |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * board/config.h - configuration options, board specific |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H |
| 30 | |
| 31 | |
| 32 | /* |
| 33 | * High Level Configuration Options |
| 34 | * (easy to change) |
| 35 | */ |
| 36 | |
| 37 | #undef CONFIG_MPC860 |
| 38 | #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ |
| 39 | #define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */ |
| 40 | #define CONFIG_RMU 1 |
| 41 | |
| 42 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
| 43 | #undef CONFIG_8xx_CONS_SMC2 |
| 44 | #undef CONFIG_8xx_CONS_NONE |
| 45 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ |
| 46 | #if 0 |
| 47 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
| 48 | #else |
| 49 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 50 | #endif |
| 51 | |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 52 | #undef CONFIG_BOOTARGS |
| 53 | #define CONFIG_BOOTCOMMAND \ |
| 54 | "bootp; " \ |
Wolfgang Denk | fe126d8 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 55 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
| 56 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 57 | "bootm" |
| 58 | |
| 59 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 60 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| 61 | |
wdenk | ca75add | 2003-08-29 10:05:53 +0000 | [diff] [blame] | 62 | /* enable I2C and select the hardware/software driver */ |
| 63 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ |
| 64 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
| 65 | |
| 66 | #define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */ |
| 67 | #define CFG_I2C_SLAVE 0xFE |
| 68 | |
| 69 | /* Software (bit-bang) I2C driver configuration */ |
| 70 | #define PB_SCL 0x00000020 /* PB 26 */ |
| 71 | #define PB_SDA 0x00000010 /* PB 27 */ |
| 72 | |
| 73 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
| 74 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
| 75 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
| 76 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
| 77 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
| 78 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
| 79 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
| 80 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
| 81 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
| 82 | |
| 83 | /* M41T11 Serial Access Timekeeper(R) SRAM */ |
| 84 | #define CONFIG_RTC_M41T11 1 |
| 85 | #define CFG_I2C_RTC_ADDR 0x68 |
| 86 | #define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ |
| 87 | |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 88 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 89 | |
wdenk | ca75add | 2003-08-29 10:05:53 +0000 | [diff] [blame] | 90 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
| 91 | CFG_CMD_DATE | \ |
| 92 | CFG_CMD_DHCP | \ |
wdenk | 414eec3 | 2005-04-02 22:37:54 +0000 | [diff] [blame] | 93 | CFG_CMD_I2C | \ |
| 94 | CFG_CMD_NFS | \ |
| 95 | CFG_CMD_SNTP ) |
wdenk | ca75add | 2003-08-29 10:05:53 +0000 | [diff] [blame] | 96 | |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 97 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
| 98 | |
| 99 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
| 100 | #include <cmd_confdefs.h> |
| 101 | |
wdenk | af6d1df | 2003-12-03 23:53:42 +0000 | [diff] [blame] | 102 | #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ |
| 103 | #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" |
| 104 | #define CONFIG_AUTOBOOT_DELAY_STR "system" |
| 105 | |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 106 | /* |
| 107 | * Miscellaneous configurable options |
| 108 | */ |
| 109 | #define CFG_LONGHELP /* undef to save memory */ |
| 110 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 111 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 112 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 113 | #else |
| 114 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 115 | #endif |
| 116 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 117 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 118 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 119 | |
| 120 | #define CFG_MEMTEST_START 0x0040000 /* memtest works on */ |
| 121 | #define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ |
| 122 | |
| 123 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
| 124 | |
| 125 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 126 | |
| 127 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 128 | |
| 129 | /* |
| 130 | * Low Level Configuration Settings |
| 131 | * (address mappings, register initial values, etc.) |
| 132 | * You should know what you are doing if you make changes here. |
| 133 | */ |
| 134 | /*----------------------------------------------------------------------- |
| 135 | * Internal Memory Mapped Register |
| 136 | */ |
| 137 | #define CFG_IMMR 0xFA200000 |
| 138 | |
| 139 | /*----------------------------------------------------------------------- |
| 140 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 141 | */ |
| 142 | #define CFG_INIT_RAM_ADDR CFG_IMMR |
| 143 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
| 144 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
| 145 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 146 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 147 | |
| 148 | /*----------------------------------------------------------------------- |
| 149 | * Start addresses for the final memory configuration |
| 150 | * (Set up by the startup code) |
| 151 | * Please note that CFG_SDRAM_BASE _must_ start at 0 |
| 152 | */ |
| 153 | #define CFG_SDRAM_BASE 0x00000000 |
wdenk | 7e78036 | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 154 | #define CFG_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */ |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 155 | #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) |
| 156 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 157 | #else |
| 158 | #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
| 159 | #endif |
wdenk | 7e78036 | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 160 | #define CFG_MONITOR_BASE TEXT_BASE |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 161 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
| 162 | |
| 163 | /* |
| 164 | * For booting Linux, the board info and command line data |
| 165 | * have to be in the first 8 MB of memory, since this is |
| 166 | * the maximum mapped by the Linux kernel during initialization. |
| 167 | */ |
| 168 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 169 | |
| 170 | /*----------------------------------------------------------------------- |
| 171 | * FLASH organization |
| 172 | */ |
| 173 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
wdenk | 7e78036 | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 174 | #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 175 | |
| 176 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 177 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
| 178 | |
| 179 | #define CFG_ENV_IS_IN_FLASH 1 |
wdenk | 7e78036 | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 180 | #define CFG_ENV_ADDR ((TEXT_BASE) + 0x40000) |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 181 | #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 182 | |
| 183 | /* Address and size of Redundant Environment Sector */ |
wdenk | 7e78036 | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 184 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE) |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 185 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
| 186 | |
| 187 | /*----------------------------------------------------------------------- |
wdenk | ca75add | 2003-08-29 10:05:53 +0000 | [diff] [blame] | 188 | * Reset address |
| 189 | */ |
| 190 | #define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) |
| 191 | |
| 192 | /*----------------------------------------------------------------------- |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 193 | * Cache Configuration |
| 194 | */ |
| 195 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
| 196 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 197 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
| 198 | #endif |
| 199 | |
| 200 | /*----------------------------------------------------------------------- |
| 201 | * SYPCR - System Protection Control 11-9 |
| 202 | * SYPCR can only be written once after reset! |
| 203 | *----------------------------------------------------------------------- |
| 204 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
| 205 | */ |
| 206 | #if defined(CONFIG_WATCHDOG) |
| 207 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
| 208 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 209 | #else |
| 210 | #define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
| 211 | #endif |
| 212 | |
| 213 | /*----------------------------------------------------------------------- |
| 214 | * SIUMCR - SIU Module Configuration 11-6 |
| 215 | *----------------------------------------------------------------------- |
| 216 | * PCMCIA config., multi-function pin tri-state |
| 217 | */ |
| 218 | #define CFG_SIUMCR (SIUMCR_MLRC10) |
| 219 | |
| 220 | /*----------------------------------------------------------------------- |
| 221 | * TBSCR - Time Base Status and Control 11-26 |
| 222 | *----------------------------------------------------------------------- |
| 223 | * Clear Reference Interrupt Status, Timebase freezing enabled |
| 224 | */ |
| 225 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) |
| 226 | |
| 227 | /*----------------------------------------------------------------------- |
| 228 | * RTCSC - Real-Time Clock Status and Control Register 11-27 |
| 229 | *----------------------------------------------------------------------- |
| 230 | */ |
| 231 | /*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ |
| 232 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) |
| 233 | |
| 234 | /*----------------------------------------------------------------------- |
| 235 | * PISCR - Periodic Interrupt Status and Control 11-31 |
| 236 | *----------------------------------------------------------------------- |
| 237 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
| 238 | */ |
| 239 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) |
| 240 | |
| 241 | /*----------------------------------------------------------------------- |
| 242 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
| 243 | *----------------------------------------------------------------------- |
| 244 | * Reset PLL lock status sticky bit, timer expired status bit and timer |
| 245 | * interrupt status bit |
| 246 | * |
| 247 | * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! |
| 248 | */ |
| 249 | /* up to 50 MHz we use a 1:1 clock */ |
| 250 | #define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) |
| 251 | |
| 252 | /*----------------------------------------------------------------------- |
| 253 | * SCCR - System Clock and reset Control Register 15-27 |
| 254 | *----------------------------------------------------------------------- |
| 255 | * Set clock output, timebase and RTC source and divider, |
| 256 | * power management and some other internal clocks |
| 257 | */ |
| 258 | #define SCCR_MASK SCCR_EBDF00 |
| 259 | /* up to 50 MHz we use a 1:1 clock */ |
| 260 | #define CFG_SCCR (SCCR_COM00 | SCCR_TBS) |
| 261 | |
| 262 | /*----------------------------------------------------------------------- |
| 263 | * PCMCIA stuff |
| 264 | *----------------------------------------------------------------------- |
| 265 | * |
| 266 | */ |
| 267 | #define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
| 268 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
| 269 | #define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
| 270 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
| 271 | #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
| 272 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
| 273 | #define CFG_PCMCIA_IO_ADDR (0xEC000000) |
| 274 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
| 275 | |
| 276 | /*----------------------------------------------------------------------- |
| 277 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
| 278 | *----------------------------------------------------------------------- |
| 279 | */ |
| 280 | |
| 281 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
| 282 | |
| 283 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
| 284 | #undef CONFIG_IDE_LED /* LED for ide not supported */ |
| 285 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
| 286 | |
| 287 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 288 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
| 289 | |
| 290 | #define CFG_ATA_IDE0_OFFSET 0x0000 |
| 291 | |
| 292 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
| 293 | |
| 294 | /* Offset for data I/O */ |
| 295 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
| 296 | |
| 297 | /* Offset for normal register accesses */ |
| 298 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
| 299 | |
| 300 | /* Offset for alternate registers */ |
| 301 | #define CFG_ATA_ALT_OFFSET 0x0100 |
| 302 | |
| 303 | /*----------------------------------------------------------------------- |
| 304 | * |
| 305 | *----------------------------------------------------------------------- |
| 306 | * |
| 307 | */ |
| 308 | /*#define CFG_DER 0x2002000F*/ |
| 309 | #define CFG_DER 0 |
| 310 | |
| 311 | /* |
| 312 | * Init Memory Controller: |
| 313 | * |
| 314 | * BR0 and OR0 (FLASH) |
| 315 | */ |
| 316 | |
wdenk | 7e78036 | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 317 | #define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base - up to 64 MB of flash */ |
| 318 | #define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask - map 64 MB */ |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 319 | |
| 320 | /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ |
| 321 | #define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) |
| 322 | |
| 323 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
| 324 | #define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) |
| 325 | |
| 326 | /* |
| 327 | * BR1 and OR1 (SDRAM) |
| 328 | * |
| 329 | */ |
| 330 | #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ |
wdenk | d94f92c | 2003-08-28 09:41:22 +0000 | [diff] [blame] | 331 | #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 332 | |
| 333 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
| 334 | #define CFG_OR_TIMING_SDRAM 0x00000E00 |
| 335 | |
wdenk | d94f92c | 2003-08-28 09:41:22 +0000 | [diff] [blame] | 336 | #define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */ |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 337 | #define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
| 338 | |
| 339 | /* RPXLITE mem setting */ |
wdenk | 7e78036 | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 340 | #define CFG_NVRAM_BASE 0xFA000000 /* NVRAM & SRAM base */ |
| 341 | /* IMMR: 0xFA200000 IMMR base address - see above */ |
| 342 | #define CFG_BCSR_BASE 0xFA400000 /* BCSR base address */ |
| 343 | |
| 344 | #define CFG_BR3_PRELIM (CFG_BCSR_BASE | BR_V) /* BCSR */ |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 345 | #define CFG_OR3_PRELIM 0xFFFF8910 |
wdenk | 7e78036 | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 346 | #define CFG_BR4_PRELIM (CFG_NVRAM_BASE | BR_PS_8 | BR_V) /* NVRAM & SRAM */ |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 347 | #define CFG_OR4_PRELIM 0xFFFE0970 |
| 348 | |
| 349 | /* |
| 350 | * Memory Periodic Timer Prescaler |
| 351 | */ |
| 352 | |
| 353 | /* periodic timer for refresh */ |
| 354 | #define CFG_MAMR_PTA 20 |
| 355 | |
| 356 | /* |
| 357 | * Refresh clock Prescalar |
| 358 | */ |
| 359 | #define CFG_MPTPR MPTPR_PTP_DIV2 |
| 360 | |
| 361 | /* |
| 362 | * MAMR settings for SDRAM |
| 363 | */ |
| 364 | |
wdenk | d94f92c | 2003-08-28 09:41:22 +0000 | [diff] [blame] | 365 | /* 9 column SDRAM */ |
| 366 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 367 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
| 368 | MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) |
| 369 | |
| 370 | /* |
| 371 | * Internal Definitions |
| 372 | * |
| 373 | * Boot Flags |
| 374 | */ |
| 375 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 376 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 377 | |
| 378 | /* |
| 379 | * BCSRx |
| 380 | * |
| 381 | * Board Status and Control Registers |
| 382 | * |
| 383 | */ |
| 384 | |
wdenk | 7e78036 | 2004-04-08 22:31:29 +0000 | [diff] [blame] | 385 | #define BCSR0 (CFG_BCSR_BASE + 0) |
| 386 | #define BCSR1 (CFG_BCSR_BASE + 1) |
| 387 | #define BCSR2 (CFG_BCSR_BASE + 2) |
| 388 | #define BCSR3 (CFG_BCSR_BASE + 3) |
wdenk | 73a8b27 | 2003-06-05 19:27:42 +0000 | [diff] [blame] | 389 | |
| 390 | #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ |
| 391 | #define BCSR0_ENNVRAM 0x02 /* CS4# Control */ |
| 392 | #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ |
| 393 | #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ |
| 394 | #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ |
| 395 | #define BCSR0_COLTEST 0x20 |
| 396 | #define BCSR0_ETHLPBK 0x40 |
| 397 | #define BCSR0_ETHEN 0x80 |
| 398 | |
| 399 | #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ |
| 400 | #define BCSR1_PCVCTL6 0x02 |
| 401 | #define BCSR1_PCVCTL5 0x04 |
| 402 | #define BCSR1_PCVCTL4 0x08 |
| 403 | #define BCSR1_IPB5SEL 0x10 |
| 404 | |
| 405 | #define BCSR2_ENPA5HDR 0x08 /* USB Control */ |
| 406 | #define BCSR2_ENUSBCLK 0x10 |
| 407 | #define BCSR2_USBPWREN 0x20 |
| 408 | #define BCSR2_USBSPD 0x40 |
| 409 | #define BCSR2_USBSUSP 0x80 |
| 410 | |
| 411 | #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ |
| 412 | #define BCSR3_BWNVR 0x02 /* NVRAM Battery */ |
| 413 | #define BCSR3_RDY_BSY 0x04 /* Flash Operation */ |
| 414 | #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ |
| 415 | #define BCSR3_D27 0x10 /* Dip Switch settings */ |
| 416 | #define BCSR3_D26 0x20 |
| 417 | #define BCSR3_D25 0x40 |
| 418 | #define BCSR3_D24 0x80 |
| 419 | |
| 420 | #endif /* __CONFIG_H */ |