Dave Gerlach | a8c13c7 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | /* |
| 3 | * Cadence DDR Driver |
| 4 | * |
Bryan Brattlof | ee31be4 | 2022-10-24 16:53:28 -0500 | [diff] [blame] | 5 | * Copyright (C) 2012-2022 Cadence Design Systems, Inc. |
| 6 | * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ |
Dave Gerlach | a8c13c7 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef LPDDR4_H |
| 10 | #define LPDDR4_H |
| 11 | |
| 12 | #include "lpddr4_ctl_regs.h" |
| 13 | #include "lpddr4_sanity.h" |
Dave Gerlach | a8c13c7 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 14 | |
Bryan Brattlof | ee31be4 | 2022-10-24 16:53:28 -0500 | [diff] [blame] | 15 | #if defined (CONFIG_K3_AM64_DDRSS) || defined (CONFIG_K3_AM62A_DDRSS) |
| 16 | #include "lpddr4_am6x.h" |
| 17 | #include "lpddr4_am6x_sanity.h" |
| 18 | #else |
| 19 | #include "lpddr4_j721e.h" |
| 20 | #include "lpddr4_j721e_sanity.h" |
Dave Gerlach | a8c13c7 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 21 | #endif |
| 22 | |
| 23 | #define PRODUCT_ID (0x1046U) |
| 24 | |
| 25 | #define LPDDR4_BIT_MASK (0x1U) |
| 26 | #define BYTE_MASK (0xffU) |
| 27 | #define NIBBLE_MASK (0xfU) |
| 28 | |
| 29 | #define WORD_SHIFT (32U) |
| 30 | #define WORD_MASK (0xffffffffU) |
| 31 | #define SLICE_WIDTH (0x100) |
| 32 | |
| 33 | #define CTL_OFFSET 0 |
| 34 | #define PI_OFFSET (((u32)1) << 11) |
| 35 | #define PHY_OFFSET (((u32)1) << 12) |
| 36 | |
| 37 | #define CTL_INT_MASK_ALL ((u32)LPDDR4_LOR_BITS - WORD_SHIFT) |
| 38 | |
| 39 | #define PLL_READY (0x3U) |
| 40 | #define IO_CALIB_DONE ((u32)0x1U << 23U) |
| 41 | #define IO_CALIB_FIELD ((u32)NIBBLE_MASK << 28U) |
| 42 | #define IO_CALIB_STATE ((u32)0xBU << 28U) |
| 43 | #define RX_CAL_DONE ((u32)LPDDR4_BIT_MASK << 4U) |
| 44 | #define CA_TRAIN_RL (((u32)LPDDR4_BIT_MASK << 5U) | ((u32)LPDDR4_BIT_MASK << 4U)) |
| 45 | #define WR_LVL_STATE (((u32)NIBBLE_MASK) << 13U) |
| 46 | #define GATE_LVL_ERROR_FIELDS (((u32)LPDDR4_BIT_MASK << 7U) | ((u32)LPDDR4_BIT_MASK << 6U)) |
| 47 | #define READ_LVL_ERROR_FIELDS ((((u32)NIBBLE_MASK) << 28U) | (((u32)BYTE_MASK) << 16U)) |
| 48 | #define DQ_LVL_STATUS (((u32)LPDDR4_BIT_MASK << 26U) | (((u32)BYTE_MASK) << 18U)) |
| 49 | |
| 50 | #define CDN_TRUE 1U |
| 51 | #define CDN_FALSE 0U |
| 52 | |
Bryan Brattlof | ee31be4 | 2022-10-24 16:53:28 -0500 | [diff] [blame] | 53 | #ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY |
| 54 | #define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U |
| 55 | #endif |
| 56 | |
| 57 | #ifndef LPDDR4_CPS_NS_DELAY_TIME |
| 58 | #define LPDDR4_CPS_NS_DELAY_TIME 10000000U |
| 59 | #endif |
| 60 | |
Dave Gerlach | a8c13c7 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 61 | void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound); |
| 62 | volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset); |
| 63 | u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay); |
| 64 | bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound); |
| 65 | void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr); |
| 66 | |
| 67 | u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd); |
| 68 | void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr); |
| 69 | u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus); |
| 70 | u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset); |
Dave Gerlach | a8c13c7 | 2021-05-11 10:22:11 -0500 | [diff] [blame] | 71 | |
| 72 | #endif /* LPDDR4_H */ |