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Thomas Choue6e2c152015-10-18 19:42:09 +08001/*
2 * Copyright (C) 2013 Altera Corporation
3 *
4 * This file is generated by sopc2dts.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9/dts-v1/;
10
11/ {
12 model = "altr,qsys_ghrd_3c120";
13 compatible = "altr,qsys_ghrd_3c120";
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu: cpu@0x0 {
22 device_type = "cpu";
23 compatible = "altr,nios2-1.0";
24 reg = <0x00000000>;
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 clock-frequency = <125000000>;
28 dcache-line-size = <32>;
29 icache-line-size = <32>;
30 dcache-size = <32768>;
31 icache-size = <32768>;
32 altr,implementation = "fast";
33 altr,pid-num-bits = <8>;
34 altr,tlb-num-ways = <16>;
35 altr,tlb-num-entries = <128>;
36 altr,tlb-ptr-sz = <7>;
37 altr,has-div = <1>;
38 altr,has-mul = <1>;
39 altr,reset-addr = <0xc2800000>;
40 altr,fast-tlb-miss-addr = <0xc7fff400>;
41 altr,exception-addr = <0xd0000020>;
42 altr,has-initda = <1>;
43 altr,has-mmu = <1>;
44 };
45 };
46
47 memory@0 {
48 device_type = "memory";
49 reg = <0x10000000 0x08000000>,
50 <0x07fff400 0x00000400>;
51 };
52
53 sopc@0 {
54 device_type = "soc";
55 ranges;
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "altr,avalon", "simple-bus";
59 bus-frequency = <125000000>;
60
61 pb_cpu_to_io: bridge@0x8000000 {
62 compatible = "simple-bus";
63 reg = <0x08000000 0x00800000>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges = <0x00002000 0x08002000 0x00002000>,
67 <0x00004000 0x08004000 0x00000400>,
68 <0x00004400 0x08004400 0x00000040>,
69 <0x00004800 0x08004800 0x00000040>,
70 <0x00004c80 0x08004c80 0x00000020>,
Thomas Chou88d5ecf2015-10-21 21:33:45 +080071 <0x00004cc0 0x08004cc0 0x00000010>,
72 <0x00004ce0 0x08004ce0 0x00000010>,
73 <0x00004d00 0x08004d00 0x00000010>,
Thomas Chouca844dd2015-10-14 08:43:31 +080074 <0x00004d40 0x08004d40 0x00000008>,
Thomas Choue6e2c152015-10-18 19:42:09 +080075 <0x00004d50 0x08004d50 0x00000008>,
76 <0x00008000 0x08008000 0x00000020>,
77 <0x00400000 0x08400000 0x00000020>;
78
79 timer_1ms: timer@0x400000 {
80 compatible = "altr,timer-1.0";
81 reg = <0x00400000 0x00000020>;
82 interrupt-parent = <&cpu>;
83 interrupts = <11>;
84 clock-frequency = <125000000>;
85 };
86
87 timer_0: timer@0x8000 {
88 compatible = "altr,timer-1.0";
89 reg = < 0x00008000 0x00000020 >;
90 interrupt-parent = < &cpu >;
91 interrupts = < 5 >;
92 clock-frequency = < 125000000 >;
93 };
94
Thomas Chouca844dd2015-10-14 08:43:31 +080095 sysid: sysid@0x4d40 {
96 compatible = "altr,sysid-1.0";
97 reg = <0x00004d40 0x00000008>;
98 };
99
Thomas Choue6e2c152015-10-18 19:42:09 +0800100 jtag_uart: serial@0x4d50 {
101 compatible = "altr,juart-1.0";
102 reg = <0x00004d50 0x00000008>;
103 interrupt-parent = <&cpu>;
104 interrupts = <1>;
105 };
106
107 tse_mac: ethernet@0x4000 {
108 compatible = "altr,tse-1.0";
109 reg = <0x00004000 0x00000400>,
110 <0x00004400 0x00000040>,
111 <0x00004800 0x00000040>,
112 <0x00002000 0x00002000>;
113 reg-names = "control_port", "rx_csr", "tx_csr", "s1";
114 interrupt-parent = <&cpu>;
115 interrupts = <2 3>;
116 interrupt-names = "rx_irq", "tx_irq";
117 rx-fifo-depth = <8192>;
118 tx-fifo-depth = <8192>;
119 max-frame-size = <1518>;
120 local-mac-address = [ 00 00 00 00 00 00 ];
121 phy-mode = "rgmii-id";
122 phy-handle = <&phy0>;
123 tse_mac_mdio: mdio {
124 compatible = "altr,tse-mdio";
125 #address-cells = <1>;
126 #size-cells = <0>;
127 phy0: ethernet-phy@18 {
128 reg = <18>;
129 device_type = "ethernet-phy";
130 };
131 };
132 };
133
134 uart: serial@0x4c80 {
135 compatible = "altr,uart-1.0";
136 reg = <0x00004c80 0x00000020>;
137 interrupt-parent = <&cpu>;
138 interrupts = <10>;
139 current-speed = <115200>;
140 clock-frequency = <62500000>;
141 };
Thomas Chou88d5ecf2015-10-21 21:33:45 +0800142
143 user_led_pio_8out: gpio@0x4cc0 {
144 compatible = "altr,pio-1.0";
145 reg = <0x00004cc0 0x00000010>;
146 resetvalue = <255>;
147 altr,gpio-bank-width = <8>;
148 #gpio-cells = <2>;
149 gpio-controller;
150 gpio-bank-name = "led";
151 };
152
153 user_dipsw_pio_8in: gpio@0x4ce0 {
154 compatible = "altr,pio-1.0";
155 reg = <0x00004ce0 0x00000010>;
156 interrupt-parent = <&cpu>;
157 interrupts = <8>;
158 edge_type = <2>;
159 level_trigger = <0>;
160 resetvalue = <0>;
161 altr,gpio-bank-width = <8>;
162 #gpio-cells = <2>;
163 gpio-controller;
164 gpio-bank-name = "dipsw";
165 };
166
167 user_pb_pio_4in: gpio@0x4d00 {
168 compatible = "altr,pio-1.0";
169 reg = <0x00004d00 0x00000010>;
170 interrupt-parent = <&cpu>;
171 interrupts = <9>;
172 edge_type = <2>;
173 level_trigger = <0>;
174 resetvalue = <0>;
175 altr,gpio-bank-width = <4>;
176 #gpio-cells = <2>;
177 gpio-controller;
178 gpio-bank-name = "pb";
179 };
Thomas Choue6e2c152015-10-18 19:42:09 +0800180 };
181
182 cfi_flash_64m: flash@0x0 {
183 compatible = "cfi-flash";
184 reg = <0x00000000 0x04000000>;
185 bank-width = <2>;
186 device-width = <1>;
187 #address-cells = <1>;
188 #size-cells = <1>;
189
190 partition@800000 {
191 reg = <0x00800000 0x01e00000>;
192 label = "JFFS2 Filesystem";
193 };
194 };
195 };
196
197 chosen {
198 bootargs = "debug console=ttyJ0,115200";
Thomas Chou220e8022015-10-23 07:36:37 +0800199 stdout-path = &jtag_uart;
Thomas Choue6e2c152015-10-18 19:42:09 +0800200 };
201};