blob: c8c48aeac43be38af2d6204c6b5ece1f03535b7f [file] [log] [blame]
Aubrey.Li3f0606a2007-03-09 13:38:44 +08001/*
Bin Menga1875592016-02-05 19:30:11 -08002 * U-Boot - Configuration file for BF533 STAMP board
Aubrey.Li3f0606a2007-03-09 13:38:44 +08003 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF533_STAMP_H__
6#define __CONFIG_BF533_STAMP_H__
Aubrey.Li3f0606a2007-03-09 13:38:44 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Aubrey.Li3f0606a2007-03-09 13:38:44 +080010
Aubrey.Li3f0606a2007-03-09 13:38:44 +080011/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040012 * Processor Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080013 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf533-0.3
Mike Frysingercf6f4692008-06-01 09:09:48 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
Mike Frysingercf6f4692008-06-01 09:09:48 -040017/*
18 * Clock Settings
19 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
20 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
21 */
22/* CONFIG_CLKIN_HZ is any value in Hz */
23#define CONFIG_CLKIN_HZ 11059200
24/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
25/* 1 = CLKIN / 2 */
26#define CONFIG_CLKIN_HALF 0
27/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
28/* 1 = bypass PLL */
29#define CONFIG_PLL_BYPASS 0
30/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
31/* Values can range from 0-63 (where 0 means 64) */
Mike Frysinger9f64ba22008-10-12 23:49:13 -040032#define CONFIG_VCO_MULT 45
Mike Frysingercf6f4692008-06-01 09:09:48 -040033/* CCLK_DIV controls the core clock divider */
34/* Values can be 1, 2, 4, or 8 ONLY */
35#define CONFIG_CCLK_DIV 1
36/* SCLK_DIV controls the system clock divider */
37/* Values can range from 1-15 */
Mike Frysingerbaf35702009-07-10 10:42:06 -040038#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
Mike Frysingercf6f4692008-06-01 09:09:48 -040039
Mike Frysingercf6f4692008-06-01 09:09:48 -040040/*
41 * Memory Settings
42 */
43#define CONFIG_MEM_ADD_WDTH 11
44#define CONFIG_MEM_SIZE 128
45
46#define CONFIG_EBIU_SDRRC_VAL 0x268
47#define CONFIG_EBIU_SDGCTL_VAL 0x911109
48
49#define CONFIG_EBIU_AMGCTL_VAL 0xFF
50#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
51#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
52
53#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
54#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
55
56
57/*
58 * Network Settings
59 */
60#define ADI_CMDS_NETWORK 1
Ben Warren7194ab82009-10-04 22:37:03 -070061#define CONFIG_SMC91111 1
Aubrey Li8db13d62007-03-10 23:49:29 +080062#define CONFIG_SMC91111_BASE 0x20300300
Mike Frysingercf6f4692008-06-01 09:09:48 -040063#define SMC91111_EEPROM_INIT() \
64 do { \
Ben Warren7194ab82009-10-04 22:37:03 -070065 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
66 bfin_write_FIO_FLAG_C(PF1); \
67 bfin_write_FIO_FLAG_S(PF0); \
Mike Frysingercf6f4692008-06-01 09:09:48 -040068 SSYNC(); \
69 } while (0)
70#define CONFIG_HOSTNAME bf533-stamp
Aubrey.Li3f0606a2007-03-09 13:38:44 +080071
Aubrey.Li3f0606a2007-03-09 13:38:44 +080072
Heiko Schocherea818db2013-01-29 08:53:15 +010073/* I2C */
74#define CONFIG_SYS_I2C
75#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
76#define CONFIG_SYS_I2C_SOFT_SPEED 50000
77#define CONFIG_SYS_I2C_SOFT_SLAVE 0
78/*
79 * Software (bit-bang) I2C driver configuration
80 */
Sonic Zhange5cb60a2013-11-18 18:59:18 +080081#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
82#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
Heiko Schocherea818db2013-01-29 08:53:15 +010083
Aubrey.Li3f0606a2007-03-09 13:38:44 +080084/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040085 * Flash Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080086 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040087#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040089#define CONFIG_SYS_FLASH_CFI
90#define CONFIG_SYS_FLASH_CFI_AMD_RESET
91#define CONFIG_SYS_MAX_FLASH_BANKS 1
92#define CONFIG_SYS_MAX_FLASH_SECT 67
Aubrey.Li3f0606a2007-03-09 13:38:44 +080093
Mike Frysingercf6f4692008-06-01 09:09:48 -040094/*
95 * SPI Settings
96 */
97#define CONFIG_BFIN_SPI
98#define CONFIG_ENV_SPI_MAX_HZ 30000000
Sonic Zhangc49eabe2014-07-17 19:00:29 +080099/*
Mike Frysingerafac8b02009-06-14 22:29:35 -0400100#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingerf4532202010-09-19 16:26:55 -0400101#define CONFIG_SPI_FLASH_ALL
Sonic Zhangc49eabe2014-07-17 19:00:29 +0800102*/
Mike Frysingercf6f4692008-06-01 09:09:48 -0400103
104/*
105 * Env Storage Settings
106 */
Mike Frysinger9171fc82008-03-30 15:46:13 -0400107#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysingercf6f4692008-06-01 09:09:48 -0400108#define CONFIG_ENV_IS_IN_SPI_FLASH
Vivi Libc43a8d2009-06-12 10:53:22 +0000109#define CONFIG_ENV_OFFSET 0x10000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400110#define CONFIG_ENV_SIZE 0x2000
Vivi Libc43a8d2009-06-12 10:53:22 +0000111#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysinger9171fc82008-03-30 15:46:13 -0400112#else
Mike Frysingercf6f4692008-06-01 09:09:48 -0400113#define CONFIG_ENV_IS_IN_FLASH
114#define CONFIG_ENV_OFFSET 0x4000
115#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
116#define CONFIG_ENV_SIZE 0x2000
117#define CONFIG_ENV_SECT_SIZE 0x2000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800118#endif
Mike Frysingercf6f4692008-06-01 09:09:48 -0400119#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
120#define ENV_IS_EMBEDDED
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800121#else
Mike Frysinger76d82182009-07-21 22:17:36 -0400122#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800123#endif
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400124#ifdef ENV_IS_EMBEDDED
125/* WARNING - the following is hand-optimized to fit within
126 * the sector before the environment sector. If it throws
127 * an error during compilation remove an object here to get
128 * it linked after the configuration sector.
129 */
130# define LDS_BOARD_TEXT \
Masahiro Yamadae2906a52013-11-11 14:36:00 +0900131 arch/blackfin/lib/built-in.o (.text*); \
132 arch/blackfin/cpu/built-in.o (.text*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400133 . = DEFINED(env_offset) ? env_offset : .; \
Mike Frysingerc70e7dd2010-11-19 19:28:56 -0500134 common/env_embedded.o (.text*);
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400135#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800136
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800137
Jon Loeligerba2351f2007-07-04 22:31:49 -0500138/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400139 * I2C Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800140 */
Heiko Schocherea818db2013-01-29 08:53:15 +0100141#define CONFIG_SYS_I2C_SOFT
142#ifdef CONFIG_SYS_I2C_SOFT
143#define CONFIG_SYS_I2C
Mike Frysingerbeb60e72010-06-08 16:22:44 -0400144#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
145#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
Heiko Schocherea818db2013-01-29 08:53:15 +0100146#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
147#define CONFIG_SYS_I2C_SOFT_SPEED 50000
148#define CONFIG_SYS_I2C_SOFT_SLAVE 0
149#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800150
151/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400152 * Compact Flash / IDE / ATA Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800153 */
154
155/* Enabled below option for CF support */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400156/* #define CONFIG_STAMP_CF */
157#if defined(CONFIG_STAMP_CF)
158#define CONFIG_MISC_INIT_R
Aubrey Li8db13d62007-03-10 23:49:29 +0800159#define CONFIG_DOS_PARTITION 1
Aubrey Li8db13d62007-03-10 23:49:29 +0800160#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
161#undef CONFIG_IDE_LED /* no led for ide supported */
162#undef CONFIG_IDE_RESET /* no reset for ide supported */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800163
Mike Frysingercf6f4692008-06-01 09:09:48 -0400164#define CONFIG_SYS_IDE_MAXBUS 1
165#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
168#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800169
Mike Frysingercf6f4692008-06-01 09:09:48 -0400170#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
171#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
172#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_ATA_STRIDE 2
Mike Frysingercf6f4692008-06-01 09:09:48 -0400175
176#undef CONFIG_EBIU_AMBCTL1_VAL
177#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800178#endif
179
Mike Frysingercf6f4692008-06-01 09:09:48 -0400180
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800181/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400182 * Misc Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800183 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400184#define CONFIG_RTC_BFIN
185#define CONFIG_UART_CONSOLE 0
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800186
Mike Frysingercf6f4692008-06-01 09:09:48 -0400187/* FLASH/ETHERNET uses the same async bank */
188#define SHARED_RESOURCES 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800189
Mike Frysinger23fd9592008-10-11 22:40:22 -0400190/* define to enable boot progress via leds */
191/* #define CONFIG_SHOW_BOOT_PROGRESS */
192
193/* define to enable run status via led */
194/* #define CONFIG_STATUS_LED */
195#ifdef CONFIG_STATUS_LED
Mike Frysingera84774f2010-06-02 05:12:11 -0400196#define CONFIG_GPIO_LED
Mike Frysinger23fd9592008-10-11 22:40:22 -0400197#define CONFIG_BOARD_SPECIFIC_LED
Mike Frysingera84774f2010-06-02 05:12:11 -0400198/* use LED0 to indicate booting/alive */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400199#define STATUS_LED_BOOT 0
Mike Frysingera84774f2010-06-02 05:12:11 -0400200#define STATUS_LED_BIT GPIO_PF2
Mike Frysinger23fd9592008-10-11 22:40:22 -0400201#define STATUS_LED_STATE STATUS_LED_ON
202#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
Mike Frysingera84774f2010-06-02 05:12:11 -0400203/* use LED1 to indicate crash */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400204#define STATUS_LED_CRASH 1
Mike Frysingera84774f2010-06-02 05:12:11 -0400205#define STATUS_LED_BIT1 GPIO_PF3
Mike Frysinger23fd9592008-10-11 22:40:22 -0400206#define STATUS_LED_STATE1 STATUS_LED_ON
207#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
Mike Frysingera84774f2010-06-02 05:12:11 -0400208/* #define STATUS_LED_BIT2 GPIO_PF4 */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400209#endif
210
Mike Frysingercf6f4692008-06-01 09:09:48 -0400211/* define to enable splash screen support */
212/* #define CONFIG_VIDEO */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800213
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800214
215/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400216 * Pull in common ADI header for remaining command/environment setup
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800217 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400218#include <configs/bfin_adi_common.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -0400219
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800220#endif