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Lokesh Vutla351f9692015-09-19 15:00:18 +05301/*
2 * Copyright 2013 Texas Instruments, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/gpio/gpio.h>
11
12#include "skeleton.dtsi"
13
14/ {
15 model = "Texas Instruments Keystone 2 SoC";
Lokesh Vutla8a9bb062015-09-19 15:00:19 +053016 #address-cells = <1>;
17 #size-cells = <1>;
Lokesh Vutla351f9692015-09-19 15:00:18 +053018 interrupt-parent = <&gic>;
19
20 aliases {
21 serial0 = &uart0;
Vignesh Re5fcf032016-07-06 09:58:58 +053022 spi0 = &spi0;
23 spi1 = &spi1;
24 spi2 = &spi2;
Cooper Jr., Franklinc7d45ff2017-04-20 10:25:47 -050025 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
Lokesh Vutla351f9692015-09-19 15:00:18 +053028 };
29
Lokesh Vutla391839f2015-09-19 15:00:20 +053030 chosen {
31 stdout-path = &uart0;
32 };
33
Lokesh Vutla351f9692015-09-19 15:00:18 +053034 memory {
Lokesh Vutla8a9bb062015-09-19 15:00:19 +053035 reg = <0x80000000 0x40000000>;
Lokesh Vutla351f9692015-09-19 15:00:18 +053036 };
37
38 gic: interrupt-controller {
39 compatible = "arm,cortex-a15-gic";
40 #interrupt-cells = <3>;
41 interrupt-controller;
Lokesh Vutla8a9bb062015-09-19 15:00:19 +053042 reg = <0x02561000 0x1000>,
43 <0x02562000 0x2000>,
44 <0x02564000 0x1000>,
45 <0x02566000 0x2000>;
Lokesh Vutla351f9692015-09-19 15:00:18 +053046 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
47 IRQ_TYPE_LEVEL_HIGH)>;
48 };
49
50 timer {
51 compatible = "arm,armv7-timer";
52 interrupts =
53 <GIC_PPI 13
54 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
55 <GIC_PPI 14
56 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
57 <GIC_PPI 11
58 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
59 <GIC_PPI 10
60 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
61 };
62
63 pmu {
64 compatible = "arm,cortex-a15-pmu";
65 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
66 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
67 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
68 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
69 };
70
71 soc {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "ti,keystone","simple-bus";
75 interrupt-parent = <&gic>;
Lokesh Vutla8a9bb062015-09-19 15:00:19 +053076 ranges;
Lokesh Vutla351f9692015-09-19 15:00:18 +053077
78 pllctrl: pll-controller@02310000 {
79 compatible = "ti,keystone-pllctrl", "syscon";
80 reg = <0x02310000 0x200>;
81 };
82
83 devctrl: device-state-control@02620000 {
84 compatible = "ti,keystone-devctrl", "syscon";
85 reg = <0x02620000 0x1000>;
86 };
87
88 rstctrl: reset-controller {
89 compatible = "ti,keystone-reset";
90 ti,syscon-pll = <&pllctrl 0xe4>;
91 ti,syscon-dev = <&devctrl 0x328>;
92 ti,wdt-list = <0>;
93 };
94
95 /include/ "keystone-clocks.dtsi"
96
97 uart0: serial@02530c00 {
98 compatible = "ns16550a";
99 current-speed = <115200>;
100 reg-shift = <2>;
101 reg-io-width = <4>;
102 reg = <0x02530c00 0x100>;
103 clocks = <&clkuart0>;
104 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
105 };
106
107 uart1: serial@02531000 {
108 compatible = "ns16550a";
109 current-speed = <115200>;
110 reg-shift = <2>;
111 reg-io-width = <4>;
112 reg = <0x02531000 0x100>;
113 clocks = <&clkuart1>;
114 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
115 };
116
117 i2c0: i2c@2530000 {
118 compatible = "ti,davinci-i2c";
119 reg = <0x02530000 0x400>;
120 clock-frequency = <100000>;
121 clocks = <&clki2c>;
122 interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 };
126
127 i2c1: i2c@2530400 {
128 compatible = "ti,davinci-i2c";
129 reg = <0x02530400 0x400>;
130 clock-frequency = <100000>;
131 clocks = <&clki2c>;
132 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
133 #address-cells = <1>;
134 #size-cells = <0>;
135 };
136
137 i2c2: i2c@2530800 {
138 compatible = "ti,davinci-i2c";
139 reg = <0x02530800 0x400>;
140 clock-frequency = <100000>;
141 clocks = <&clki2c>;
142 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
143 #address-cells = <1>;
144 #size-cells = <0>;
145 };
146
147 spi0: spi@21000400 {
148 compatible = "ti,dm6441-spi";
149 reg = <0x21000400 0x200>;
150 num-cs = <4>;
151 ti,davinci-spi-intr-line = <0>;
152 interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
153 clocks = <&clkspi>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156 };
157
158 spi1: spi@21000600 {
159 compatible = "ti,dm6441-spi";
160 reg = <0x21000600 0x200>;
161 num-cs = <4>;
162 ti,davinci-spi-intr-line = <0>;
163 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
164 clocks = <&clkspi>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 };
168
169 spi2: spi@21000800 {
170 compatible = "ti,dm6441-spi";
171 reg = <0x21000800 0x200>;
172 num-cs = <4>;
173 ti,davinci-spi-intr-line = <0>;
174 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
175 clocks = <&clkspi>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 };
179
180 usb_phy: usb_phy@2620738 {
181 compatible = "ti,keystone-usbphy";
182 #address-cells = <1>;
183 #size-cells = <1>;
184 reg = <0x2620738 24>;
185 status = "disabled";
186 };
187
188 usb: usb@2680000 {
189 compatible = "ti,keystone-dwc3";
190 #address-cells = <1>;
191 #size-cells = <1>;
192 reg = <0x2680000 0x10000>;
193 clocks = <&clkusb>;
194 clock-names = "usb";
195 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
196 ranges;
197 dma-coherent;
198 dma-ranges;
199 status = "disabled";
200
201 dwc3@2690000 {
202 compatible = "synopsys,dwc3";
203 reg = <0x2690000 0x70000>;
204 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
205 usb-phy = <&usb_phy>, <&usb_phy>;
206 };
207 };
208
209 wdt: wdt@022f0080 {
210 compatible = "ti,keystone-wdt","ti,davinci-wdt";
211 reg = <0x022f0080 0x80>;
212 clocks = <&clkwdtimer0>;
213 };
214
215 clock_event: timer@22f0000 {
216 compatible = "ti,keystone-timer";
217 reg = <0x022f0000 0x80>;
218 interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
219 clocks = <&clktimer15>;
220 };
221
222 gpio0: gpio@260bf00 {
223 compatible = "ti,keystone-gpio";
224 reg = <0x0260bf00 0x100>;
225 gpio-controller;
226 #gpio-cells = <2>;
227 /* HW Interrupts mapped to GPIO pins */
228 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
229 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
230 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
231 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
232 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
233 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
234 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
235 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
236 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
237 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
238 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
239 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
240 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
241 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
242 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
243 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
244 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
245 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
246 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
247 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
248 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
249 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
250 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
251 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
252 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
254 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
255 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
256 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
257 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
258 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
259 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
260 clocks = <&clkgpio>;
261 clock-names = "gpio";
262 ti,ngpio = <32>;
263 ti,davinci-gpio-unbanked = <32>;
264 };
265
266 aemif: aemif@21000A00 {
267 compatible = "ti,keystone-aemif", "ti,davinci-aemif";
268 #address-cells = <2>;
269 #size-cells = <1>;
270 clocks = <&clkaemif>;
271 clock-names = "aemif";
272 clock-ranges;
273
274 reg = <0x21000A00 0x00000100>;
275 ranges = <0 0 0x30000000 0x10000000
276 1 0 0x21000A00 0x00000100>;
277 };
278
279 kirq0: keystone_irq@26202a0 {
280 compatible = "ti,keystone-irq";
281 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
282 interrupt-controller;
283 #interrupt-cells = <1>;
284 ti,syscon-dev = <&devctrl 0x2a0>;
285 };
286
287 pcie0: pcie@21800000 {
288 compatible = "ti,keystone-pcie", "snps,dw-pcie";
289 clocks = <&clkpcie>;
290 clock-names = "pcie";
291 #address-cells = <3>;
292 #size-cells = <2>;
293 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
294 ranges = <0x81000000 0 0 0x23250000 0 0x4000
295 0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
296
297 status = "disabled";
298 device_type = "pci";
299 num-lanes = <2>;
300
301 #interrupt-cells = <1>;
302 interrupt-map-mask = <0 0 0 7>;
303 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
304 <0 0 0 2 &pcie_intc0 1>, /* INT B */
305 <0 0 0 3 &pcie_intc0 2>, /* INT C */
306 <0 0 0 4 &pcie_intc0 3>; /* INT D */
307
308 pcie_msi_intc0: msi-interrupt-controller {
309 interrupt-controller;
310 #interrupt-cells = <1>;
311 interrupt-parent = <&gic>;
312 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
313 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
314 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
315 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
316 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
317 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
318 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
319 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
320 };
321
322 pcie_intc0: legacy-interrupt-controller {
323 interrupt-controller;
324 #interrupt-cells = <1>;
325 interrupt-parent = <&gic>;
326 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
327 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
328 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
329 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
330 };
331 };
332 };
333};