blob: 71ea408aa5e2e359ee94c84a7ef8c539583bc7b5 [file] [log] [blame]
wdenkbf9e3b32004-02-12 00:47:09 +00001/*
2 * (C) Copyright 2003
3 * Josef Baumgartner <josef.baumgartner@telex.de>
4 *
Heiko Schocher9acb6262006-04-20 08:42:42 +02005 * MCF5282 additionals
6 * (C) Copyright 2005
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
8 *
wdenkbf9e3b32004-02-12 00:47:09 +00009 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <watchdog.h>
30#include <command.h>
TsiChungLiew83ec20b2007-08-15 19:21:21 -050031#include <asm/immap.h>
wdenkbf9e3b32004-02-12 00:47:09 +000032
Zachary P. Landaueacbd312006-01-26 17:35:56 -050033#ifdef CONFIG_M5271
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +010034/*
35 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
36 * determine which one we are running on, based on the Chip Identification
37 * Register (CIR).
38 */
TsiChungLiew83ec20b2007-08-15 19:21:21 -050039int checkcpu(void)
Zachary P. Landaueacbd312006-01-26 17:35:56 -050040{
Marian Balakowiczb75ef852006-05-09 11:45:31 +020041 char buf[32];
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +010042 unsigned short cir; /* Chip Identification Register */
43 unsigned short pin; /* Part identification number */
44 unsigned char prn; /* Part revision number */
45 char *cpu_model;
Marian Balakowiczb75ef852006-05-09 11:45:31 +020046
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +010047 cir = mbar_readShort(MCF_CCM_CIR);
48 pin = cir >> MCF_CCM_CIR_PIN_LEN;
49 prn = cir & MCF_CCM_CIR_PRN_MASK;
50
51 switch (pin) {
52 case MCF_CCM_CIR_PIN_MCF5270:
53 cpu_model = "5270";
54 break;
55 case MCF_CCM_CIR_PIN_MCF5271:
56 cpu_model = "5271";
57 break;
58 default:
59 cpu_model = NULL;
60 break;
61 }
62
63 if (cpu_model)
64 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
TsiChungLiew83ec20b2007-08-15 19:21:21 -050065 cpu_model, prn, strmhz(buf, CFG_CLK));
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +010066 else
67 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
TsiChungLiew83ec20b2007-08-15 19:21:21 -050068 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
69 pin, prn, strmhz(buf, CFG_CLK));
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +010070
Zachary P. Landaueacbd312006-01-26 17:35:56 -050071 return 0;
72}
73
TsiChungLiew83ec20b2007-08-15 19:21:21 -050074int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
75{
Zachary P. Landaueacbd312006-01-26 17:35:56 -050076 mbar_writeByte(MCF_RCM_RCR,
TsiChungLiew83ec20b2007-08-15 19:21:21 -050077 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
Zachary P. Landaueacbd312006-01-26 17:35:56 -050078 return 0;
79};
80
81#if defined(CONFIG_WATCHDOG)
TsiChungLiew83ec20b2007-08-15 19:21:21 -050082void watchdog_reset(void)
Zachary P. Landaueacbd312006-01-26 17:35:56 -050083{
84 mbar_writeShort(MCF_WTM_WSR, 0x5555);
85 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
86}
87
TsiChungLiew83ec20b2007-08-15 19:21:21 -050088int watchdog_disable(void)
Zachary P. Landaueacbd312006-01-26 17:35:56 -050089{
90 mbar_writeShort(MCF_WTM_WCR, 0);
91 return (0);
92}
93
TsiChungLiew83ec20b2007-08-15 19:21:21 -050094int watchdog_init(void)
Zachary P. Landaueacbd312006-01-26 17:35:56 -050095{
Zachary P. Landaueacbd312006-01-26 17:35:56 -050096 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
97 return (0);
98}
TsiChungLiew83ec20b2007-08-15 19:21:21 -050099#endif /* #ifdef CONFIG_WATCHDOG */
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500100
101#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000102
103#ifdef CONFIG_M5272
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500104int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
105{
106 volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdenkbf9e3b32004-02-12 00:47:09 +0000107
108 wdp->wdog_wrrr = 0;
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500109 udelay(1000);
wdenkbf9e3b32004-02-12 00:47:09 +0000110
111 /* enable watchdog, set timeout to 0 and wait */
112 wdp->wdog_wrrr = 1;
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500113 while (1) ;
wdenkbf9e3b32004-02-12 00:47:09 +0000114
115 /* we don't return! */
116 return 0;
117};
118
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500119int checkcpu(void)
120{
121 volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
wdenkbf9e3b32004-02-12 00:47:09 +0000122 uchar msk;
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500123 char *suf;
wdenkbf9e3b32004-02-12 00:47:09 +0000124
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500125 puts("CPU: ");
126 msk = (sysctrl->sc_dir > 28) & 0xf;
wdenkbf9e3b32004-02-12 00:47:09 +0000127 switch (msk) {
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500128 case 0x2:
129 suf = "1K75N";
130 break;
131 case 0x4:
132 suf = "3K75N";
133 break;
134 default:
135 suf = NULL;
136 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
137 break;
138 }
wdenkbf9e3b32004-02-12 00:47:09 +0000139
140 if (suf)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500141 printf("Freescale MCF5272 %s\n", suf);
wdenkbf9e3b32004-02-12 00:47:09 +0000142 return 0;
143};
144
wdenkbf9e3b32004-02-12 00:47:09 +0000145#if defined(CONFIG_WATCHDOG)
146/* Called by macro WATCHDOG_RESET */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500147void watchdog_reset(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000148{
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500149 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
150 wdt->wdog_wcr = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000151}
152
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500153int watchdog_disable(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000154{
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500155 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
wdenkbf9e3b32004-02-12 00:47:09 +0000156
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500157 wdt->wdog_wcr = 0; /* reset watchdog counter */
158 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
159 wdt->wdog_wrrr = 0; /* disable watchdog timer */
wdenkbf9e3b32004-02-12 00:47:09 +0000160
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500161 puts("WATCHDOG:disabled\n");
wdenkbf9e3b32004-02-12 00:47:09 +0000162 return (0);
163}
164
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500165int watchdog_init(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000166{
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500167 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
wdenkbf9e3b32004-02-12 00:47:09 +0000168
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500169 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
wdenkbf9e3b32004-02-12 00:47:09 +0000170
171 /* set timeout and enable watchdog */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500172 wdt->wdog_wrrr =
173 ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
174 wdt->wdog_wcr = 0; /* reset watchdog counter */
wdenkbf9e3b32004-02-12 00:47:09 +0000175
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500176 puts("WATCHDOG:enabled\n");
wdenkbf9e3b32004-02-12 00:47:09 +0000177 return (0);
178}
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500179#endif /* #ifdef CONFIG_WATCHDOG */
wdenkbf9e3b32004-02-12 00:47:09 +0000180
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500181#endif /* #ifdef CONFIG_M5272 */
wdenkbf9e3b32004-02-12 00:47:09 +0000182
183#ifdef CONFIG_M5282
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500184int checkcpu(void)
wdenkbf9e3b32004-02-12 00:47:09 +0000185{
Wolfgang Denk4176c792006-06-10 19:27:47 +0200186 unsigned char resetsource = MCFRESET_RSR;
Heiko Schocher9acb6262006-04-20 08:42:42 +0200187
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500188 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
189 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
190 printf("Reset:%s%s%s%s%s%s%s\n",
191 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
192 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
193 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
194 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
195 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
196 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
197 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
wdenkbf9e3b32004-02-12 00:47:09 +0000198 return 0;
199}
200
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500201int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
Heiko Schocher9acb6262006-04-20 08:42:42 +0200202{
203 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
wdenkbf9e3b32004-02-12 00:47:09 +0000204 return 0;
205};
206#endif
stroese8c725b92004-12-16 18:09:49 +0000207
TsiChungLiewa1436a82007-08-16 13:20:50 -0500208#ifdef CONFIG_M5249
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500209int checkcpu(void)
stroese8c725b92004-12-16 18:09:49 +0000210{
211 char buf[32];
212
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500213 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
214 strmhz(buf, CFG_CLK));
stroese8c725b92004-12-16 18:09:49 +0000215 return 0;
216}
217
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500218int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
219{
stroese8c725b92004-12-16 18:09:49 +0000220 /* enable watchdog, set timeout to 0 and wait */
221 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500222 while (1) ;
stroese8c725b92004-12-16 18:09:49 +0000223
224 /* we don't return! */
225 return 0;
226};
227#endif
TsiChungLiewa1436a82007-08-16 13:20:50 -0500228
229#ifdef CONFIG_M5253
230int checkcpu(void)
231{
232 char buf[32];
233
234 unsigned char resetsource = mbar_readLong(SIM_RSR);
235 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
236 strmhz(buf, CFG_CLK));
237
238 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
239 printf("Reset:%s%s\n",
240 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
241 : "",
242 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
243 "");
244 }
245 return 0;
246}
247
248int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
249{
250 /* enable watchdog, set timeout to 0 and wait */
251 mbar_writeByte(SIM_SYPCR, 0xc0);
252 while (1) ;
253
254 /* we don't return! */
255 return 0;
256};
257#endif