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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a27044b14a9e93678a82d7b35f202b93e7687abc / . / board / amcc / makalu / makalu.c
blob: b7933a056d1be76e198ed4116c7b52b5965a5735 [file] [log] [blame]
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ppc4xx.h>
26#include <ppc405.h>
27#include <libfdt.h>
28#include <asm/processor.h>
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100[diff] [blame]29#include <asm/gpio.h>
30#include <asm/io.h>
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]31
32#if defined(CONFIG_PCI)
33#include <pci.h>
34#include <asm/4xx_pcie.h>
35#endif
36
37DECLARE_GLOBAL_DATA_PTR;
38
39extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
40
41/*
42 * Board early initialization function
43 */
44int board_early_init_f (void)
45{
46 /*--------------------------------------------------------------------+
47 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
48 +--------------------------------------------------------------------+
49 +---------------------------------------------------------------------+
50 |Interrupt| Source | Pol. | Sensi.| Crit. |
51 +---------+-----------------------------------+-------+-------+-------+
52 | IRQ 00 | UART0 | High | Level | Non |
53 | IRQ 01 | UART1 | High | Level | Non |
54 | IRQ 02 | IIC0 | High | Level | Non |
55 | IRQ 03 | TBD | High | Level | Non |
56 | IRQ 04 | TBD | High | Level | Non |
57 | IRQ 05 | EBM | High | Level | Non |
58 | IRQ 06 | BGI | High | Level | Non |
59 | IRQ 07 | IIC1 | Rising| Edge | Non |
60 | IRQ 08 | SPI | High | Lvl/ed| Non |
61 | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
62 | IRQ 10 | MAL TX EOB | High | Level | Non |
63 | IRQ 11 | MAL RX EOB | High | Level | Non |
64 | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
65 | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
66 | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
67 | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
68 | IRQ 16 | PCIE0 AL | high | Level | Non |
69 | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
70 | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
71 | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
72 | IRQ 20 | PCIE0 TCR | High | Level | Non |
73 | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
74 | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
75 | IRQ 23 | Security EIP-94 | High | Level | Non |
76 | IRQ 24 | EMAC0 interrupt | High | Level | Non |
77 | IRQ 25 | EMAC1 interrupt | High | Level | Non |
78 | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
79 | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
80 | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
81 | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
82 | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
83 | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
84 |----------------------------------------------------------------------
85 | IRQ 32 | MAL Serr | High | Level | Non |
86 | IRQ 33 | MAL Txde | High | Level | Non |
87 | IRQ 34 | MAL Rxde | High | Level | Non |
88 | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
89 | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
90 | IRQ 37 | EBC | High |Lvl Edg| Non |
91 | IRQ 38 | NDFC | High | Level | Non |
92 | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
93 | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
94 | IRQ 41 | PCIE1 AL | high | Level | Non |
95 | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
96 | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
97 | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
98 | IRQ 45 | PCIE1 TCR | High | Level | Non |
99 | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
100 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
101 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
102 | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
103 | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
104 | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
105 | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
106 | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
107 | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
108 | IRQ 55 | Serial ROM | High | Level | Non |
109 | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
110 | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
111 | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
112 | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
113 | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
114 | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
115 | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
116 |----------------------------------------------------------------------
117 | IRQ 64 | PE0 AL | High | Level | Non |
118 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
119 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
120 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
121 | IRQ 68 | PE0 TCR | High | Level | Non |
122 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
123 | IRQ 70 | PE0 DCR Error | High | Level | Non |
124 | IRQ 71 | Reserved | N/A | N/A | Non |
125 | IRQ 72 | PE1 AL | High | Level | Non |
126 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
127 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
128 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
129 | IRQ 76 | PE1 TCR | High | Level | Non |
130 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
131 | IRQ 78 | PE1 DCR Error | High | Level | Non |
132 | IRQ 79 | Reserved | N/A | N/A | Non |
133 | IRQ 80 | PE2 AL | High | Level | Non |
134 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
135 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
136 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
137 | IRQ 84 | PE2 TCR | High | Level | Non |
138 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
139 | IRQ 86 | PE2 DCR Error | High | Level | Non |
140 | IRQ 87 | Reserved | N/A | N/A | Non |
141 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
142 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
143 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
144 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
145 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
146 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
147 | IRQ 94 | Reserved | N/A | N/A | Non |
148 | IRQ 95 | Reserved | N/A | N/A | Non |
149 |---------------------------------------------------------------------
150 +---------+-----------------------------------+-------+-------+------*/
151 /*--------------------------------------------------------------------+
152 | Initialise UIC registers. Clear all interrupts. Disable all
153 | interrupts.
154 | Set critical interrupt values. Set interrupt polarities. Set
155 | interrupt trigger levels. Make bit 0 High priority. Clear all
156 | interrupts again.
157 +-------------------------------------------------------------------*/
158
159 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
160 mtdcr (uic2er, 0x00000000); /* disable all interrupts */
161 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
162 mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
163 mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
164 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
165 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
166 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
167
168 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
169 mtdcr (uic1er, 0x00000000); /* disable all interrupts */
170 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
171 mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
172 mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
173 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
174 mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
175 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
176
177 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
178 mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
179 /* Except cascade UIC0 and UIC1 */
180 mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
181 mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
182 mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
183 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
184 mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
185 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
186
187 /*
188 * Note: Some cores are still in reset when the chip starts, so
189 * take them out of reset
190 */
191 mtsdr(SDR0_SRST, 0);
192
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100[diff] [blame]193 /* Reset PCIe slots */
194 gpio_write_bit(CFG_GPIO_PCIE_RST, 0);
195 udelay(100);
196 gpio_write_bit(CFG_GPIO_PCIE_RST, 1);
197
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]198 return 0;
199}
200
201int misc_init_r(void)
202{
203#ifdef CFG_ENV_IS_IN_FLASH
204 /* Monitor protection ON by default */
205 flash_protect(FLAG_PROTECT_SET,
206 -CFG_MONITOR_LEN,
207 0xffffffff,
208 &flash_info[0]);
209#endif
210
211 return 0;
212}
213
214int checkboard (void)
215{
216 char *s = getenv("serial#");
217
218 printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
219
220 if (s != NULL) {
221 puts(", serial# ");
222 puts(s);
223 }
224 putc('\n');
225
226 return (0);
227}
228
229/*************************************************************************
230 * pci_pre_init
231 *
232 * This routine is called just prior to registering the hose and gives
233 * the board the opportunity to check things. Returning a value of zero
234 * indicates that things are bad & PCI initialization should be aborted.
235 *
236 * Different boards may wish to customize the pci controller structure
237 * (add regions, override default access routines, etc) or perform
238 * certain pre-initialization actions.
239 *
240 ************************************************************************/
241#if defined(CONFIG_PCI)
242int pci_pre_init(struct pci_controller * hose )
243{
244 return 0;
245}
246#endif /* defined(CONFIG_PCI) */
247
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]248#ifdef CONFIG_PCI
249static struct pci_controller pcie_hose[2] = {{0},{0}};
250
251void pcie_setup_hoses(int busno)
252{
253 struct pci_controller *hose;
254 int i, bus;
255 int ret = 0;
256 bus = busno;
257 char *env;
258 unsigned int delay;
259
260 for (i = 0; i < 2; i++) {
261
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100[diff] [blame]262 if (is_end_point(i))
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]263 ret = ppc4xx_init_pcie_endport(i);
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100[diff] [blame]264 else
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]265 ret = ppc4xx_init_pcie_rootport(i);
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]266 if (ret) {
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100[diff] [blame]267 printf("PCIE%d: initialization as %s failed\n", i,
268 is_end_point(i) ? "endpoint" : "root-complex");
Stefan Roese211ea912007-10-22 07:34:34 +0200[diff] [blame]269 continue;
270 }
271
272 hose = &pcie_hose[i];
273 hose->first_busno = bus;
274 hose->last_busno = bus;
275 hose->current_busno = bus;
276
277 /* setup mem resource */
278 pci_set_region(hose->regions + 0,
279 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
280 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
281 CFG_PCIE_MEMSIZE,
282 PCI_REGION_MEM);
283 hose->region_count = 1;
284 pci_register_hose(hose);
285
286 if (is_end_point(i)) {
287 ppc4xx_setup_pcie_endpoint(hose, i);
288 /*
289 * Reson for no scanning is endpoint can not generate
290 * upstream configuration accesses.
291 */
292 } else {
293 ppc4xx_setup_pcie_rootpoint(hose, i);
294 env = getenv ("pciscandelay");
295 if (env != NULL) {
296 delay = simple_strtoul(env, NULL, 10);
297 if (delay > 5)
298 printf("Warning, expect noticable delay before "
299 "PCIe scan due to 'pciscandelay' value!\n");
300 mdelay(delay * 1000);
301 }
302
303 /*
304 * Config access can only go down stream
305 */
306 hose->last_busno = pci_hose_scan(hose);
307 bus = hose->last_busno + 1;
308 }
309 }
310}
311#endif
312
313#if defined(CONFIG_POST)
314/*
315 * Returns 1 if keys pressed to start the power-on long-running tests
316 * Called from board_init_f().
317 */
318int post_hotkeys_pressed(void)
319{
320 return 0; /* No hotkeys supported */
321}
322#endif /* CONFIG_POST */
323
324#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
325void ft_board_setup(void *blob, bd_t *bd)
326{
327 u32 val[4];
328 int rc;
329
330 ft_cpu_setup(blob, bd);
331
332 /* Fixup NOR mapping */
333 val[0] = 0; /* chip select number */
334 val[1] = 0; /* always 0 */
335 val[2] = gd->bd->bi_flashstart;
336 val[3] = gd->bd->bi_flashsize;
337 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
338 val, sizeof(val), 1);
339 if (rc)
340 printf("Unable to update property NOR mapping, err=%s\n",
341 fdt_strerror(rc));
342}
343#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */