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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* sdram_init.c - automatic memory sizing */
25
26#include <common.h>
27#include <74xx_7xx.h>
28#include <galileo/memory.h>
29#include <galileo/pci.h>
30#include <galileo/gt64260R.h>
31#include <net.h>
32
33#include "eth.h"
34#include "mpsc.h"
35#include "i2c.h"
36#include "64260.h"
37
Wolfgang Denkd87080b2006-03-31 18:32:53 +020038DECLARE_GLOBAL_DATA_PTR;
39
wdenkc6097192002-11-03 00:24:07 +000040/* #define DEBUG */
41#define MAP_PCI
42
43#ifdef DEBUG
44#define DP(x) x
45#else
46#define DP(x)
47#endif
48
49#define GB (1 << 30)
50
51/* structure to store the relevant information about an sdram bank */
52typedef struct sdram_info {
53 uchar drb_size;
54 uchar registered, ecc;
55 uchar tpar;
56 uchar tras_clocks;
57 uchar burst_len;
58 uchar banks, slot;
wdenkbf9e3b32004-02-12 00:47:09 +000059 int size; /* detected size, not from I2C but from dram_size() */
wdenkc6097192002-11-03 00:24:07 +000060} sdram_info_t;
61
62#ifdef DEBUG
wdenkbf9e3b32004-02-12 00:47:09 +000063void dump_dimm_info (struct sdram_info *d)
wdenkc6097192002-11-03 00:24:07 +000064{
wdenkbf9e3b32004-02-12 00:47:09 +000065 static const char *ecc_legend[] = { "", " Parity", " ECC" };
66
67 printf ("dimm%s %sDRAM: %dMibytes:\n",
68 ecc_legend[d->ecc],
69 d->registered ? "R" : "", (d->size >> 20));
70 printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
71 d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
72 d->banks, d->slot);
wdenkc6097192002-11-03 00:24:07 +000073}
74#endif
75
76static int
wdenkbf9e3b32004-02-12 00:47:09 +000077memory_map_bank (unsigned int bankNo,
78 unsigned int bankBase, unsigned int bankLength)
wdenkc6097192002-11-03 00:24:07 +000079{
80#ifdef DEBUG
81 if (bankLength > 0) {
wdenkbf9e3b32004-02-12 00:47:09 +000082 printf ("mapping bank %d at %08x - %08x\n",
83 bankNo, bankBase, bankBase + bankLength - 1);
wdenkc6097192002-11-03 00:24:07 +000084 } else {
wdenkbf9e3b32004-02-12 00:47:09 +000085 printf ("unmapping bank %d\n", bankNo);
wdenkc6097192002-11-03 00:24:07 +000086 }
87#endif
88
wdenkbf9e3b32004-02-12 00:47:09 +000089 memoryMapBank (bankNo, bankBase, bankLength);
wdenkc6097192002-11-03 00:24:07 +000090
91 return 0;
92}
93
94#ifdef MAP_PCI
95static int
wdenkbf9e3b32004-02-12 00:47:09 +000096memory_map_bank_pci (unsigned int bankNo,
97 unsigned int bankBase, unsigned int bankLength)
wdenkc6097192002-11-03 00:24:07 +000098{
99 PCI_HOST host;
wdenkbf9e3b32004-02-12 00:47:09 +0000100
101 for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
102 const int features =
wdenkc6097192002-11-03 00:24:07 +0000103 PREFETCH_ENABLE |
104 DELAYED_READ_ENABLE |
105 AGGRESSIVE_PREFETCH |
106 READ_LINE_AGGRESSIVE_PREFETCH |
107 READ_MULTI_AGGRESSIVE_PREFETCH |
wdenkbf9e3b32004-02-12 00:47:09 +0000108 MAX_BURST_4 | PCI_NO_SWAP;
wdenkc6097192002-11-03 00:24:07 +0000109
wdenkbf9e3b32004-02-12 00:47:09 +0000110 pciMapMemoryBank (host, bankNo, bankBase, bankLength);
wdenkc6097192002-11-03 00:24:07 +0000111
wdenkbf9e3b32004-02-12 00:47:09 +0000112 pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
113 bankLength);
wdenkc6097192002-11-03 00:24:07 +0000114
wdenkbf9e3b32004-02-12 00:47:09 +0000115 pciSetRegionFeatures (host, bankNo, features, bankBase,
116 bankLength);
wdenkc6097192002-11-03 00:24:07 +0000117 }
118 return 0;
119}
120#endif
121
122/* ------------------------------------------------------------------------- */
123
124/* much of this code is based on (or is) the code in the pip405 port */
125/* thanks go to the authors of said port - Josh */
126
127
128/*
129 * translate ns.ns/10 coding of SPD timing values
130 * into 10 ps unit values
131 */
wdenkbf9e3b32004-02-12 00:47:09 +0000132static inline unsigned short NS10to10PS (unsigned char spd_byte)
wdenkc6097192002-11-03 00:24:07 +0000133{
134 unsigned short ns, ns10;
135
136 /* isolate upper nibble */
137 ns = (spd_byte >> 4) & 0x0F;
138 /* isolate lower nibble */
139 ns10 = (spd_byte & 0x0F);
140
wdenkbf9e3b32004-02-12 00:47:09 +0000141 return (ns * 100 + ns10 * 10);
wdenkc6097192002-11-03 00:24:07 +0000142}
143
144/*
145 * translate ns coding of SPD timing values
146 * into 10 ps unit values
147 */
wdenkbf9e3b32004-02-12 00:47:09 +0000148static inline unsigned short NSto10PS (unsigned char spd_byte)
wdenkc6097192002-11-03 00:24:07 +0000149{
wdenkbf9e3b32004-02-12 00:47:09 +0000150 return (spd_byte * 100);
wdenkc6097192002-11-03 00:24:07 +0000151}
152
153#ifdef CONFIG_ZUMA_V2
wdenkbf9e3b32004-02-12 00:47:09 +0000154static int check_dimm (uchar slot, sdram_info_t * info)
wdenkc6097192002-11-03 00:24:07 +0000155{
wdenk8bde7f72003-06-27 21:31:46 +0000156 /* assume 2 dimms, 2 banks each 256M - we dont have an
wdenkc6097192002-11-03 00:24:07 +0000157 * dimm i2c so rely on the detection routines later */
158
wdenkbf9e3b32004-02-12 00:47:09 +0000159 memset (info, 0, sizeof (*info));
wdenkc6097192002-11-03 00:24:07 +0000160
161 info->slot = slot;
162 info->banks = 2; /* Detect later */
wdenkbf9e3b32004-02-12 00:47:09 +0000163 info->registered = 0;
wdenkc6097192002-11-03 00:24:07 +0000164 info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
165 but doesn't matter, both do same
166 thing in setup_sdram() */
wdenkbf9e3b32004-02-12 00:47:09 +0000167 info->tpar = 3;
168 info->tras_clocks = 5;
169 info->burst_len = 4;
wdenkc6097192002-11-03 00:24:07 +0000170#ifdef CONFIG_ECC
171 info->ecc = 0; /* Detect later */
172#endif /* CONFIG_ECC */
173 return 0;
174}
175
wdenk12f34242003-09-02 22:48:03 +0000176#elif defined(CONFIG_P3G4)
177
wdenkbf9e3b32004-02-12 00:47:09 +0000178static int check_dimm (uchar slot, sdram_info_t * info)
wdenk12f34242003-09-02 22:48:03 +0000179{
wdenkbf9e3b32004-02-12 00:47:09 +0000180 memset (info, 0, sizeof (*info));
wdenk12f34242003-09-02 22:48:03 +0000181
182 if (slot)
183 return 0;
184
185 info->slot = slot;
186 info->banks = 1;
187 info->registered = 0;
188 info->drb_size = 4;
189 info->tpar = 3;
190 info->tras_clocks = 6;
191 info->burst_len = 4;
192#ifdef CONFIG_ECC
193 info->ecc = 2;
194#endif
195 return 0;
196}
197
wdenkbf9e3b32004-02-12 00:47:09 +0000198#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
wdenkc6097192002-11-03 00:24:07 +0000199
200/* This code reads the SPD chip on the sdram and populates
201 * the array which is passed in with the relevant information */
wdenkbf9e3b32004-02-12 00:47:09 +0000202static int check_dimm (uchar slot, sdram_info_t * info)
wdenkc6097192002-11-03 00:24:07 +0000203{
wdenkc6097192002-11-03 00:24:07 +0000204 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
205 int ret;
206 uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
207 ulong tmemclk;
208 uchar trp_clocks, trcd_clocks;
209 uchar data[128];
210
211 get_clocks ();
212
wdenkbf9e3b32004-02-12 00:47:09 +0000213 tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
wdenkc6097192002-11-03 00:24:07 +0000214
215#ifdef CONFIG_EVB64260_750CX
216 if (0 != slot) {
wdenkbf9e3b32004-02-12 00:47:09 +0000217 printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
218 printf (" called with slot=%d insetad!\n", slot);
wdenkc6097192002-11-03 00:24:07 +0000219 return 0;
220 }
221#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000222 DP (puts ("before i2c read\n"));
wdenkc6097192002-11-03 00:24:07 +0000223
wdenkbf9e3b32004-02-12 00:47:09 +0000224 ret = i2c_read (addr, 0, 128, data, 0);
wdenkc6097192002-11-03 00:24:07 +0000225
wdenkbf9e3b32004-02-12 00:47:09 +0000226 DP (puts ("after i2c read\n"));
wdenkc6097192002-11-03 00:24:07 +0000227
228 /* zero all the values */
wdenkbf9e3b32004-02-12 00:47:09 +0000229 memset (info, 0, sizeof (*info));
wdenkc6097192002-11-03 00:24:07 +0000230
231 if (ret) {
wdenkbf9e3b32004-02-12 00:47:09 +0000232 DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
wdenkc6097192002-11-03 00:24:07 +0000233 return 0;
234 }
235
236 /* first, do some sanity checks */
237 if (data[2] != 0x4) {
wdenkbf9e3b32004-02-12 00:47:09 +0000238 printf ("Not SDRAM in slot %d\n", slot);
wdenkc6097192002-11-03 00:24:07 +0000239 return 0;
240 }
241
242 /* get various information */
243 rows = data[3];
244 cols = data[4];
245 info->banks = data[5];
246 sdram_banks = data[17];
247 width = data[13] & 0x7f;
248
wdenkbf9e3b32004-02-12 00:47:09 +0000249 DP (printf
250 ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
wdenkc6097192002-11-03 00:24:07 +0000251
252 /* check if the memory is registered */
253 if (data[21] & (BIT1 | BIT4))
254 info->registered = 1;
255
256#ifdef CONFIG_ECC
257 /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
258 info->ecc = (data[11] & 2) >> 1;
259#endif
260
261 /* bit 1 is CL2, bit 2 is CL3 */
262 supp_cal = (data[18] & 0x6) >> 1;
263
264 /* compute the relevant clock values */
wdenkbf9e3b32004-02-12 00:47:09 +0000265 trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
266 trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
267 info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
wdenkc6097192002-11-03 00:24:07 +0000268
wdenkbf9e3b32004-02-12 00:47:09 +0000269 DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
270 trp_clocks, trcd_clocks, info->tras_clocks));
wdenkc6097192002-11-03 00:24:07 +0000271
272 /* try a CAS latency of 3 first... */
273 cal_val = 0;
274 if (supp_cal & 3) {
wdenkbf9e3b32004-02-12 00:47:09 +0000275 if (NS10to10PS (data[9]) <= tmemclk)
wdenkc6097192002-11-03 00:24:07 +0000276 cal_val = 3;
277 }
278
279 /* then 2... */
280 if (supp_cal & 2) {
wdenkbf9e3b32004-02-12 00:47:09 +0000281 if (NS10to10PS (data[23]) <= tmemclk)
wdenkc6097192002-11-03 00:24:07 +0000282 cal_val = 2;
283 }
284
wdenkbf9e3b32004-02-12 00:47:09 +0000285 DP (printf ("cal_val = %d\n", cal_val));
wdenkc6097192002-11-03 00:24:07 +0000286
287 /* bummer, did't work... */
288 if (cal_val == 0) {
wdenkbf9e3b32004-02-12 00:47:09 +0000289 DP (printf ("Couldn't find a good CAS latency\n"));
wdenkc6097192002-11-03 00:24:07 +0000290 return 0;
291 }
292
293 /* get the largest delay -- these values need to all be the same
294 * see Res#6 */
295 info->tpar = cal_val;
296 if (trp_clocks > info->tpar)
297 info->tpar = trp_clocks;
298 if (trcd_clocks > info->tpar)
299 info->tpar = trcd_clocks;
300
wdenkbf9e3b32004-02-12 00:47:09 +0000301 DP (printf ("tpar set to: %d\n", info->tpar));
wdenkc6097192002-11-03 00:24:07 +0000302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#ifdef CONFIG_SYS_BROKEN_CL2
wdenkbf9e3b32004-02-12 00:47:09 +0000304 if (info->tpar == 2) {
wdenkc6097192002-11-03 00:24:07 +0000305 info->tpar = 3;
wdenkbf9e3b32004-02-12 00:47:09 +0000306 DP (printf ("tpar fixed-up to: %d\n", info->tpar));
wdenkc6097192002-11-03 00:24:07 +0000307 }
308#endif
309 /* compute the module DRB size */
wdenkbf9e3b32004-02-12 00:47:09 +0000310 info->drb_size =
311 (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
wdenkc6097192002-11-03 00:24:07 +0000312
wdenkbf9e3b32004-02-12 00:47:09 +0000313 DP (printf ("drb_size set to: %d\n", info->drb_size));
wdenkc6097192002-11-03 00:24:07 +0000314
315 /* find the burst len */
316 info->burst_len = data[16] & 0xf;
317 if ((info->burst_len & 8) == 8) {
318 info->burst_len = 1;
319 } else if ((info->burst_len & 4) == 4) {
320 info->burst_len = 0;
321 } else {
322 return 0;
323 }
324
325 info->slot = slot;
326 return 0;
327}
328#endif /* ! CONFIG_ZUMA_V2 */
329
wdenkbf9e3b32004-02-12 00:47:09 +0000330static int setup_sdram_common (sdram_info_t info[2])
wdenkc6097192002-11-03 00:24:07 +0000331{
wdenk8bde7f72003-06-27 21:31:46 +0000332 ulong tmp;
wdenkbf9e3b32004-02-12 00:47:09 +0000333 int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;
wdenkc6097192002-11-03 00:24:07 +0000334
wdenkbf9e3b32004-02-12 00:47:09 +0000335 if (!info[0].banks && !info[1].banks)
336 return 0;
wdenkc6097192002-11-03 00:24:07 +0000337
wdenkbf9e3b32004-02-12 00:47:09 +0000338 if (info[0].banks) {
339 if (info[0].tpar > tpar)
340 tpar = info[0].tpar;
341 if (info[0].tras_clocks > tras_clocks)
342 tras_clocks = info[0].tras_clocks;
343 if (!info[0].registered)
344 registered = 0;
wdenk3f85ce22004-02-23 16:11:30 +0000345 if (info[0].ecc != 2)
wdenkbf9e3b32004-02-12 00:47:09 +0000346 ecc = 0;
wdenkc6097192002-11-03 00:24:07 +0000347 }
348
wdenkbf9e3b32004-02-12 00:47:09 +0000349 if (info[1].banks) {
350 if (info[1].tpar > tpar)
351 tpar = info[1].tpar;
352 if (info[1].tras_clocks > tras_clocks)
353 tras_clocks = info[1].tras_clocks;
354 if (!info[1].registered)
355 registered = 0;
356 if (info[1].ecc != 2)
357 ecc = 0;
wdenkc6097192002-11-03 00:24:07 +0000358 }
359
360 /* SDRAM configuration */
wdenkbf9e3b32004-02-12 00:47:09 +0000361 tmp = GTREGREAD (SDRAM_CONFIGURATION);
wdenkc6097192002-11-03 00:24:07 +0000362
363 /* Turn on physical interleave if both DIMMs
364 * have even numbers of banks. */
wdenkbf9e3b32004-02-12 00:47:09 +0000365 if ((info[0].banks == 0 || info[0].banks == 2) &&
366 (info[1].banks == 0 || info[1].banks == 2)) {
367 /* physical interleave on */
368 tmp &= ~(1 << 15);
wdenkc6097192002-11-03 00:24:07 +0000369 } else {
wdenkbf9e3b32004-02-12 00:47:09 +0000370 /* physical interleave off */
371 tmp |= (1 << 15);
wdenkc6097192002-11-03 00:24:07 +0000372 }
373
374 tmp |= (registered << 17);
375
376 /* Use buffer 1 to return read data to the CPU
377 * See Res #12 */
378 tmp |= (1 << 26);
379
wdenkbf9e3b32004-02-12 00:47:09 +0000380 GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
381 DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
wdenkc6097192002-11-03 00:24:07 +0000382
383 /* SDRAM timing */
384 tmp = (((tpar == 3) ? 2 : 1) |
385 (((tpar == 3) ? 2 : 1) << 2) |
wdenkbf9e3b32004-02-12 00:47:09 +0000386 (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
wdenkc6097192002-11-03 00:24:07 +0000387
388#ifdef CONFIG_ECC
389 /* Setup ECC */
wdenkbf9e3b32004-02-12 00:47:09 +0000390 if (ecc == 2)
391 tmp |= 1 << 13;
wdenkc6097192002-11-03 00:24:07 +0000392#endif /* CONFIG_ECC */
393
wdenkbf9e3b32004-02-12 00:47:09 +0000394 GT_REG_WRITE (SDRAM_TIMING, tmp);
395 DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
396 GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
wdenkc6097192002-11-03 00:24:07 +0000397
398 /* SDRAM address decode register */
399 /* program this with the default value */
wdenkbf9e3b32004-02-12 00:47:09 +0000400 GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
401 DP (printf ("SDRAM decode: %08x\n",
402 GTREGREAD (SDRAM_ADDRESS_DECODE)));
wdenkc6097192002-11-03 00:24:07 +0000403
404 return 0;
405}
406
407/* sets up the GT properly with information passed in */
wdenkbf9e3b32004-02-12 00:47:09 +0000408static int setup_sdram (sdram_info_t * info)
wdenkc6097192002-11-03 00:24:07 +0000409{
410 ulong tmp, check;
411 ulong *addr = 0;
412 int i;
413
414 /* sanity checking */
wdenkbf9e3b32004-02-12 00:47:09 +0000415 if (!info->banks)
416 return 0;
wdenkc6097192002-11-03 00:24:07 +0000417
418 /* ---------------------------- */
419 /* Program the GT with the discovered data */
420
421 /* bank parameters */
wdenkbf9e3b32004-02-12 00:47:09 +0000422 tmp = (0xf << 16); /* leave all virt bank pages open */
wdenkc6097192002-11-03 00:24:07 +0000423
wdenkbf9e3b32004-02-12 00:47:09 +0000424 DP (printf ("drb_size: %d\n", info->drb_size));
wdenkc6097192002-11-03 00:24:07 +0000425 switch (info->drb_size) {
426 case 1:
427 tmp |= (1 << 14);
428 break;
429 case 4:
430 case 8:
431 tmp |= (2 << 14);
432 break;
433 case 16:
434 case 32:
435 tmp |= (3 << 14);
436 break;
437 default:
wdenkbf9e3b32004-02-12 00:47:09 +0000438 printf ("Error in dram size calculation\n");
wdenkc6097192002-11-03 00:24:07 +0000439 return 1;
440 }
441
442 /* SDRAM bank parameters */
443 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
wdenkbf9e3b32004-02-12 00:47:09 +0000444 GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
445 GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
446 DP (printf
447 ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
448 info->slot * 2, (info->slot * 2) + 1, tmp));
wdenkc6097192002-11-03 00:24:07 +0000449
450 /* set the SDRAM configuration for each bank */
451 for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
wdenkbf9e3b32004-02-12 00:47:09 +0000452 DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
wdenkc6097192002-11-03 00:24:07 +0000453
454 /* map the bank */
wdenkbf9e3b32004-02-12 00:47:09 +0000455 memory_map_bank (i, 0, GB / 4);
wdenkc6097192002-11-03 00:24:07 +0000456
457 /* set SDRAM mode */
wdenkbf9e3b32004-02-12 00:47:09 +0000458 GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
459 check = GTREGREAD (SDRAM_OPERATION_MODE);
wdenkc6097192002-11-03 00:24:07 +0000460
461 /* dummy write */
462 *addr = 0;
463
464 /* wait for the command to complete */
wdenkbf9e3b32004-02-12 00:47:09 +0000465 while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
wdenkc6097192002-11-03 00:24:07 +0000466
467 /* switch back to normal operation mode */
wdenkbf9e3b32004-02-12 00:47:09 +0000468 GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
469 check = GTREGREAD (SDRAM_OPERATION_MODE);
wdenkc6097192002-11-03 00:24:07 +0000470
471 /* unmap the bank */
wdenkbf9e3b32004-02-12 00:47:09 +0000472 memory_map_bank (i, 0, 0);
473 DP (printf ("*** MRS cycle for bank %d done ***\n", i));
wdenkc6097192002-11-03 00:24:07 +0000474 }
475
476 return 0;
477}
478
479/*
480 * Check memory range for valid RAM. A simple memory test determines
481 * the actually available RAM size between addresses `base' and
482 * `base + maxsize'. Some (not all) hardware errors are detected:
483 * - short between address lines
484 * - short between data lines
485 */
wdenkbf9e3b32004-02-12 00:47:09 +0000486static long int dram_size (long int *base, long int maxsize)
wdenkc6097192002-11-03 00:24:07 +0000487{
wdenkbf9e3b32004-02-12 00:47:09 +0000488 volatile long int *addr, *b = base;
489 long int cnt, val, save1, save2;
wdenkc6097192002-11-03 00:24:07 +0000490
491#define STARTVAL (1<<20) /* start test at 1M */
wdenkbf9e3b32004-02-12 00:47:09 +0000492 for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
493 cnt <<= 1) {
494 addr = base + cnt; /* pointer arith! */
wdenkc6097192002-11-03 00:24:07 +0000495
wdenkbf9e3b32004-02-12 00:47:09 +0000496 save1 = *addr; /* save contents of addr */
497 save2 = *b; /* save contents of base */
wdenkc6097192002-11-03 00:24:07 +0000498
wdenkbf9e3b32004-02-12 00:47:09 +0000499 *addr = cnt; /* write cnt to addr */
500 *b = 0; /* put null at base */
wdenkc6097192002-11-03 00:24:07 +0000501
wdenkbf9e3b32004-02-12 00:47:09 +0000502 /* check at base address */
503 if ((*b) != 0) {
504 *addr = save1; /* restore *addr */
505 *b = save2; /* restore *b */
506 return (0);
507 }
508 val = *addr; /* read *addr */
wdenkc6097192002-11-03 00:24:07 +0000509
wdenkbf9e3b32004-02-12 00:47:09 +0000510 *addr = save1;
511 *b = save2;
wdenkc6097192002-11-03 00:24:07 +0000512
wdenkbf9e3b32004-02-12 00:47:09 +0000513 if (val != cnt) {
514 /* fix boundary condition.. STARTVAL means zero */
515 if (cnt == STARTVAL / sizeof (long))
516 cnt = 0;
517 return (cnt * sizeof (long));
518 }
519 }
520 return maxsize;
wdenkc6097192002-11-03 00:24:07 +0000521}
522
523/* ------------------------------------------------------------------------- */
524
525/* U-Boot interface function to SDRAM init - this is where all the
526 * controlling logic happens */
Becky Bruce9973e3c2008-06-09 16:03:40 -0500527phys_size_t initdram (int board_type)
wdenkc6097192002-11-03 00:24:07 +0000528{
wdenkbf9e3b32004-02-12 00:47:09 +0000529 ulong checkbank[4] = {[0 ... 3] = 0 };
wdenkc6097192002-11-03 00:24:07 +0000530 int bank_no;
wdenk8bde7f72003-06-27 21:31:46 +0000531 ulong total;
wdenkc6097192002-11-03 00:24:07 +0000532 int nhr;
533 sdram_info_t dimm_info[2];
534
535
536 /* first, use the SPD to get info about the SDRAM */
537
538 /* check the NHR bit and skip mem init if it's already done */
wdenkbf9e3b32004-02-12 00:47:09 +0000539 nhr = get_hid0 () & (1 << 16);
wdenkc6097192002-11-03 00:24:07 +0000540
541 if (nhr) {
wdenkbf9e3b32004-02-12 00:47:09 +0000542 printf ("Skipping SDRAM setup due to NHR bit being set\n");
wdenkc6097192002-11-03 00:24:07 +0000543 } else {
544 /* DIMM0 */
wdenkbf9e3b32004-02-12 00:47:09 +0000545 check_dimm (0, &dimm_info[0]);
wdenkc6097192002-11-03 00:24:07 +0000546
547 /* DIMM1 */
wdenkbf9e3b32004-02-12 00:47:09 +0000548#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
549 check_dimm (1, &dimm_info[1]);
550#else /* CONFIG_EVB64260_750CX */
551 memset (&dimm_info[1], 0, sizeof (sdram_info_t));
wdenkc6097192002-11-03 00:24:07 +0000552#endif
553
554 /* unmap all banks */
wdenkbf9e3b32004-02-12 00:47:09 +0000555 memory_map_bank (0, 0, 0);
556 memory_map_bank (1, 0, 0);
557 memory_map_bank (2, 0, 0);
558 memory_map_bank (3, 0, 0);
wdenkc6097192002-11-03 00:24:07 +0000559
560 /* Now, program the GT with the correct values */
wdenkbf9e3b32004-02-12 00:47:09 +0000561 if (setup_sdram_common (dimm_info)) {
562 printf ("Setup common failed.\n");
wdenkc6097192002-11-03 00:24:07 +0000563 }
564
wdenkbf9e3b32004-02-12 00:47:09 +0000565 if (setup_sdram (&dimm_info[0])) {
566 printf ("Setup for DIMM1 failed.\n");
wdenkc6097192002-11-03 00:24:07 +0000567 }
568
wdenkbf9e3b32004-02-12 00:47:09 +0000569 if (setup_sdram (&dimm_info[1])) {
570 printf ("Setup for DIMM2 failed.\n");
wdenkc6097192002-11-03 00:24:07 +0000571 }
572
573 /* set the NHR bit */
wdenkbf9e3b32004-02-12 00:47:09 +0000574 set_hid0 (get_hid0 () | (1 << 16));
wdenkc6097192002-11-03 00:24:07 +0000575 }
576 /* next, size the SDRAM banks */
577
578 total = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000579 if (dimm_info[0].banks > 0)
580 checkbank[0] = 1;
581 if (dimm_info[0].banks > 1)
582 checkbank[1] = 1;
wdenkc6097192002-11-03 00:24:07 +0000583 if (dimm_info[0].banks > 2)
wdenkbf9e3b32004-02-12 00:47:09 +0000584 printf ("Error, SPD claims DIMM1 has >2 banks\n");
wdenkc6097192002-11-03 00:24:07 +0000585
wdenkbf9e3b32004-02-12 00:47:09 +0000586 if (dimm_info[1].banks > 0)
587 checkbank[2] = 1;
588 if (dimm_info[1].banks > 1)
589 checkbank[3] = 1;
wdenkc6097192002-11-03 00:24:07 +0000590 if (dimm_info[1].banks > 2)
wdenkbf9e3b32004-02-12 00:47:09 +0000591 printf ("Error, SPD claims DIMM2 has >2 banks\n");
wdenkc6097192002-11-03 00:24:07 +0000592
593 /* Generic dram sizer: works even if we don't have i2c DIMMs,
594 * as long as the timing settings are more or less correct */
595
596 /*
597 * pass 1: size all the banks, using first bat (0-256M)
wdenkbf9e3b32004-02-12 00:47:09 +0000598 * limitation: we only support 256M per bank due to
599 * us only having 1 BAT for all DRAM
wdenkc6097192002-11-03 00:24:07 +0000600 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200601 for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
wdenkc6097192002-11-03 00:24:07 +0000602 /* skip over banks that are not populated */
wdenkbf9e3b32004-02-12 00:47:09 +0000603 if (!checkbank[bank_no])
wdenkc6097192002-11-03 00:24:07 +0000604 continue;
605
wdenkbf9e3b32004-02-12 00:47:09 +0000606 DP (printf ("checking bank %d\n", bank_no));
wdenkc6097192002-11-03 00:24:07 +0000607
wdenkbf9e3b32004-02-12 00:47:09 +0000608 memory_map_bank (bank_no, 0, GB / 4);
609 checkbank[bank_no] = dram_size (NULL, GB / 4);
610 memory_map_bank (bank_no, 0, 0);
wdenkc6097192002-11-03 00:24:07 +0000611
wdenkbf9e3b32004-02-12 00:47:09 +0000612 DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
wdenkc6097192002-11-03 00:24:07 +0000613 }
614
615 /*
616 * pass 2: contiguously map each bank into physical address
wdenkbf9e3b32004-02-12 00:47:09 +0000617 * space.
wdenkc6097192002-11-03 00:24:07 +0000618 */
wdenkbf9e3b32004-02-12 00:47:09 +0000619 dimm_info[0].banks = dimm_info[1].banks = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620 for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
wdenkbf9e3b32004-02-12 00:47:09 +0000621 if (!checkbank[bank_no])
622 continue;
wdenkc6097192002-11-03 00:24:07 +0000623
wdenkbf9e3b32004-02-12 00:47:09 +0000624 dimm_info[bank_no / 2].banks++;
625 dimm_info[bank_no / 2].size += checkbank[bank_no];
wdenkc6097192002-11-03 00:24:07 +0000626
wdenkbf9e3b32004-02-12 00:47:09 +0000627 memory_map_bank (bank_no, total, checkbank[bank_no]);
wdenkc6097192002-11-03 00:24:07 +0000628#ifdef MAP_PCI
wdenkbf9e3b32004-02-12 00:47:09 +0000629 memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
wdenkc6097192002-11-03 00:24:07 +0000630#endif
631 total += checkbank[bank_no];
632 }
633
634#ifdef CONFIG_ECC
635#ifdef CONFIG_ZUMA_V2
636 /*
637 * We always enable ECC when bank 2 and 3 are unpopulated
638 * If we 2 or 3 are populated, we CAN'T support ECC.
639 * (Zuma boards only support ECC in banks 0 and 1; assume that
640 * in that configuration, ECC chips are mounted, even for stacked
641 * chips)
642 */
wdenkbf9e3b32004-02-12 00:47:09 +0000643 if (checkbank[2] == 0 && checkbank[3] == 0) {
644 dimm_info[0].ecc = 2;
645 GT_REG_WRITE (SDRAM_TIMING,
646 GTREGREAD (SDRAM_TIMING) | (1 << 13));
wdenkc6097192002-11-03 00:24:07 +0000647 /* TODO: do we have to run MRS cycles again? */
648 }
649#endif /* CONFIG_ZUMA_V2 */
650
wdenkbf9e3b32004-02-12 00:47:09 +0000651 if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
652 puts ("[ECC] ");
wdenkc6097192002-11-03 00:24:07 +0000653 }
654#endif /* CONFIG_ECC */
655
656#ifdef DEBUG
wdenkbf9e3b32004-02-12 00:47:09 +0000657 dump_dimm_info (&dimm_info[0]);
658 dump_dimm_info (&dimm_info[1]);
wdenkc6097192002-11-03 00:24:07 +0000659#endif
660 /* TODO: return at MOST 256M? */
wdenk8bde7f72003-06-27 21:31:46 +0000661 /* return total > GB/4 ? GB/4 : total; */
wdenkc6097192002-11-03 00:24:07 +0000662 return total;
663}