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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a2cd50ed6ef0ac6b127b3d6db756979a8336718d / . / cpu / mpc85xx / start.S
blob: 651ff1c02c9cbb04a2ea8bbe2246bde2cfda2e3f [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1/*
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]2 * Copyright 2004, 2007 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]3 * Copyright (C) 2003 Motorola,Inc.
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
25 *
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
28 *
29 */
30
31#include <config.h>
32#include <mpc85xx.h>
33#include <version.h>
34
35#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
36
37#include <ppc_asm.tmpl>
38#include <ppc_defs.h>
39
40#include <asm/cache.h>
41#include <asm/mmu.h>
42
43#ifndef CONFIG_IDENT_STRING
44#define CONFIG_IDENT_STRING ""
45#endif
46
47#undef MSR_KERNEL
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]48#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]49
50/*
51 * Set up GOT: Global Offset Table
52 *
53 * Use r14 to access the GOT
54 */
55 START_GOT
56 GOT_ENTRY(_GOT2_TABLE_)
57 GOT_ENTRY(_FIXUP_TABLE_)
58
59 GOT_ENTRY(_start)
60 GOT_ENTRY(_start_of_vectors)
61 GOT_ENTRY(_end_of_vectors)
62 GOT_ENTRY(transfer_to_handler)
63
64 GOT_ENTRY(__init_end)
65 GOT_ENTRY(_end)
66 GOT_ENTRY(__bss_start)
67 END_GOT
68
69/*
70 * e500 Startup -- after reset only the last 4KB of the effective
71 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
72 * section is located at THIS LAST page and basically does three
73 * things: clear some registers, set up exception tables and
74 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
75 * continue the boot procedure.
76
77 * Once the boot rom is mapped by TLB entries we can proceed
78 * with normal startup.
79 *
80 */
81
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]82 .section .bootpg,"ax"
83 .globl _start_e500
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]84
85_start_e500:
wdenk97d80fc2004-06-09 00:34:46 +0000[diff] [blame]86
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]87/* clear registers/arrays not reset by hardware */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]88
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]89 /* L1 */
90 li r0,2
91 mtspr L1CSR0,r0 /* invalidate d-cache */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]92 mtspr L1CSR1,r0 /* invalidate i-cache */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]93
94 mfspr r1,DBSR
95 mtspr DBSR,r1 /* Clear all valid bits */
96
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]97 /*
98 * Enable L1 Caches early
99 *
100 */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]101
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]102 lis r2,L1CSR0_CPE@H /* enable parity */
103 ori r2,r2,L1CSR0_DCE
104 mtspr L1CSR0,r2 /* enable L1 Dcache */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]105 isync
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]106 mtspr L1CSR1,r2 /* enable L1 Icache */
107 isync
108 msync
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]109
110 /* Setup interrupt vectors */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]111 lis r1,TEXT_BASE@h
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]112 mtspr IVPR,r1
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]113
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]114 li r1,0x0100
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]115 mtspr IVOR0,r1 /* 0: Critical input */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]116 li r1,0x0200
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]117 mtspr IVOR1,r1 /* 1: Machine check */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]118 li r1,0x0300
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]119 mtspr IVOR2,r1 /* 2: Data storage */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]120 li r1,0x0400
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]121 mtspr IVOR3,r1 /* 3: Instruction storage */
122 li r1,0x0500
123 mtspr IVOR4,r1 /* 4: External interrupt */
124 li r1,0x0600
125 mtspr IVOR5,r1 /* 5: Alignment */
126 li r1,0x0700
127 mtspr IVOR6,r1 /* 6: Program check */
128 li r1,0x0800
129 mtspr IVOR7,r1 /* 7: floating point unavailable */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]130 li r1,0x0900
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]131 mtspr IVOR8,r1 /* 8: System call */
132 /* 9: Auxiliary processor unavailable(unsupported) */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]133 li r1,0x0a00
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]134 mtspr IVOR10,r1 /* 10: Decrementer */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]135 li r1,0x0b00
136 mtspr IVOR11,r1 /* 11: Interval timer */
137 li r1,0x0c00
Wolfgang Denk3e0bc442005-08-04 01:24:19 +0200[diff] [blame]138 mtspr IVOR12,r1 /* 12: Watchdog timer */
139 li r1,0x0d00
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]140 mtspr IVOR13,r1 /* 13: Data TLB error */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]141 li r1,0x0e00
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]142 mtspr IVOR14,r1 /* 14: Instruction TLB error */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]143 li r1,0x0f00
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]144 mtspr IVOR15,r1 /* 15: Debug */
145
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]146 /* Clear and set up some registers. */
Kumar Gala87163182008-01-16 22:38:34 -0600[diff] [blame]147 li r0,0x0000
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]148 lis r1,0xffff
149 mtspr DEC,r0 /* prevent dec exceptions */
150 mttbl r0 /* prevent fit & wdt exceptions */
151 mttbu r0
152 mtspr TSR,r1 /* clear all timer exception status */
153 mtspr TCR,r0 /* disable all */
154 mtspr ESR,r0 /* clear exception syndrome register */
155 mtspr MCSR,r0 /* machine check syndrome register */
156 mtxer r0 /* clear integer exception register */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]157
158 /* Enable Time Base and Select Time Base Clock */
wdenk0ac6f8b2004-07-09 23:27:13 +0000[diff] [blame]159 lis r0,HID0_EMCP@h /* Enable machine check */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500[diff] [blame]160#if defined(CONFIG_ENABLE_36BIT_PHYS)
Kumar Gala87163182008-01-16 22:38:34 -0600[diff] [blame]161 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500[diff] [blame]162#endif
Kumar Gala87163182008-01-16 22:38:34 -0600[diff] [blame]163 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]164 mtspr HID0,r0
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]165
Kumar Gala0f060c32008-10-23 01:47:38 -0500[diff] [blame]166#ifndef CONFIG_E500MC
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]167 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]168 mtspr HID1,r0
Kumar Gala0f060c32008-10-23 01:47:38 -0500[diff] [blame]169#endif
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]170
171 /* Enable Branch Prediction */
172#if defined(CONFIG_BTB)
173 li r0,0x201 /* BBFI = 1, BPEN = 1 */
174 mtspr BUCSR,r0
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]175#endif
176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]177#if defined(CONFIG_SYS_INIT_DBCR)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]178 lis r1,0xffff
179 ori r1,r1,0xffff
wdenk0ac6f8b2004-07-09 23:27:13 +0000[diff] [blame]180 mtspr DBSR,r1 /* Clear all status bits */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]181 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
182 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
wdenk0ac6f8b2004-07-09 23:27:13 +0000[diff] [blame]183 mtspr DBCR0,r0
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]184#endif
185
Kumar Gala87163182008-01-16 22:38:34 -0600[diff] [blame]186 /* create a temp mapping in AS=1 to the boot window */
187 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
188 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
189
190 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h
191 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l
192
Andrew Klossner24ef76f2008-07-02 07:03:53 -0700[diff] [blame]193 /* Align the mapping to 16MB */
194 lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h
195 ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l
Kumar Gala87163182008-01-16 22:38:34 -0600[diff] [blame]196
Andrew Klossner24ef76f2008-07-02 07:03:53 -0700[diff] [blame]197 lis r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
198 ori r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
Kumar Gala87163182008-01-16 22:38:34 -0600[diff] [blame]199
200 mtspr MAS0,r6
201 mtspr MAS1,r7
202 mtspr MAS2,r8
203 mtspr MAS3,r9
204 isync
205 msync
206 tlbwe
207
208 /* create a temp mapping in AS=1 to the stack */
209 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
210 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
211
212 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
213 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]215 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
216 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
Kumar Gala87163182008-01-16 22:38:34 -0600[diff] [blame]217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]218 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
219 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
Kumar Gala87163182008-01-16 22:38:34 -0600[diff] [blame]220
221 mtspr MAS0,r6
222 mtspr MAS1,r7
223 mtspr MAS2,r8
224 mtspr MAS3,r9
225 isync
226 msync
227 tlbwe
228
229 lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h
230 ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l
231 lis r7,switch_as@h
232 ori r7,r7,switch_as@l
233
234 mtspr SPRN_SRR0,r7
235 mtspr SPRN_SRR1,r6
236 rfi
237
238switch_as:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]239/* L1 DCache is used for initial RAM */
240
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]241 /* Allocate Initial RAM in data cache.
242 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]243 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
244 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
Kumar Galab009f3e2008-01-08 01:22:21 -0600[diff] [blame]245 mfspr r2, L1CFG0
246 andi. r2, r2, 0x1ff
247 /* cache size * 1024 / (2 * L1 line size) */
248 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]249 mtctr r2
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]250 li r0,0
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]2511:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]252 dcbz r0,r3
253 dcbtls 0,r0,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]254 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]255 bdnz 1b
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]256
Kumar Gala3db0bef2007-08-07 18:07:27 -0500[diff] [blame]257 /* Jump out the last 4K page and continue to 'normal' start */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]258#ifdef CONFIG_SYS_RAMBOOT
Kumar Gala3db0bef2007-08-07 18:07:27 -0500[diff] [blame]259 b _start_cont
260#else
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]261 /* Calculate absolute address in FLASH and jump there */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]262 /*--------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]263 lis r3,CONFIG_SYS_MONITOR_BASE@h
264 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
Kumar Gala3db0bef2007-08-07 18:07:27 -0500[diff] [blame]265 addi r3,r3,_start_cont - _start + _START_OFFSET
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]266 mtlr r3
urwithsughosh@gmail.com1e701e72007-09-24 13:36:01 -0400[diff] [blame]267 blr
Kumar Gala3db0bef2007-08-07 18:07:27 -0500[diff] [blame]268#endif
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]269
Kumar Gala3db0bef2007-08-07 18:07:27 -0500[diff] [blame]270 .text
271 .globl _start
272_start:
273 .long 0x27051956 /* U-BOOT Magic Number */
274 .globl version_string
275version_string:
276 .ascii U_BOOT_VERSION
277 .ascii " (", __DATE__, " - ", __TIME__, ")"
278 .ascii CONFIG_IDENT_STRING, "\0"
279
280 .align 4
281 .globl _start_cont
282_start_cont:
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]283 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]284 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
285 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]286
287 li r0,0
288 stwu r0,-4(r1)
289 stwu r0,-4(r1) /* Terminate call chain */
290
291 stwu r1,-8(r1) /* Save back chain and move SP */
292 lis r0,RESET_VECTOR@h /* Address of reset vector */
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]293 ori r0,r0,RESET_VECTOR@l
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]294 stwu r1,-8(r1) /* Save back chain and move SP */
295 stw r0,+12(r1) /* Save return addr (underflow vect) */
296
297 GET_GOT
Kumar Gala87163182008-01-16 22:38:34 -0600[diff] [blame]298 bl cpu_init_early_f
299
300 /* switch back to AS = 0 */
301 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
302 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
303 mtmsr r3
304 isync
305
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]306 bl cpu_init_f
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]307 bl board_init_f
wdenk0ac6f8b2004-07-09 23:27:13 +0000[diff] [blame]308 isync
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]309
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]310 . = EXC_OFF_SYS_RESET
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]311 .globl _start_of_vectors
312_start_of_vectors:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]313
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]314/* Critical input. */
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]315 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
316
317/* Machine check */
318 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]319
320/* Data Storage exception. */
321 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
322
323/* Instruction Storage exception. */
324 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
325
326/* External Interrupt exception. */
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]327 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]328
329/* Alignment exception. */
330 . = 0x0600
331Alignment:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200[diff] [blame]332 EXCEPTION_PROLOG(SRR0, SRR1)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]333 mfspr r4,DAR
334 stw r4,_DAR(r21)
335 mfspr r5,DSISR
336 stw r5,_DSISR(r21)
337 addi r3,r1,STACK_FRAME_OVERHEAD
338 li r20,MSR_KERNEL
339 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
340 lwz r6,GOT(transfer_to_handler)
341 mtlr r6
342 blrl
343.L_Alignment:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]344 .long AlignmentException - _start + _START_OFFSET
345 .long int_return - _start + _START_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]346
347/* Program check exception */
348 . = 0x0700
349ProgramCheck:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200[diff] [blame]350 EXCEPTION_PROLOG(SRR0, SRR1)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]351 addi r3,r1,STACK_FRAME_OVERHEAD
352 li r20,MSR_KERNEL
353 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
354 lwz r6,GOT(transfer_to_handler)
355 mtlr r6
356 blrl
357.L_ProgramCheck:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]358 .long ProgramCheckException - _start + _START_OFFSET
359 .long int_return - _start + _START_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]360
361 /* No FPU on MPC85xx. This exception is not supposed to happen.
362 */
363 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]364
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]365 . = 0x0900
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]366/*
367 * r0 - SYSCALL number
368 * r3-... arguments
369 */
370SystemCall:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]371 addis r11,r0,0 /* get functions table addr */
372 ori r11,r11,0 /* Note: this code is patched in trap_init */
373 addis r12,r0,0 /* get number of functions */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]374 ori r12,r12,0
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]375
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]376 cmplw 0,r0,r12
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]377 bge 1f
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]378
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]379 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]380 add r11,r11,r0
381 lwz r11,0(r11)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]382
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]383 li r20,0xd00-4 /* Get stack pointer */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]384 lwz r12,0(r20)
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]385 subi r12,r12,12 /* Adjust stack pointer */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]386 li r0,0xc00+_end_back-SystemCall
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]387 cmplw 0,r0,r12 /* Check stack overflow */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]388 bgt 1f
389 stw r12,0(r20)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]390
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]391 mflr r0
392 stw r0,0(r12)
393 mfspr r0,SRR0
394 stw r0,4(r12)
395 mfspr r0,SRR1
396 stw r0,8(r12)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]397
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]398 li r12,0xc00+_back-SystemCall
399 mtlr r12
400 mtspr SRR0,r11
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]401
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]4021: SYNC
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]403 rfi
404_back:
405
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]406 mfmsr r11 /* Disable interrupts */
407 li r12,0
408 ori r12,r12,MSR_EE
409 andc r11,r11,r12
410 SYNC /* Some chip revs need this... */
411 mtmsr r11
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]412 SYNC
413
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]414 li r12,0xd00-4 /* restore regs */
415 lwz r12,0(r12)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]416
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]417 lwz r11,0(r12)
418 mtlr r11
419 lwz r11,4(r12)
420 mtspr SRR0,r11
421 lwz r11,8(r12)
422 mtspr SRR1,r11
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]423
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]424 addi r12,r12,12 /* Adjust stack pointer */
425 li r20,0xd00-4
426 stw r12,0(r20)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]427
428 SYNC
429 rfi
430_end_back:
431
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]432 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
433 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
434 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]435
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]436 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
437 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]438
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]439 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]440
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]441 .globl _end_of_vectors
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]442_end_of_vectors:
443
444
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]445 . = . + (0x100 - ( . & 0xff )) /* align for debug */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]446
447/*
448 * This code finishes saving the registers to the exception frame
449 * and jumps to the appropriate handler for the exception.
450 * Register r21 is pointer into trap frame, r1 has new stack pointer.
451 */
452 .globl transfer_to_handler
453transfer_to_handler:
454 stw r22,_NIP(r21)
455 lis r22,MSR_POW@h
456 andc r23,r23,r22
457 stw r23,_MSR(r21)
458 SAVE_GPR(7, r21)
459 SAVE_4GPRS(8, r21)
460 SAVE_8GPRS(12, r21)
461 SAVE_8GPRS(24, r21)
462
463 mflr r23
464 andi. r24,r23,0x3f00 /* get vector offset */
465 stw r24,TRAP(r21)
466 li r22,0
467 stw r22,RESULT(r21)
468 mtspr SPRG2,r22 /* r1 is now kernel sp */
469
470 lwz r24,0(r23) /* virtual address of handler */
471 lwz r23,4(r23) /* where to go when done */
472 mtspr SRR0,r24
473 mtspr SRR1,r20
474 mtlr r23
475 SYNC
476 rfi /* jump to handler, enable MMU */
477
478int_return:
479 mfmsr r28 /* Disable interrupts */
480 li r4,0
481 ori r4,r4,MSR_EE
482 andc r28,r28,r4
483 SYNC /* Some chip revs need this... */
484 mtmsr r28
485 SYNC
486 lwz r2,_CTR(r1)
487 lwz r0,_LINK(r1)
488 mtctr r2
489 mtlr r0
490 lwz r2,_XER(r1)
491 lwz r0,_CCR(r1)
492 mtspr XER,r2
493 mtcrf 0xFF,r0
494 REST_10GPRS(3, r1)
495 REST_10GPRS(13, r1)
496 REST_8GPRS(23, r1)
497 REST_GPR(31, r1)
498 lwz r2,_NIP(r1) /* Restore environment */
499 lwz r0,_MSR(r1)
500 mtspr SRR0,r2
501 mtspr SRR1,r0
502 lwz r0,GPR0(r1)
503 lwz r2,GPR2(r1)
504 lwz r1,GPR1(r1)
505 SYNC
506 rfi
507
508crit_return:
509 mfmsr r28 /* Disable interrupts */
510 li r4,0
511 ori r4,r4,MSR_EE
512 andc r28,r28,r4
513 SYNC /* Some chip revs need this... */
514 mtmsr r28
515 SYNC
516 lwz r2,_CTR(r1)
517 lwz r0,_LINK(r1)
518 mtctr r2
519 mtlr r0
520 lwz r2,_XER(r1)
521 lwz r0,_CCR(r1)
522 mtspr XER,r2
523 mtcrf 0xFF,r0
524 REST_10GPRS(3, r1)
525 REST_10GPRS(13, r1)
526 REST_8GPRS(23, r1)
527 REST_GPR(31, r1)
528 lwz r2,_NIP(r1) /* Restore environment */
529 lwz r0,_MSR(r1)
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]530 mtspr SPRN_CSRR0,r2
531 mtspr SPRN_CSRR1,r0
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]532 lwz r0,GPR0(r1)
533 lwz r2,GPR2(r1)
534 lwz r1,GPR1(r1)
535 SYNC
536 rfci
537
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]538mck_return:
539 mfmsr r28 /* Disable interrupts */
540 li r4,0
541 ori r4,r4,MSR_EE
542 andc r28,r28,r4
543 SYNC /* Some chip revs need this... */
544 mtmsr r28
545 SYNC
546 lwz r2,_CTR(r1)
547 lwz r0,_LINK(r1)
548 mtctr r2
549 mtlr r0
550 lwz r2,_XER(r1)
551 lwz r0,_CCR(r1)
552 mtspr XER,r2
553 mtcrf 0xFF,r0
554 REST_10GPRS(3, r1)
555 REST_10GPRS(13, r1)
556 REST_8GPRS(23, r1)
557 REST_GPR(31, r1)
558 lwz r2,_NIP(r1) /* Restore environment */
559 lwz r0,_MSR(r1)
560 mtspr SPRN_MCSRR0,r2
561 mtspr SPRN_MCSRR1,r0
562 lwz r0,GPR0(r1)
563 lwz r2,GPR2(r1)
564 lwz r1,GPR1(r1)
565 SYNC
566 rfmci
567
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]568/* Cache functions.
569*/
Kumar Gala54e091d2008-09-22 14:11:10 -0500[diff] [blame]570.globl invalidate_icache
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]571invalidate_icache:
572 mfspr r0,L1CSR1
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]573 ori r0,r0,L1CSR1_ICFI
574 msync
575 isync
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]576 mtspr L1CSR1,r0
577 isync
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]578 blr /* entire I cache */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]579
Kumar Gala54e091d2008-09-22 14:11:10 -0500[diff] [blame]580.globl invalidate_dcache
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]581invalidate_dcache:
582 mfspr r0,L1CSR0
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]583 ori r0,r0,L1CSR0_DCFI
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]584 msync
585 isync
586 mtspr L1CSR0,r0
587 isync
588 blr
589
590 .globl icache_enable
591icache_enable:
592 mflr r8
593 bl invalidate_icache
594 mtlr r8
595 isync
596 mfspr r4,L1CSR1
597 ori r4,r4,0x0001
598 oris r4,r4,0x0001
599 mtspr L1CSR1,r4
600 isync
601 blr
602
603 .globl icache_disable
604icache_disable:
605 mfspr r0,L1CSR1
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]606 lis r3,0
607 ori r3,r3,L1CSR1_ICE
608 andc r0,r0,r3
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]609 mtspr L1CSR1,r0
610 isync
611 blr
612
613 .globl icache_status
614icache_status:
615 mfspr r3,L1CSR1
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]616 andi. r3,r3,L1CSR1_ICE
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]617 blr
618
619 .globl dcache_enable
620dcache_enable:
621 mflr r8
622 bl invalidate_dcache
623 mtlr r8
624 isync
625 mfspr r0,L1CSR0
626 ori r0,r0,0x0001
627 oris r0,r0,0x0001
628 msync
629 isync
630 mtspr L1CSR0,r0
631 isync
632 blr
633
634 .globl dcache_disable
635dcache_disable:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]636 mfspr r3,L1CSR0
637 lis r4,0
638 ori r4,r4,L1CSR0_DCE
639 andc r3,r3,r4
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]640 mtspr L1CSR0,r0
641 isync
642 blr
643
644 .globl dcache_status
645dcache_status:
646 mfspr r3,L1CSR0
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]647 andi. r3,r3,L1CSR0_DCE
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]648 blr
649
650 .globl get_pir
651get_pir:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]652 mfspr r3,PIR
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]653 blr
654
655 .globl get_pvr
656get_pvr:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]657 mfspr r3,PVR
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]658 blr
659
wdenk97d80fc2004-06-09 00:34:46 +0000[diff] [blame]660 .globl get_svr
661get_svr:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]662 mfspr r3,SVR
wdenk97d80fc2004-06-09 00:34:46 +0000[diff] [blame]663 blr
664
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]665 .globl wr_tcr
666wr_tcr:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]667 mtspr TCR,r3
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]668 blr
669
670/*------------------------------------------------------------------------------- */
671/* Function: in8 */
672/* Description: Input 8 bits */
673/*------------------------------------------------------------------------------- */
674 .globl in8
675in8:
676 lbz r3,0x0000(r3)
677 blr
678
679/*------------------------------------------------------------------------------- */
680/* Function: out8 */
681/* Description: Output 8 bits */
682/*------------------------------------------------------------------------------- */
683 .globl out8
684out8:
685 stb r4,0x0000(r3)
Ed Swarthout1487adb2007-09-26 16:35:54 -0500[diff] [blame]686 sync
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]687 blr
688
689/*------------------------------------------------------------------------------- */
690/* Function: out16 */
691/* Description: Output 16 bits */
692/*------------------------------------------------------------------------------- */
693 .globl out16
694out16:
695 sth r4,0x0000(r3)
Ed Swarthout1487adb2007-09-26 16:35:54 -0500[diff] [blame]696 sync
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]697 blr
698
699/*------------------------------------------------------------------------------- */
700/* Function: out16r */
701/* Description: Byte reverse and output 16 bits */
702/*------------------------------------------------------------------------------- */
703 .globl out16r
704out16r:
705 sthbrx r4,r0,r3
Ed Swarthout1487adb2007-09-26 16:35:54 -0500[diff] [blame]706 sync
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]707 blr
708
709/*------------------------------------------------------------------------------- */
710/* Function: out32 */
711/* Description: Output 32 bits */
712/*------------------------------------------------------------------------------- */
713 .globl out32
714out32:
715 stw r4,0x0000(r3)
Ed Swarthout1487adb2007-09-26 16:35:54 -0500[diff] [blame]716 sync
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]717 blr
718
719/*------------------------------------------------------------------------------- */
720/* Function: out32r */
721/* Description: Byte reverse and output 32 bits */
722/*------------------------------------------------------------------------------- */
723 .globl out32r
724out32r:
725 stwbrx r4,r0,r3
Ed Swarthout1487adb2007-09-26 16:35:54 -0500[diff] [blame]726 sync
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]727 blr
728
729/*------------------------------------------------------------------------------- */
730/* Function: in16 */
731/* Description: Input 16 bits */
732/*------------------------------------------------------------------------------- */
733 .globl in16
734in16:
735 lhz r3,0x0000(r3)
736 blr
737
738/*------------------------------------------------------------------------------- */
739/* Function: in16r */
740/* Description: Input 16 bits and byte reverse */
741/*------------------------------------------------------------------------------- */
742 .globl in16r
743in16r:
744 lhbrx r3,r0,r3
745 blr
746
747/*------------------------------------------------------------------------------- */
748/* Function: in32 */
749/* Description: Input 32 bits */
750/*------------------------------------------------------------------------------- */
751 .globl in32
752in32:
753 lwz 3,0x0000(3)
754 blr
755
756/*------------------------------------------------------------------------------- */
757/* Function: in32r */
758/* Description: Input 32 bits and byte reverse */
759/*------------------------------------------------------------------------------- */
760 .globl in32r
761in32r:
762 lwbrx r3,r0,r3
763 blr
764
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]765/*------------------------------------------------------------------------------*/
766
767/*
768 * void relocate_code (addr_sp, gd, addr_moni)
769 *
770 * This "function" does not return, instead it continues in RAM
771 * after relocating the monitor code.
772 *
773 * r3 = dest
774 * r4 = src
775 * r5 = length in bytes
776 * r6 = cachelinesize
777 */
778 .globl relocate_code
779relocate_code:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]780 mr r1,r3 /* Set new stack pointer */
781 mr r9,r4 /* Save copy of Init Data pointer */
782 mr r10,r5 /* Save copy of Destination Address */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]783
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]784 mr r3,r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]785 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
786 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]787 lwz r5,GOT(__init_end)
788 sub r5,r5,r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]789 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]790
791 /*
792 * Fix GOT pointer:
793 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]794 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]795 *
796 * Offset:
797 */
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]798 sub r15,r10,r4
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]799
800 /* First our own GOT */
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]801 add r14,r14,r15
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]802 /* the the one used by the C code */
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]803 add r30,r30,r15
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]804
805 /*
806 * Now relocate code
807 */
808
809 cmplw cr1,r3,r4
810 addi r0,r5,3
811 srwi. r0,r0,2
812 beq cr1,4f /* In place copy is not necessary */
813 beq 7f /* Protect against 0 count */
814 mtctr r0
815 bge cr1,2f
816
817 la r8,-4(r4)
818 la r7,-4(r3)
8191: lwzu r0,4(r8)
820 stwu r0,4(r7)
821 bdnz 1b
822 b 4f
823
8242: slwi r0,r0,2
825 add r8,r4,r0
826 add r7,r3,r0
8273: lwzu r0,-4(r8)
828 stwu r0,-4(r7)
829 bdnz 3b
830
831/*
832 * Now flush the cache: note that we must start from a cache aligned
833 * address. Otherwise we might miss one cache line.
834 */
8354: cmpwi r6,0
836 add r5,r3,r5
837 beq 7f /* Always flush prefetch queue in any case */
838 subi r0,r6,1
839 andc r3,r3,r0
840 mr r4,r3
8415: dcbst 0,r4
842 add r4,r4,r6
843 cmplw r4,r5
844 blt 5b
845 sync /* Wait for all dcbst to complete on bus */
846 mr r4,r3
8476: icbi 0,r4
848 add r4,r4,r6
849 cmplw r4,r5
850 blt 6b
8517: sync /* Wait for all icbi to complete on bus */
852 isync
853
Wolfgang Denk7d314992005-10-05 00:00:54 +0200[diff] [blame]854 /*
855 * Re-point the IVPR at RAM
856 */
857 mtspr IVPR,r10
Wolfgang Denk99b0d282005-10-05 00:19:34 +0200[diff] [blame]858
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]859/*
860 * We are done. Do not return, instead branch to second part of board
861 * initialization, now running from RAM.
862 */
863
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]864 addi r0,r10,in_ram - _start + _START_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]865 mtlr r0
866 blr /* NEVER RETURNS! */
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]867 .globl in_ram
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]868in_ram:
869
870 /*
871 * Relocation Function, r14 point to got2+0x8000
872 *
873 * Adjust got2 pointers, no need to check for 0, this code
874 * already puts a few entries in the table.
875 */
876 li r0,__got2_entries@sectoff@l
877 la r3,GOT(_GOT2_TABLE_)
878 lwz r11,GOT(_GOT2_TABLE_)
879 mtctr r0
880 sub r11,r3,r11
881 addi r3,r3,-4
8821: lwzu r0,4(r3)
883 add r0,r0,r11
884 stw r0,0(r3)
885 bdnz 1b
886
887 /*
888 * Now adjust the fixups and the pointers to the fixups
889 * in case we need to move ourselves again.
890 */
8912: li r0,__fixup_entries@sectoff@l
892 lwz r3,GOT(_FIXUP_TABLE_)
893 cmpwi r0,0
894 mtctr r0
895 addi r3,r3,-4
896 beq 4f
8973: lwzu r4,4(r3)
898 lwzux r0,r4,r11
899 add r0,r0,r11
900 stw r10,0(r3)
901 stw r0,0(r4)
902 bdnz 3b
9034:
904clear_bss:
905 /*
906 * Now clear BSS segment
907 */
908 lwz r3,GOT(__bss_start)
909 lwz r4,GOT(_end)
910
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]911 cmplw 0,r3,r4
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]912 beq 6f
913
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]914 li r0,0
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]9155:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]916 stw r0,0(r3)
917 addi r3,r3,4
918 cmplw 0,r3,r4
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]919 bne 5b
9206:
921
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]922 mr r3,r9 /* Init Data pointer */
923 mr r4,r10 /* Destination Address */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]924 bl board_init_r
925
926 /*
927 * Copy exception vector code to low memory
928 *
929 * r3: dest_addr
930 * r7: source address, r8: end address, r9: target address
931 */
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]932 .globl trap_init
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]933trap_init:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]934 lwz r7,GOT(_start_of_vectors)
935 lwz r8,GOT(_end_of_vectors)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]936
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]937 li r9,0x100 /* reset vector always at 0x100 */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]938
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]939 cmplw 0,r7,r8
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]940 bgelr /* return if r7>=r8 - just in case */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]941
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]942 mflr r4 /* save link register */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]9431:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]944 lwz r0,0(r7)
945 stw r0,0(r9)
946 addi r7,r7,4
947 addi r9,r9,4
948 cmplw 0,r7,r8
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]949 bne 1b
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]950
951 /*
952 * relocate `hdlr' and `int_return' entries
953 */
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]954 li r7,.L_CriticalInput - _start + _START_OFFSET
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]955 bl trap_reloc
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]956 li r7,.L_MachineCheck - _start + _START_OFFSET
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]957 bl trap_reloc
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]958 li r7,.L_DataStorage - _start + _START_OFFSET
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]959 bl trap_reloc
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]960 li r7,.L_InstStorage - _start + _START_OFFSET
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]961 bl trap_reloc
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]962 li r7,.L_ExtInterrupt - _start + _START_OFFSET
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]963 bl trap_reloc
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]964 li r7,.L_Alignment - _start + _START_OFFSET
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]965 bl trap_reloc
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]966 li r7,.L_ProgramCheck - _start + _START_OFFSET
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]967 bl trap_reloc
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]968 li r7,.L_FPUnavailable - _start + _START_OFFSET
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]969 bl trap_reloc
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]970 li r7,.L_Decrementer - _start + _START_OFFSET
971 bl trap_reloc
972 li r7,.L_IntervalTimer - _start + _START_OFFSET
973 li r8,_end_of_vectors - _start + _START_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]9742:
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]975 bl trap_reloc
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]976 addi r7,r7,0x100 /* next exception vector */
977 cmplw 0,r7,r8
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]978 blt 2b
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]979
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]980 lis r7,0x0
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]981 mtspr IVPR,r7
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]982
wdenk343117b2005-05-13 22:49:36 +0000[diff] [blame]983 mtlr r4 /* restore link register */
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]984 blr
985
986 /*
987 * Function: relocate entries for one exception vector
988 */
989trap_reloc:
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]990 lwz r0,0(r7) /* hdlr ... */
991 add r0,r0,r3 /* ... += dest_addr */
992 stw r0,0(r7)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]993
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]994 lwz r0,4(r7) /* int_return ... */
995 add r0,r0,r3 /* ... += dest_addr */
996 stw r0,4(r7)
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]997
998 blr
999
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1000.globl unlock_ram_in_cache
1001unlock_ram_in_cache:
1002 /* invalidate the INIT_RAM section */
Kumar Galaa38a5b62008-10-23 01:47:37 -0500[diff] [blame]1003 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1004 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
Kumar Galab009f3e2008-01-08 01:22:21 -0600[diff] [blame]1005 mfspr r4,L1CFG0
1006 andi. r4,r4,0x1ff
1007 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
Andy Fleming61a21e92007-08-14 01:34:21 -0500[diff] [blame]1008 mtctr r4
Kumar Gala2b22fa42008-02-27 16:30:47 -0600[diff] [blame]10091: dcbi r0,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]1010 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1011 bdnz 1b
Kumar Gala2b22fa42008-02-27 16:30:47 -0600[diff] [blame]1012 sync
Andy Fleming21fae8b2008-02-27 14:29:58 -0600[diff] [blame]1013
1014 /* Invalidate the TLB entries for the cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]1015 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1016 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
Andy Fleming21fae8b2008-02-27 14:29:58 -0600[diff] [blame]1017 tlbivax 0,r3
1018 addi r3,r3,0x1000
1019 tlbivax 0,r3
1020 addi r3,r3,0x1000
1021 tlbivax 0,r3
1022 addi r3,r3,0x1000
1023 tlbivax 0,r3
wdenk42d1f032003-10-15 23:53:47 +0000[diff] [blame]1024 isync
1025 blr
Kumar Gala54e091d2008-09-22 14:11:10 -0500[diff] [blame]1026
1027.globl flush_dcache
1028flush_dcache:
1029 mfspr r3,SPRN_L1CFG0
1030
1031 rlwinm r5,r3,9,3 /* Extract cache block size */
1032 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1033 * are currently defined.
1034 */
1035 li r4,32
1036 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1037 * log2(number of ways)
1038 */
1039 slw r5,r4,r5 /* r5 = cache block size */
1040
1041 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1042 mulli r7,r7,13 /* An 8-way cache will require 13
1043 * loads per set.
1044 */
1045 slw r7,r7,r6
1046
1047 /* save off HID0 and set DCFA */
1048 mfspr r8,SPRN_HID0
1049 ori r9,r8,HID0_DCFA@l
1050 mtspr SPRN_HID0,r9
1051 isync
1052
1053 lis r4,0
1054 mtctr r7
1055
10561: lwz r3,0(r4) /* Load... */
1057 add r4,r4,r5
1058 bdnz 1b
1059
1060 msync
1061 lis r4,0
1062 mtctr r7
1063
10641: dcbf 0,r4 /* ...and flush. */
1065 add r4,r4,r5
1066 bdnz 1b
1067
1068 /* restore HID0 */
1069 mtspr SPRN_HID0,r8
1070 isync
1071
1072 blr