| Frank Wunderlich | 38bff32 | 2020-08-13 10:20:47 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * MTK SATA platform driver |
| 4 | * |
| 5 | * (C) Copyright 2020 |
| 6 | * Mediatek |
| 7 | * |
| 8 | * Author: Frank Wunderlich <frank-w@public-files.de> |
| 9 | * based on https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci_mtk.c |
| 10 | * Author: Ryder Lee <ryder.lee@mediatek.com> |
| 11 | */ |
| 12 | |
| 13 | #include <common.h> |
| 14 | #include <ahci.h> |
| 15 | #include <asm/io.h> |
| 16 | #include <dm.h> |
| 17 | #include <dm/of_access.h> |
| 18 | #include <generic-phy.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <regmap.h> |
| 21 | #include <reset.h> |
| 22 | #include <sata.h> |
| 23 | #include <scsi.h> |
| 24 | #include <syscon.h> |
| 25 | |
| 26 | #define SYS_CFG 0x14 |
| 27 | #define SYS_CFG_SATA_MSK GENMASK(31, 30) |
| 28 | #define SYS_CFG_SATA_EN BIT(31) |
| 29 | |
| 30 | struct mtk_ahci_priv { |
| 31 | void *base; |
| 32 | |
| 33 | struct ahci_uc_priv ahci_priv; |
| 34 | struct regmap *mode; |
| 35 | struct reset_ctl_bulk rst_bulk; |
| 36 | }; |
| 37 | |
| 38 | static int mtk_ahci_bind(struct udevice *dev) |
| 39 | { |
| 40 | struct udevice *scsi_dev; |
| 41 | |
| 42 | return ahci_bind_scsi(dev, &scsi_dev); |
| 43 | } |
| 44 | |
| 45 | static int mtk_ahci_ofdata_to_platdata(struct udevice *dev) |
| 46 | { |
| 47 | struct mtk_ahci_priv *priv = dev_get_priv(dev); |
| 48 | |
| 49 | priv->base = devfdt_remap_addr_index(dev, 0); |
| 50 | |
| 51 | return 0; |
| 52 | } |
| 53 | |
| 54 | static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv, |
| 55 | struct udevice *dev) |
| 56 | { |
| 57 | struct mtk_ahci_priv *plat = dev_get_priv(dev); |
| 58 | const void *fdt = gd->fdt_blob; |
| 59 | |
| 60 | /* enable SATA function if needed */ |
| 61 | if (fdt_get_property(fdt, dev_of_offset(dev), |
| 62 | "mediatek,phy-mode", NULL)) { |
| 63 | plat->mode = syscon_regmap_lookup_by_phandle(dev, |
| 64 | "mediatek,phy-mode"); |
| 65 | if (IS_ERR(plat->mode)) { |
| 66 | dev_err(dev, "missing phy-mode phandle\n"); |
| 67 | return PTR_ERR(plat->mode); |
| 68 | } |
| 69 | regmap_update_bits(plat->mode, SYS_CFG, |
| 70 | SYS_CFG_SATA_MSK, SYS_CFG_SATA_EN); |
| 71 | } |
| 72 | |
| 73 | ofnode_read_u32(dev->node, "ports-implemented", &hpriv->port_map); |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | static int mtk_ahci_probe(struct udevice *dev) |
| 78 | { |
| 79 | struct mtk_ahci_priv *priv = dev_get_priv(dev); |
| 80 | int ret; |
| 81 | struct phy phy; |
| 82 | |
| 83 | ret = mtk_ahci_parse_property(&priv->ahci_priv, dev); |
| 84 | if (ret) |
| 85 | return ret; |
| 86 | |
| 87 | ret = reset_get_bulk(dev, &priv->rst_bulk); |
| 88 | if (!ret) { |
| 89 | reset_assert_bulk(&priv->rst_bulk); |
| 90 | reset_deassert_bulk(&priv->rst_bulk); |
| 91 | } else { |
| 92 | dev_err(dev, "Failed to get reset: %d\n", ret); |
| 93 | } |
| 94 | |
| 95 | ret = generic_phy_get_by_name(dev, "sata-phy", &phy); |
| 96 | if (ret) { |
| 97 | pr_err("can't get the phy from DT\n"); |
| 98 | return ret; |
| 99 | } |
| 100 | |
| 101 | ret = generic_phy_init(&phy); |
| 102 | if (ret) { |
| 103 | pr_err("unable to initialize the sata phy\n"); |
| 104 | return ret; |
| 105 | } |
| 106 | |
| 107 | ret = generic_phy_power_on(&phy); |
| 108 | if (ret) { |
| 109 | pr_err("unable to power on the sata phy\n"); |
| 110 | return ret; |
| 111 | } |
| 112 | |
| 113 | return ahci_probe_scsi(dev, (ulong)priv->base); |
| 114 | } |
| 115 | |
| 116 | static const struct udevice_id mtk_ahci_ids[] = { |
| 117 | { .compatible = "mediatek,mtk-ahci" }, |
| 118 | { } |
| 119 | }; |
| 120 | |
| 121 | U_BOOT_DRIVER(mtk_ahci) = { |
| 122 | .name = "mtk_ahci", |
| 123 | .id = UCLASS_AHCI, |
| 124 | .of_match = mtk_ahci_ids, |
| 125 | .bind = mtk_ahci_bind, |
| 126 | .ofdata_to_platdata = mtk_ahci_ofdata_to_platdata, |
| 127 | .ops = &scsi_ops, |
| 128 | .probe = mtk_ahci_probe, |
| 129 | .priv_auto_alloc_size = sizeof(struct mtk_ahci_priv), |
| 130 | }; |