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Lukasz Majewski1d7993d2019-06-24 15:50:45 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 *
6 * Copyright 2012 Freescale Semiconductor, Inc.
7 * Copyright 2012 Linaro Ltd.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <common.h>
18#include <asm/io.h>
19#include <malloc.h>
20#include <clk-uclass.h>
21#include <dm/device.h>
22#include <linux/clk-provider.h>
23#include <div64.h>
24#include <clk.h>
25#include "clk.h"
26
27#define UBOOT_DM_CLK_IMX_PFD "imx_clk_pfd"
28
29struct clk_pfd {
30 struct clk clk;
31 void __iomem *reg;
32 u8 idx;
33};
34
35#define to_clk_pfd(_clk) container_of(_clk, struct clk_pfd, clk)
36
37#define SET 0x4
38#define CLR 0x8
39#define OTG 0xc
40
41static unsigned long clk_pfd_recalc_rate(struct clk *clk)
42{
43 struct clk_pfd *pfd =
44 to_clk_pfd(dev_get_clk_ptr(clk->dev));
45 unsigned long parent_rate = clk_get_parent_rate(clk);
46 u64 tmp = parent_rate;
47 u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
48
49 tmp *= 18;
50 do_div(tmp, frac);
51
52 return tmp;
53}
54
Giulio Benetti824c3712020-01-10 15:47:00 +010055static unsigned long clk_pfd_set_rate(struct clk *clk, unsigned long rate)
56{
57 struct clk_pfd *pfd = to_clk_pfd(clk);
58 unsigned long parent_rate = clk_get_parent_rate(clk);
59 u64 tmp = parent_rate;
60 u8 frac;
61
62 tmp = tmp * 18 + rate / 2;
63 do_div(tmp, rate);
64 frac = tmp;
65 if (frac < 12)
66 frac = 12;
67 else if (frac > 35)
68 frac = 35;
69
70 writel(0x3f << (pfd->idx * 8), pfd->reg + CLR);
71 writel(frac << (pfd->idx * 8), pfd->reg + SET);
72
73 return 0;
74}
75
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020076static const struct clk_ops clk_pfd_ops = {
77 .get_rate = clk_pfd_recalc_rate,
Giulio Benetti824c3712020-01-10 15:47:00 +010078 .set_rate = clk_pfd_set_rate,
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020079};
80
81struct clk *imx_clk_pfd(const char *name, const char *parent_name,
82 void __iomem *reg, u8 idx)
83{
84 struct clk_pfd *pfd;
85 struct clk *clk;
86 int ret;
87
88 pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
89 if (!pfd)
90 return ERR_PTR(-ENOMEM);
91
92 pfd->reg = reg;
93 pfd->idx = idx;
94
95 /* register the clock */
96 clk = &pfd->clk;
97
98 ret = clk_register(clk, UBOOT_DM_CLK_IMX_PFD, name, parent_name);
99 if (ret) {
100 kfree(pfd);
101 return ERR_PTR(ret);
102 }
103
104 return clk;
105}
106
107U_BOOT_DRIVER(clk_pfd) = {
108 .name = UBOOT_DM_CLK_IMX_PFD,
109 .id = UCLASS_CLK,
110 .ops = &clk_pfd_ops,
111 .flags = DM_FLAG_PRE_RELOC,
112};