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wdenk983fda82004-10-28 00:09:35 +00001/*
2 * (C) Copyright 2004
3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31#define CONFIG_MPC8220 1
32#define CONFIG_ALASKA8220 1 /* ... on Alaska board */
33
Wolfgang Denk2ae18242010-10-06 09:05:45 +020034#define CONFIG_SYS_TEXT_BASE 0xfff00000
35
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050036#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce31d82672008-05-08 19:02:12 -050037#define CONFIG_HIGH_BATS 1 /* High BATs supported */
38
wdenk983fda82004-10-28 00:09:35 +000039/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
40 determine the CPU speed. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_MPC8220_CLKIN 30000000/* ... running at 30MHz */
42#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
wdenk983fda82004-10-28 00:09:35 +000043
wdenk983fda82004-10-28 00:09:35 +000044/*
45 * Serial console configuration
46 */
wdenk7680c142005-05-16 15:23:22 +000047
48/* Define this for PSC console
49#define CONFIG_PSC_CONSOLE 1
50*/
51
wdenk983fda82004-10-28 00:09:35 +000052#define CONFIG_EXTUART_CONSOLE 1
53
54#ifdef CONFIG_EXTUART_CONSOLE
wdenk7680c142005-05-16 15:23:22 +000055# define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056# define CONFIG_SYS_NS16550_SERIAL
57# define CONFIG_SYS_NS16550
58# define CONFIG_SYS_NS16550_REG_SIZE 1
59# define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CPLD_BASE + 0x1008)
60# define CONFIG_SYS_NS16550_CLK 18432000
wdenk983fda82004-10-28 00:09:35 +000061#endif
62
63#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk983fda82004-10-28 00:09:35 +000066
wdenk7680c142005-05-16 15:23:22 +000067#define CONFIG_TIMESTAMP /* Print image info with timestamp */
wdenk414eec32005-04-02 22:37:54 +000068
Jon Loeliger498ff9a2007-07-05 19:13:52 -050069
wdenk983fda82004-10-28 00:09:35 +000070/*
Jon Loeliger11799432007-07-10 09:02:57 -050071 * BOOTP options
72 */
73#define CONFIG_BOOTP_BOOTFILESIZE
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77
78
79/*
Jon Loeliger498ff9a2007-07-05 19:13:52 -050080 * Command line configuration.
wdenk983fda82004-10-28 00:09:35 +000081 */
Jon Loeliger498ff9a2007-07-05 19:13:52 -050082#include <config_cmd_default.h>
83
84#define CONFIG_CMD_BOOTD
85#define CONFIG_CMD_CACHE
86#define CONFIG_CMD_DHCP
87#define CONFIG_CMD_DIAG
88#define CONFIG_CMD_EEPROM
89#define CONFIG_CMD_ELF
90#define CONFIG_CMD_I2C
91#define CONFIG_CMD_NET
92#define CONFIG_CMD_NFS
93#define CONFIG_CMD_PCI
94#define CONFIG_CMD_PING
95#define CONFIG_CMD_REGINFO
96#define CONFIG_CMD_SDRAM
97#define CONFIG_CMD_SNTP
98
wdenk983fda82004-10-28 00:09:35 +000099
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200100#define CONFIG_MII
wdenk983fda82004-10-28 00:09:35 +0000101
wdenk983fda82004-10-28 00:09:35 +0000102/*
103 * Autobooting
104 */
105#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
106#define CONFIG_BOOTARGS "root=/dev/ram rw"
107#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
wdenke2ffd592004-12-31 09:32:47 +0000108#define CONFIG_HAS_ETH1
wdenk983fda82004-10-28 00:09:35 +0000109#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
110#define CONFIG_IPADDR 192.162.1.2
111#define CONFIG_NETMASK 255.255.255.0
112#define CONFIG_SERVERIP 192.162.1.1
113#define CONFIG_GATEWAYIP 192.162.1.1
114#define CONFIG_HOSTNAME Alaska
115#define CONFIG_OVERWRITE_ETHADDR_ONCE
116
117
118/*
119 * I2C configuration
120 */
121#define CONFIG_HARD_I2C 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_I2C_MODULE 1
wdenk983fda82004-10-28 00:09:35 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
125#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk983fda82004-10-28 00:09:35 +0000126
127/*
128 * EEPROM configuration
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
131#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
132#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
133#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenk983fda82004-10-28 00:09:35 +0000134/*
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200135#define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200136#define CONFIG_ENV_OFFSET 0
137#define CONFIG_ENV_SIZE 256
wdenk983fda82004-10-28 00:09:35 +0000138*/
139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
wdenk983fda82004-10-28 00:09:35 +0000141 else undefined it will boot from Intel Strata flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_AMD_BOOT 1
wdenk983fda82004-10-28 00:09:35 +0000143
144/*
145 * Flexbus Chipselect configuration
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#if defined (CONFIG_SYS_AMD_BOOT)
148#define CONFIG_SYS_CS0_BASE 0xfff0
149#define CONFIG_SYS_CS0_MASK 0x00080000 /* 512 KB */
150#define CONFIG_SYS_CS0_CTRL 0x003f0d40
wdenk983fda82004-10-28 00:09:35 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_CS1_BASE 0xfe00
153#define CONFIG_SYS_CS1_MASK 0x01000000 /* 16 MB */
154#define CONFIG_SYS_CS1_CTRL 0x003f1540
wdenk983fda82004-10-28 00:09:35 +0000155#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_CS0_BASE 0xff00
157#define CONFIG_SYS_CS0_MASK 0x01000000 /* 16 MB */
158#define CONFIG_SYS_CS0_CTRL 0x003f1540
wdenk983fda82004-10-28 00:09:35 +0000159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_CS1_BASE 0xfe08
161#define CONFIG_SYS_CS1_MASK 0x00080000 /* 512 KB */
162#define CONFIG_SYS_CS1_CTRL 0x003f0d40
wdenk983fda82004-10-28 00:09:35 +0000163#endif
164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_CS2_BASE 0xf100
166#define CONFIG_SYS_CS2_MASK 0x00040000
167#define CONFIG_SYS_CS2_CTRL 0x003f1140
wdenk983fda82004-10-28 00:09:35 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_CS3_BASE 0xf200
170#define CONFIG_SYS_CS3_MASK 0x00040000
171#define CONFIG_SYS_CS3_CTRL 0x003f1100
wdenk983fda82004-10-28 00:09:35 +0000172
173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
175#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_CS1_BASE << 16)
wdenk983fda82004-10-28 00:09:35 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#if defined (CONFIG_SYS_AMD_BOOT)
178#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH0_BASE
179#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH1_BASE + 0xf00000
180#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_AMD_BASE
wdenk983fda82004-10-28 00:09:35 +0000181#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH0_BASE + 0xf00000
183#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH1_BASE
184#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_INTEL_BASE
wdenk983fda82004-10-28 00:09:35 +0000185#endif
186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_CPLD_BASE (CONFIG_SYS_CS2_BASE << 16)
188#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_CS3_BASE << 16)
wdenk983fda82004-10-28 00:09:35 +0000189
190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max num of memory banks */
192#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenk983fda82004-10-28 00:09:35 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
195#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
196#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
197#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
198#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
wdenk983fda82004-10-28 00:09:35 +0000199
200#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
201#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_CHECKSUM
wdenk983fda82004-10-28 00:09:35 +0000204/*
205 * Environment settings
206 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200207#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#if defined (CONFIG_SYS_AMD_BOOT)
209#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200210#define CONFIG_ENV_SIZE PHYS_AMD_SECT_SIZE
211#define CONFIG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200213#define CONFIG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
214#define CONFIG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
wdenk983fda82004-10-28 00:09:35 +0000215#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200217#define CONFIG_ENV_SIZE PHYS_INTEL_SECT_SIZE
218#define CONFIG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200220#define CONFIG_ENV1_SIZE PHYS_AMD_SECT_SIZE
221#define CONFIG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
wdenk983fda82004-10-28 00:09:35 +0000222#endif
223
224#define CONFIG_ENV_OVERWRITE 1
225
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200226#if defined CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200227#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200228#undef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200229#elif defined CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200230#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200231#undef CONFIG_ENV_IS_IN_EEPROM
232#elif defined CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200233#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200234#undef CONFIG_ENV_IS_IN_FLASH
wdenk983fda82004-10-28 00:09:35 +0000235#endif
236
wdenk983fda82004-10-28 00:09:35 +0000237/*
238 * Memory map
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MBAR 0xF0000000
241#define CONFIG_SYS_SDRAM_BASE 0x00000000
242#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
243#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
244#define CONFIG_SYS_SRAM_SIZE 0x8000
wdenk983fda82004-10-28 00:09:35 +0000245
246/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
Wolfgang Denk553f0982010-10-26 13:32:32 +0200248#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
wdenk983fda82004-10-28 00:09:35 +0000249
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200250#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk983fda82004-10-28 00:09:35 +0000252
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200253#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
255# define CONFIG_SYS_RAMBOOT 1
wdenk983fda82004-10-28 00:09:35 +0000256#endif
257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
259#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
260#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk983fda82004-10-28 00:09:35 +0000261
wdenk12b43d52005-04-05 21:57:18 +0000262/* SDRAM configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_SDRAM_TOTAL_BANKS 2
264#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
265#define CONFIG_SYS_SDRAM_SPD_SIZE 0x40
266#define CONFIG_SYS_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
wdenk7680c142005-05-16 15:23:22 +0000267
268/* SDRAM drive strength register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
wdenk7680c142005-05-16 15:23:22 +0000270 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
271 (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
272 (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
273 (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
wdenk12b43d52005-04-05 21:57:18 +0000274
wdenk983fda82004-10-28 00:09:35 +0000275/*
276 * Ethernet configuration
277 */
278#define CONFIG_MPC8220_FEC 1
279#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
280#define CONFIG_PHY_ADDR 0x18
281
282
283/*
284 * Miscellaneous configurable options
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_LONGHELP /* undef to save memory */
287#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500288#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk983fda82004-10-28 00:09:35 +0000290#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk983fda82004-10-28 00:09:35 +0000292#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
294#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
295#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk983fda82004-10-28 00:09:35 +0000296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
298#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenk983fda82004-10-28 00:09:35 +0000299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk983fda82004-10-28 00:09:35 +0000301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk983fda82004-10-28 00:09:35 +0000303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500305#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500307#endif
308
wdenk983fda82004-10-28 00:09:35 +0000309/*
310 * Various low-level settings
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
313#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenk983fda82004-10-28 00:09:35 +0000314
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200315/*
316 * JFFS2 partitions
317 */
318
319/* No command line, one static partition */
320/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100321#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200322#define CONFIG_JFFS2_DEV "nor0"
323#define CONFIG_JFFS2_PART_SIZE 0x00400000
324#define CONFIG_JFFS2_PART_OFFSET 0x00000000
325*/
326
327/* mtdparts command line support */
328/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100329#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200330#define MTDIDS_DEFAULT "nor0=alaska-0"
331#define MTDPARTS_DEFAULT "mtdparts=alaska-0:4m(user)"
332*/
333
wdenk983fda82004-10-28 00:09:35 +0000334#endif /* __CONFIG_H */