| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 1 | menu "MediaTek MIPS platforms" |
| Weijie Gao | 16b9490 | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 2 | depends on ARCH_MTMIPS |
| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 3 | |
| 4 | config SYS_MALLOC_F_LEN |
| 5 | default 0x1000 |
| 6 | |
| 7 | config SYS_SOC |
| Weijie Gao | 16b9490 | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 8 | default "mt7628" if SOC_MT7628 |
| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 9 | |
| 10 | choice |
| 11 | prompt "MediaTek MIPS SoC select" |
| 12 | |
| Weijie Gao | 16b9490 | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 13 | config SOC_MT7628 |
| 14 | bool "MT7628" |
| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 15 | select MIPS_L1_CACHE_SHIFT_5 |
| 16 | help |
| Weijie Gao | 16b9490 | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 17 | This supports MediaTek MT7628/MT7688. |
| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 18 | |
| 19 | endchoice |
| 20 | |
| 21 | choice |
| 22 | prompt "Board select" |
| 23 | |
| Stefan Roese | 88dc409 | 2018-08-16 15:27:31 +0200 | [diff] [blame] | 24 | config BOARD_GARDENA_SMART_GATEWAY_MT7688 |
| Stefan Roese | eacbdd6 | 2019-03-15 09:09:34 +0100 | [diff] [blame] | 25 | bool "GARDENA smart Gateway" |
| Weijie Gao | 16b9490 | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 26 | depends on SOC_MT7628 |
| Stefan Roese | b1f51fc | 2018-10-09 08:59:13 +0200 | [diff] [blame] | 27 | select BOARD_LATE_INIT |
| Stefan Roese | 88dc409 | 2018-08-16 15:27:31 +0200 | [diff] [blame] | 28 | select SUPPORTS_BOOT_RAM |
| 29 | help |
| Stefan Roese | eacbdd6 | 2019-03-15 09:09:34 +0100 | [diff] [blame] | 30 | GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM |
| Stefan Roese | 88dc409 | 2018-08-16 15:27:31 +0200 | [diff] [blame] | 31 | and 8 MiB of flash (SPI NOR) and additional SPI NAND storage. |
| 32 | |
| Stefan Roese | b02f76a | 2018-08-16 15:27:30 +0200 | [diff] [blame] | 33 | config BOARD_LINKIT_SMART_7688 |
| 34 | bool "LinkIt Smart 7688" |
| Weijie Gao | 16b9490 | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 35 | depends on SOC_MT7628 |
| Stefan Roese | b02f76a | 2018-08-16 15:27:30 +0200 | [diff] [blame] | 36 | select SUPPORTS_BOOT_RAM |
| 37 | help |
| 38 | Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM |
| 39 | and 32 MiB of flash (SPI). |
| 40 | Between its different peripherals there's an integrated switch with 4 |
| 41 | ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and |
| 42 | a MT7688 (PCIe). |
| 43 | |
| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 44 | endchoice |
| 45 | |
| 46 | choice |
| 47 | prompt "Boot mode" |
| 48 | |
| 49 | config BOOT_RAM |
| 50 | bool "RAM boot" |
| 51 | depends on SUPPORTS_BOOT_RAM |
| 52 | help |
| 53 | This builds an image that is linked to a RAM address. It can be used |
| 54 | for booting from CFE via TFTP using an ELF image, but it can also be |
| 55 | booted from RAM by other bootloaders using a BIN image. |
| 56 | |
| 57 | config BOOT_ROM |
| 58 | bool "ROM boot" |
| 59 | depends on SUPPORTS_BOOT_RAM |
| 60 | help |
| 61 | This builds an image that is linked to a ROM address. It can be |
| 62 | used as main bootloader image which is programmed onto the onboard |
| 63 | flash storage (SPI NOR). |
| 64 | |
| 65 | endchoice |
| 66 | |
| 67 | choice |
| 68 | prompt "DDR2 size" |
| 69 | |
| 70 | config ONBOARD_DDR2_SIZE_256MBIT |
| 71 | bool "256MBit (32MByte) total size" |
| 72 | depends on BOOT_ROM |
| 73 | help |
| 74 | Use 256MBit (32MByte) of DDR total size |
| 75 | |
| 76 | config ONBOARD_DDR2_SIZE_512MBIT |
| 77 | bool "512MBit (64MByte) total size" |
| 78 | depends on BOOT_ROM |
| 79 | help |
| 80 | Use 512MBit (64MByte) of DDR total size |
| 81 | |
| 82 | config ONBOARD_DDR2_SIZE_1024MBIT |
| 83 | bool "1024MBit (128MByte) total size" |
| 84 | depends on BOOT_ROM |
| 85 | help |
| 86 | Use 1024MBit (128MByte) of DDR total size |
| 87 | |
| 88 | config ONBOARD_DDR2_SIZE_2048MBIT |
| 89 | bool "2048MBit (256MByte) total size" |
| 90 | depends on BOOT_ROM |
| 91 | help |
| 92 | Use 2048MBit (256MByte) of DDR total size |
| 93 | |
| 94 | endchoice |
| 95 | |
| 96 | choice |
| 97 | prompt "DDR2 chip width" |
| 98 | |
| 99 | config ONBOARD_DDR2_CHIP_WIDTH_8BIT |
| 100 | bool "8bit DDR chip width" |
| 101 | depends on BOOT_ROM |
| 102 | help |
| 103 | Use DDR chips with 8bit width |
| 104 | |
| 105 | config ONBOARD_DDR2_CHIP_WIDTH_16BIT |
| 106 | bool "16bit DDR chip width" |
| 107 | depends on BOOT_ROM |
| 108 | help |
| 109 | Use DDR chips with 16bit width |
| 110 | |
| 111 | endchoice |
| 112 | |
| 113 | choice |
| 114 | prompt "DDR2 bus width" |
| 115 | |
| 116 | config ONBOARD_DDR2_BUS_WIDTH_16BIT |
| 117 | bool "16bit DDR bus width" |
| 118 | depends on BOOT_ROM |
| 119 | help |
| 120 | Use 16bit DDR bus width |
| 121 | |
| 122 | config ONBOARD_DDR2_BUS_WIDTH_32BIT |
| 123 | bool "32bit DDR bus width" |
| 124 | depends on BOOT_ROM |
| 125 | help |
| 126 | Use 32bit DDR bus width |
| 127 | |
| 128 | endchoice |
| 129 | |
| 130 | config SUPPORTS_BOOT_RAM |
| 131 | bool |
| 132 | |
| Stefan Roese | 88dc409 | 2018-08-16 15:27:31 +0200 | [diff] [blame] | 133 | source "board/gardena/smart-gateway-mt7688/Kconfig" |
| Stefan Roese | b02f76a | 2018-08-16 15:27:30 +0200 | [diff] [blame] | 134 | source "board/seeed/linkit-smart-7688/Kconfig" |
| 135 | |
| Stefan Roese | 4c835a6 | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 136 | endmenu |