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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
stroesea20b27a2004-12-16 18:05:42 +000027#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
stroesea20b27a2004-12-16 18:05:42 +000034#define CONFIG_405EP 1 /* This is a PPC405 CPU */
35#define CONFIG_4xx 1 /* ...member of PPC4xx family */
36#define CONFIG_VOM405 1 /* ...on a VOM405 board */
37
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
39
stroesea20b27a2004-12-16 18:05:42 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
42
43#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
44
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#undef CONFIG_BOOTARGS
49#undef CONFIG_BOOTCOMMAND
50
51#define CONFIG_PREBOOT /* enable preboot variable */
52
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesea20b27a2004-12-16 18:05:42 +000054
Stefan Roesefeaedfc2005-11-15 10:35:59 +010055#undef CONFIG_HAS_ETH1
56
Ben Warren96e21f82008-10-27 23:50:15 -070057#define CONFIG_PPC4xx_EMAC
stroesea20b27a2004-12-16 18:05:42 +000058#define CONFIG_MII 1 /* MII PHY management */
59#define CONFIG_PHY_ADDR 0 /* PHY address */
60#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Stefan Roesefeaedfc2005-11-15 10:35:59 +010061#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
stroesea20b27a2004-12-16 18:05:42 +000062
Jon Loeliger37d4bb72007-07-09 21:38:02 -050063/*
64 * BOOTP options
65 */
66#define CONFIG_BOOTP_SUBNETMASK
67#define CONFIG_BOOTP_GATEWAY
68#define CONFIG_BOOTP_HOSTNAME
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_DNS
71#define CONFIG_BOOTP_DNS2
72#define CONFIG_BOOTP_SEND_HOSTNAME
stroesea20b27a2004-12-16 18:05:42 +000073
Jon Loeligera5562902007-07-08 15:31:57 -050074/*
75 * Command line configuration.
76 */
77#include <config_cmd_default.h>
78
79#define CONFIG_CMD_DHCP
80#define CONFIG_CMD_BSP
Jon Loeligera5562902007-07-08 15:31:57 -050081#define CONFIG_CMD_IRQ
82#define CONFIG_CMD_ELF
83#define CONFIG_CMD_I2C
84#define CONFIG_CMD_MII
85#define CONFIG_CMD_PING
86#define CONFIG_CMD_EEPROM
87
Matthias Fuchsfcaffd52008-09-02 15:07:51 +020088#define CONFIG_OF_LIBFDT
89#define CONFIG_OF_BOARD_SETUP
stroesea20b27a2004-12-16 18:05:42 +000090
91#undef CONFIG_WATCHDOG /* watchdog disabled */
92
93#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
94
95#undef CONFIG_PRAM /* no "protected RAM" */
96
97/*
98 * Miscellaneous configurable options
99 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_LONGHELP /* undef to save memory */
101#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroesea20b27a2004-12-16 18:05:42 +0000102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
104#ifdef CONFIG_SYS_HUSH_PARSER
105#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroesea20b27a2004-12-16 18:05:42 +0000106#endif
107
Jon Loeligera5562902007-07-08 15:31:57 -0500108#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000110#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000112#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
114#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
115#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesea20b27a2004-12-16 18:05:42 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesea20b27a2004-12-16 18:05:42 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
122#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000123
Stefan Roese550650d2010-09-20 16:05:31 +0200124#define CONFIG_CONS_INDEX 1 /* Use UART0 */
125#define CONFIG_SYS_NS16550
126#define CONFIG_SYS_NS16550_SERIAL
127#define CONFIG_SYS_NS16550_REG_SIZE 1
128#define CONFIG_SYS_NS16550_CLK get_serial_clock()
129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_BASE_BAUD 691200
stroesea20b27a2004-12-16 18:05:42 +0000132
133/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_BAUDRATE_TABLE \
stroesea20b27a2004-12-16 18:05:42 +0000135 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
136 57600, 115200, 230400, 460800, 921600 }
137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
139#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesea20b27a2004-12-16 18:05:42 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroesea20b27a2004-12-16 18:05:42 +0000142
Matthias Fuchs1092ce22008-09-02 15:07:54 +0200143#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
stroesea20b27a2004-12-16 18:05:42 +0000144#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
145
146#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea20b27a2004-12-16 18:05:42 +0000149
stroesea20b27a2004-12-16 18:05:42 +0000150/*
151 * For booting Linux, the board info and command line data
152 * have to be in the first 8 MB of memory, since this is
153 * the maximum mapped by the Linux kernel during initialization.
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchs1092ce22008-09-02 15:07:54 +0200156/*
stroesea20b27a2004-12-16 18:05:42 +0000157 * FLASH organization
158 */
159#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
162#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroesea20b27a2004-12-16 18:05:42 +0000163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
165#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
stroesea20b27a2004-12-16 18:05:42 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
168#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
169#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesea20b27a2004-12-16 18:05:42 +0000170/*
171 * The following defines are added for buggy IOP480 byte interface.
172 * All other boards should use the standard values (CPCI405 etc.)
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
175#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
176#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroesea20b27a2004-12-16 18:05:42 +0000177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea20b27a2004-12-16 18:05:42 +0000179
Matthias Fuchs1092ce22008-09-02 15:07:54 +0200180/*
stroesea20b27a2004-12-16 18:05:42 +0000181 * Start addresses for the final memory configuration
182 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_SDRAM_BASE 0x00000000
Matthias Fuchs700d5532009-04-29 09:50:59 +0200186#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200187#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
188#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Matthias Fuchs700d5532009-04-29 09:50:59 +0200189#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
stroesea20b27a2004-12-16 18:05:42 +0000190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
192# define CONFIG_SYS_RAMBOOT 1
stroesea20b27a2004-12-16 18:05:42 +0000193#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194# undef CONFIG_SYS_RAMBOOT
stroesea20b27a2004-12-16 18:05:42 +0000195#endif
196
Matthias Fuchs1092ce22008-09-02 15:07:54 +0200197/*
stroesea20b27a2004-12-16 18:05:42 +0000198 * Environment Variable setup
199 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200200#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200201#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
202#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000203 /* total size of a CAT24WC16 is 2048 bytes */
204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
206#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
stroesea20b27a2004-12-16 18:05:42 +0000207
Matthias Fuchs1092ce22008-09-02 15:07:54 +0200208/*
stroesea20b27a2004-12-16 18:05:42 +0000209 * I2C EEPROM (CAT24WC16) for environment
210 */
211#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200212#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
214#define CONFIG_SYS_I2C_SLAVE 0x7F
stroesea20b27a2004-12-16 18:05:42 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
217#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
stroesea20b27a2004-12-16 18:05:42 +0000218/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
220#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroesea20b27a2004-12-16 18:05:42 +0000221 /* 16 byte page write mode using*/
222 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea20b27a2004-12-16 18:05:42 +0000224
Matthias Fuchs1092ce22008-09-02 15:07:54 +0200225/*
stroesea20b27a2004-12-16 18:05:42 +0000226 * External Bus Controller (EBC) Setup
227 */
stroesea20b27a2004-12-16 18:05:42 +0000228#define CAN_BA 0xF0000000 /* CAN Base Address */
229
230/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_EBC_PB0AP 0x92015480
232#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000233
234/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
236#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000237
Matthias Fuchs1092ce22008-09-02 15:07:54 +0200238/*
stroesea20b27a2004-12-16 18:05:42 +0000239 * FPGA stuff
240 */
Matthias Fuchs700d5532009-04-29 09:50:59 +0200241#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
stroesea20b27a2004-12-16 18:05:42 +0000242
243/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
245#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
246#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
247#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
248#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
stroesea20b27a2004-12-16 18:05:42 +0000249
Matthias Fuchs1092ce22008-09-02 15:07:54 +0200250/*
stroesea20b27a2004-12-16 18:05:42 +0000251 * Definitions for initial stack pointer and data area (in data cache)
252 */
253/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_TEMP_STACK_OCM 1
stroesea20b27a2004-12-16 18:05:42 +0000255
256/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
258#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
259#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200260#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
stroesea20b27a2004-12-16 18:05:42 +0000261
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200262#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesea20b27a2004-12-16 18:05:42 +0000264
Matthias Fuchs1092ce22008-09-02 15:07:54 +0200265/*
stroesea20b27a2004-12-16 18:05:42 +0000266 * Definitions for GPIO setup (PPC405EP specific)
267 *
268 * GPIO0[0] - External Bus Controller BLAST output
269 * GPIO0[1-9] - Instruction trace outputs -> GPIO
270 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
271 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
272 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
273 * GPIO0[24-27] - UART0 control signal inputs/outputs
274 * GPIO0[28-29] - UART1 data signal input/output
275 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
276 */
277/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
278/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
279/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
280/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200281#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
282#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
283#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
284#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
285#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
286#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
stroesea20b27a2004-12-16 18:05:42 +0000288
289/*
stroesea20b27a2004-12-16 18:05:42 +0000290 * Default speed selection (cpu_plb_opb_ebc) in mhz.
291 * This value will be set if iic boot eprom is disabled.
292 */
stroesea20b27a2004-12-16 18:05:42 +0000293#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
294#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroesea20b27a2004-12-16 18:05:42 +0000295
296#endif /* __CONFIG_H */