| wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * mcftimer.h -- ColdFire internal TIMER support defines. |
| 3 | * |
| 4 | * Based on mcftimer.h of uCLinux distribution: |
| 5 | * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com) |
| 6 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | /****************************************************************************/ |
| 28 | #ifndef mcftimer_h |
| 29 | #define mcftimer_h |
| 30 | /****************************************************************************/ |
| 31 | |
| 32 | #include <linux/config.h> |
| 33 | |
| 34 | /* |
| 35 | * Get address specific defines for this ColdFire member. |
| 36 | */ |
| 37 | #if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) |
| 38 | #define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ |
| 39 | #define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ |
| 40 | #elif defined(CONFIG_M5272) |
| 41 | #define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ |
| 42 | #define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ |
| 43 | #define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ |
| 44 | #define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ |
| 45 | #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) |
| 46 | #define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ |
| 47 | #define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ |
| Zachary P. Landau | eacbd31 | 2006-01-26 17:35:56 -0500 | [diff] [blame] | 48 | #elif defined(CONFIG_M5282) | defined(CONFIG_M5271) |
| wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 49 | #define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */ |
| 50 | #define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */ |
| 51 | #define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */ |
| 52 | #define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */ |
| 53 | #endif |
| 54 | |
| 55 | /* |
| 56 | * Define the TIMER register set addresses. |
| 57 | */ |
| 58 | #define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ |
| 59 | #define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */ |
| 60 | #define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */ |
| 61 | #define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */ |
| 62 | #define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ |
| 63 | |
| 64 | |
| 65 | /* |
| 66 | * Define the TIMER register set addresses for 5282. |
| 67 | */ |
| 68 | #define MCFTIMER_PCSR 0 |
| 69 | #define MCFTIMER_PMR 1 |
| 70 | #define MCFTIMER_PCNTR 2 |
| 71 | |
| 72 | /* |
| 73 | * Bit definitions for the Timer Mode Register (TMR). |
| 74 | * Register bit flags are common accross ColdFires. |
| 75 | */ |
| 76 | #define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ |
| 77 | #define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ |
| 78 | #define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ |
| 79 | #define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ |
| 80 | #define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ |
| 81 | #define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ |
| 82 | #define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ |
| 83 | #define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ |
| 84 | #define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ |
| 85 | #define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ |
| 86 | #define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ |
| 87 | #define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ |
| 88 | #define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ |
| 89 | #define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ |
| 90 | #define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ |
| 91 | #define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ |
| 92 | #define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ |
| 93 | |
| 94 | /* |
| 95 | * Bit definitions for the Timer Event Registers (TER). |
| 96 | */ |
| 97 | #define MCFTIMER_TER_CAP 0x01 /* Capture event */ |
| 98 | #define MCFTIMER_TER_REF 0x02 /* Refernece event */ |
| 99 | |
| 100 | /* |
| 101 | * Bit definitions for the 5282 PIT Control and Status Register (PCSR). |
| 102 | */ |
| 103 | #define MCFTIMER_PCSR_EN 0x0001 |
| 104 | #define MCFTIMER_PCSR_RLD 0x0002 |
| 105 | #define MCFTIMER_PCSR_PIF 0x0004 |
| 106 | #define MCFTIMER_PCSR_PIE 0x0008 |
| 107 | #define MCFTIMER_PCSR_OVW 0x0010 |
| 108 | #define MCFTIMER_PCSR_HALTED 0x0020 |
| 109 | #define MCFTIMER_PCSR_DOZE 0x0040 |
| 110 | |
| 111 | |
| 112 | /****************************************************************************/ |
| 113 | #endif /* mcftimer_h */ |