blob: cebd175ff593de557760c5c014d011e887174aba [file] [log] [blame]
Dave Liu19580e62007-09-18 12:37:57 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Dave Liu19580e62007-09-18 12:37:57 +08006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Kim Phillipsfdfaa292015-03-17 12:00:45 -050011#define CONFIG_SYS_GENERIC_BOARD
12#define CONFIG_DISPLAY_BOARDINFO
13
Dave Liu19580e62007-09-18 12:37:57 +080014/*
15 * High Level Configuration Options
16 */
17#define CONFIG_E300 1 /* E300 family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050018#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Dave Liu19580e62007-09-18 12:37:57 +080019#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
20
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021#define CONFIG_SYS_TEXT_BASE 0xFE000000
22
Dave Liu19580e62007-09-18 12:37:57 +080023/*
24 * System Clock Setup
25 */
26#ifdef CONFIG_PCISLAVE
27#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
28#else
29#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
30#endif
31
32#ifndef CONFIG_SYS_CLK_FREQ
33#define CONFIG_SYS_CLK_FREQ 66000000
34#endif
35
36/*
37 * Hardware Reset Configuration Word
38 * if CLKIN is 66MHz, then
39 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
40 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_HRCW_LOW (\
Dave Liu19580e62007-09-18 12:37:57 +080042 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
43 HRCWL_DDR_TO_SCB_CLK_1X1 |\
44 HRCWL_SVCOD_DIV_2 |\
45 HRCWL_CSB_TO_CLKIN_6X1 |\
46 HRCWL_CORE_TO_CSB_1_5X1)
47
48#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080050 HRCWH_PCI_AGENT |\
51 HRCWH_PCI1_ARBITER_DISABLE |\
52 HRCWH_CORE_ENABLE |\
53 HRCWH_FROM_0XFFF00100 |\
54 HRCWH_BOOTSEQ_DISABLE |\
55 HRCWH_SW_WATCHDOG_DISABLE |\
56 HRCWH_ROM_LOC_LOCAL_16BIT |\
57 HRCWH_RL_EXT_LEGACY |\
58 HRCWH_TSEC1M_IN_RGMII |\
59 HRCWH_TSEC2M_IN_RGMII |\
60 HRCWH_BIG_ENDIAN |\
61 HRCWH_LDP_CLEAR)
62#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu19580e62007-09-18 12:37:57 +080064 HRCWH_PCI_HOST |\
65 HRCWH_PCI1_ARBITER_ENABLE |\
66 HRCWH_CORE_ENABLE |\
67 HRCWH_FROM_0X00000100 |\
68 HRCWH_BOOTSEQ_DISABLE |\
69 HRCWH_SW_WATCHDOG_DISABLE |\
70 HRCWH_ROM_LOC_LOCAL_16BIT |\
71 HRCWH_RL_EXT_LEGACY |\
72 HRCWH_TSEC1M_IN_RGMII |\
73 HRCWH_TSEC2M_IN_RGMII |\
74 HRCWH_BIG_ENDIAN |\
75 HRCWH_LDP_CLEAR)
76#endif
77
Dave Liubd4458c2008-03-04 16:59:22 +080078/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
Joe Hershberger8d858082011-10-11 23:57:18 -050080#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
Dave Liubd4458c2008-03-04 16:59:22 +080081
82/* System Priority Control Register */
Joe Hershberger8d858082011-10-11 23:57:18 -050083#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
Dave Liubd4458c2008-03-04 16:59:22 +080084
Dave Liu19580e62007-09-18 12:37:57 +080085/*
Dave Liubd4458c2008-03-04 16:59:22 +080086 * IP blocks clock configuration
Dave Liu19580e62007-09-18 12:37:57 +080087 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
89#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
Joe Hershberger8d858082011-10-11 23:57:18 -050090#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
Dave Liu19580e62007-09-18 12:37:57 +080091
92/*
93 * System IO Config
94 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_SICRH 0x00000000
96#define CONFIG_SYS_SICRL 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +080097
98/*
99 * Output Buffer Impedance
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_OBIR 0x31100000
Dave Liu19580e62007-09-18 12:37:57 +0800102
103#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
104#define CONFIG_BOARD_EARLY_INIT_R
Anton Vorontsovc78c6782009-06-10 00:25:31 +0400105#define CONFIG_HWCONFIG
Dave Liu19580e62007-09-18 12:37:57 +0800106
107/*
108 * IMMR new address
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu19580e62007-09-18 12:37:57 +0800111
112/*
113 * DDR Setup
114 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
116#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
117#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
118#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
119#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershberger2fef4022011-10-11 23:57:29 -0500120#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
121 | DDRCDR_ODT \
122 | DDRCDR_Q_DRN)
123 /* 0x80080001 */ /* ODT 150ohm on SoC */
Dave Liu19580e62007-09-18 12:37:57 +0800124
125#undef CONFIG_DDR_ECC /* support DDR ECC function */
126#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
127
128#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
129#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
130
131#if defined(CONFIG_SPD_EEPROM)
132#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
133#else
134/*
135 * Manually set up DDR parameters
Dave Liu7e74d632008-01-10 23:07:23 +0800136 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
Dave Liu19580e62007-09-18 12:37:57 +0800137 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_DDR_SIZE 512 /* MB */
140#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
Joe Hershberger8d858082011-10-11 23:57:18 -0500141#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500142 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
143 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
144 | CSCONFIG_ROW_BIT_14 \
145 | CSCONFIG_COL_BIT_10)
146 /* 0x80010202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger8d858082011-10-11 23:57:18 -0500148#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
149 | (0 << TIMING_CFG0_WRT_SHIFT) \
150 | (0 << TIMING_CFG0_RRT_SHIFT) \
151 | (0 << TIMING_CFG0_WWT_SHIFT) \
152 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
153 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
154 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
155 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800156 /* 0x00620802 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500157#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
158 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
159 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
160 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
161 | (13 << TIMING_CFG1_REFREC_SHIFT) \
162 | (3 << TIMING_CFG1_WRREC_SHIFT) \
163 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
164 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800165 /* 0x3935d322 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500166#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
167 | (6 << TIMING_CFG2_CPO_SHIFT) \
168 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
169 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
170 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
171 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
172 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
Dave Liu7e74d632008-01-10 23:07:23 +0800173 /* 0x131088c8 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500174#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
175 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Dave Liu19580e62007-09-18 12:37:57 +0800176 /* 0x03E00100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
178#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
Joe Hershberger8d858082011-10-11 23:57:18 -0500179#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
180 | (0x1432 << SDRAM_MODE_SD_SHIFT))
Dave Liu7e74d632008-01-10 23:07:23 +0800181 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Joe Hershberger8d858082011-10-11 23:57:18 -0500182#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu19580e62007-09-18 12:37:57 +0800183#endif
184
185/*
186 * Memory test
187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
189#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
190#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu19580e62007-09-18 12:37:57 +0800191
192/*
193 * The reserved memory
194 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200195#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dave Liu19580e62007-09-18 12:37:57 +0800196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
198#define CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800199#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#undef CONFIG_SYS_RAMBOOT
Dave Liu19580e62007-09-18 12:37:57 +0800201#endif
202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger8d858082011-10-11 23:57:18 -0500204#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
205#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu19580e62007-09-18 12:37:57 +0800206
207/*
208 * Initial RAM Base Address Setup
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_INIT_RAM_LOCK 1
211#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200212#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger8d858082011-10-11 23:57:18 -0500213#define CONFIG_SYS_GBL_DATA_OFFSET \
214 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu19580e62007-09-18 12:37:57 +0800215
216/*
217 * Local Bus Configuration & Clock Setup
218 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500219#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
220#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_LBC_LBCR 0x00000000
Becky Bruce0914f482010-06-17 11:37:18 -0500222#define CONFIG_FSL_ELBC 1
Dave Liu19580e62007-09-18 12:37:57 +0800223
224/*
225 * FLASH on the Local Bus
226 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500227#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200228#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Joe Hershberger8d858082011-10-11 23:57:18 -0500229#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
230#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
231#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu19580e62007-09-18 12:37:57 +0800232
Joe Hershberger8d858082011-10-11 23:57:18 -0500233 /* Window base at flash base */
234#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500235#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Dave Liu19580e62007-09-18 12:37:57 +0800236
Joe Hershberger8d858082011-10-11 23:57:18 -0500237#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500238 | BR_PS_16 /* 16 bit port */ \
239 | BR_MS_GPCM /* MSEL = GPCM */ \
240 | BR_V) /* valid */
241#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Dave Liuded08312008-01-10 23:08:26 +0800242 | OR_UPM_XAM \
243 | OR_GPCM_CSNT \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400244 | OR_GPCM_ACS_DIV2 \
Dave Liuded08312008-01-10 23:08:26 +0800245 | OR_GPCM_XACS \
246 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500247 | OR_GPCM_TRLX_SET \
248 | OR_GPCM_EHTR_SET \
Joe Hershberger8d858082011-10-11 23:57:18 -0500249 | OR_GPCM_EAD)
Dave Liuded08312008-01-10 23:08:26 +0800250 /* 0xFE000FF7 */
Dave Liu19580e62007-09-18 12:37:57 +0800251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
253#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Dave Liu19580e62007-09-18 12:37:57 +0800254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#undef CONFIG_SYS_FLASH_CHECKSUM
256#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
257#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu19580e62007-09-18 12:37:57 +0800258
259/*
260 * BCSR on the Local Bus
261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_BCSR 0xF8000000
Joe Hershberger8d858082011-10-11 23:57:18 -0500263 /* Access window base at BCSR base */
264#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500265#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu19580e62007-09-18 12:37:57 +0800266
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500267#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
268 | BR_PS_8 \
269 | BR_MS_GPCM \
270 | BR_V)
271 /* 0xF8000801 */
272#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
273 | OR_GPCM_XAM \
274 | OR_GPCM_CSNT \
275 | OR_GPCM_XACS \
276 | OR_GPCM_SCY_15 \
277 | OR_GPCM_TRLX_SET \
278 | OR_GPCM_EHTR_SET \
279 | OR_GPCM_EAD)
280 /* 0xFFFFE9F7 */
Dave Liu19580e62007-09-18 12:37:57 +0800281
282/*
283 * NAND Flash on the Local Bus
284 */
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400285#define CONFIG_CMD_NAND 1
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400286#define CONFIG_SYS_MAX_NAND_DEVICE 1
Joe Hershberger8d858082011-10-11 23:57:18 -0500287#define CONFIG_NAND_FSL_ELBC 1
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400288
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500289#define CONFIG_SYS_NAND_BASE 0xE0600000
Joe Hershberger8d858082011-10-11 23:57:18 -0500290#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500291 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger8d858082011-10-11 23:57:18 -0500292 | BR_PS_8 /* 8 bit port */ \
Dave Liu19580e62007-09-18 12:37:57 +0800293 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500294 | BR_V) /* valid */
295#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400296 | OR_FCM_BCTLD \
Dave Liu19580e62007-09-18 12:37:57 +0800297 | OR_FCM_CST \
298 | OR_FCM_CHT \
299 | OR_FCM_SCY_1 \
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400300 | OR_FCM_RST \
Dave Liu19580e62007-09-18 12:37:57 +0800301 | OR_FCM_TRLX \
Joe Hershberger8d858082011-10-11 23:57:18 -0500302 | OR_FCM_EHTR)
Anton Vorontsovb3379f32008-10-08 20:52:54 +0400303 /* 0xFFFF919E */
Dave Liu19580e62007-09-18 12:37:57 +0800304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500306#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu19580e62007-09-18 12:37:57 +0800307
308/*
309 * Serial Port
310 */
311#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_NS16550
313#define CONFIG_SYS_NS16550_SERIAL
314#define CONFIG_SYS_NS16550_REG_SIZE 1
315#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu19580e62007-09-18 12:37:57 +0800316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger8d858082011-10-11 23:57:18 -0500318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
Dave Liu19580e62007-09-18 12:37:57 +0800319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
321#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu19580e62007-09-18 12:37:57 +0800322
323/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_HUSH_PARSER
Dave Liu19580e62007-09-18 12:37:57 +0800325
326/* Pass open firmware flat tree */
327#define CONFIG_OF_LIBFDT 1
328#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600329#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Dave Liu19580e62007-09-18 12:37:57 +0800330
331/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200332#define CONFIG_SYS_I2C
333#define CONFIG_SYS_I2C_FSL
334#define CONFIG_SYS_FSL_I2C_SPEED 400000
335#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
336#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
337#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Dave Liu19580e62007-09-18 12:37:57 +0800338
339/*
340 * Config on-board RTC
341 */
342#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu19580e62007-09-18 12:37:57 +0800344
345/*
346 * General PCI
347 * Addresses are mapped 1-1.
348 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500349#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
350#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
351#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
353#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
354#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
355#define CONFIG_SYS_PCI_IO_BASE 0x00000000
356#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
357#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu19580e62007-09-18 12:37:57 +0800358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
360#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
361#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu19580e62007-09-18 12:37:57 +0800362
Anton Vorontsov8b345572009-01-08 04:26:19 +0300363#define CONFIG_SYS_PCIE1_BASE 0xA0000000
364#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
365#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
366#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
367#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
368#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
369#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
370#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
371#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
372
373#define CONFIG_SYS_PCIE2_BASE 0xC0000000
374#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
375#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
376#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
377#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
378#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
379#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
380#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
381#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
382
Dave Liu19580e62007-09-18 12:37:57 +0800383#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000384#define CONFIG_PCI_INDIRECT_BRIDGE
Anton Vorontsov00f7bba2008-10-02 19:17:33 +0400385#ifndef __ASSEMBLY__
386extern int board_pci_host_broken(void);
387#endif
Kim Phillipsbe9b56d2009-07-23 14:09:38 -0500388#define CONFIG_PCIE
Dave Liu19580e62007-09-18 12:37:57 +0800389#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
390
Anton Vorontsov3bf1be32008-10-14 22:58:53 +0400391#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
Nikhil Badola6c3c5752014-10-20 16:31:01 +0530392#define CONFIG_CMD_USB
393#define CONFIG_USB_STORAGE
394#define CONFIG_USB_EHCI
395#define CONFIG_USB_EHCI_FSL
396#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov3bf1be32008-10-14 22:58:53 +0400397
Dave Liu19580e62007-09-18 12:37:57 +0800398#define CONFIG_PCI_PNP /* do pci plug-and-play */
399
400#undef CONFIG_EEPRO100
401#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu19580e62007-09-18 12:37:57 +0800403#endif /* CONFIG_PCI */
404
Dave Liu19580e62007-09-18 12:37:57 +0800405/*
406 * TSEC
407 */
408#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger8d858082011-10-11 23:57:18 -0500410#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger8d858082011-10-11 23:57:18 -0500412#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu19580e62007-09-18 12:37:57 +0800413
414/*
415 * TSEC ethernet configuration
416 */
417#define CONFIG_MII 1 /* MII PHY management */
418#define CONFIG_TSEC1 1
419#define CONFIG_TSEC1_NAME "eTSEC0"
420#define CONFIG_TSEC2 1
421#define CONFIG_TSEC2_NAME "eTSEC1"
422#define TSEC1_PHY_ADDR 2
423#define TSEC2_PHY_ADDR 3
Anton Vorontsov1da83a62008-10-02 18:32:25 +0400424#define TSEC1_PHY_ADDR_SGMII 8
425#define TSEC2_PHY_ADDR_SGMII 4
Dave Liu19580e62007-09-18 12:37:57 +0800426#define TSEC1_PHYIDX 0
427#define TSEC2_PHYIDX 0
428#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
429#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
430
431/* Options are: TSEC[0-1] */
432#define CONFIG_ETHPRIME "eTSEC1"
433
Dave Liu6f8c85e2008-03-26 22:56:36 +0800434/* SERDES */
435#define CONFIG_FSL_SERDES
436#define CONFIG_FSL_SERDES1 0xe3000
437#define CONFIG_FSL_SERDES2 0xe3100
438
Dave Liu19580e62007-09-18 12:37:57 +0800439/*
Dave Liu2eeb3e42008-03-26 22:57:19 +0800440 * SATA
441 */
442#define CONFIG_LIBATA
443#define CONFIG_FSL_SATA
444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_SATA_MAX_DEVICE 2
Dave Liu2eeb3e42008-03-26 22:57:19 +0800446#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger8d858082011-10-11 23:57:18 -0500448#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
449#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800450#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger8d858082011-10-11 23:57:18 -0500452#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
453#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Dave Liu2eeb3e42008-03-26 22:57:19 +0800454
455#ifdef CONFIG_FSL_SATA
456#define CONFIG_LBA48
457#define CONFIG_CMD_SATA
458#define CONFIG_DOS_PARTITION
459#define CONFIG_CMD_EXT2
460#endif
461
462/*
Dave Liu19580e62007-09-18 12:37:57 +0800463 * Environment
464 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200466 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger8d858082011-10-11 23:57:18 -0500467 #define CONFIG_ENV_ADDR \
468 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200469 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
470 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800471#else
Joe Hershberger8d858082011-10-11 23:57:18 -0500472 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200473 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200475 #define CONFIG_ENV_SIZE 0x2000
Dave Liu19580e62007-09-18 12:37:57 +0800476#endif
477
478#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu19580e62007-09-18 12:37:57 +0800480
481/*
482 * BOOTP options
483 */
484#define CONFIG_BOOTP_BOOTFILESIZE
485#define CONFIG_BOOTP_BOOTPATH
486#define CONFIG_BOOTP_GATEWAY
487#define CONFIG_BOOTP_HOSTNAME
488
489
490/*
491 * Command line configuration.
492 */
Dave Liu19580e62007-09-18 12:37:57 +0800493#define CONFIG_CMD_PING
494#define CONFIG_CMD_I2C
495#define CONFIG_CMD_MII
496#define CONFIG_CMD_DATE
497
498#if defined(CONFIG_PCI)
499 #define CONFIG_CMD_PCI
500#endif
501
Dave Liu19580e62007-09-18 12:37:57 +0800502#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500503#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu19580e62007-09-18 12:37:57 +0800504
505#undef CONFIG_WATCHDOG /* watchdog disabled */
506
Andy Fleminge1ac3872008-10-30 16:50:14 -0500507#define CONFIG_MMC 1
508
509#ifdef CONFIG_MMC
510#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800511#define CONFIG_FSL_ESDHC_PIN_MUX
Andy Fleminge1ac3872008-10-30 16:50:14 -0500512#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
513#define CONFIG_CMD_MMC
514#define CONFIG_GENERIC_MMC
515#define CONFIG_CMD_EXT2
516#define CONFIG_CMD_FAT
517#define CONFIG_DOS_PARTITION
518#endif
519
Dave Liu19580e62007-09-18 12:37:57 +0800520/*
521 * Miscellaneous configurable options
522 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_LONGHELP /* undef to save memory */
524#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dave Liu19580e62007-09-18 12:37:57 +0800525
526#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800528#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200529 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu19580e62007-09-18 12:37:57 +0800530#endif
531
Joe Hershberger8d858082011-10-11 23:57:18 -0500532 /* Print Buffer Size */
533#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
534#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
535 /* Boot Argument Buffer Size */
536#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Dave Liu19580e62007-09-18 12:37:57 +0800537
538/*
539 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700540 * have to be in the first 256 MB of memory, since this is
Dave Liu19580e62007-09-18 12:37:57 +0800541 * the maximum mapped by the Linux kernel during initialization.
542 */
Joe Hershberger8d858082011-10-11 23:57:18 -0500543#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Dave Liu19580e62007-09-18 12:37:57 +0800544
545/*
546 * Core HID Setup
547 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500548#define CONFIG_SYS_HID0_INIT 0x000000000
549#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
550 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200551#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu19580e62007-09-18 12:37:57 +0800552
553/*
Dave Liu19580e62007-09-18 12:37:57 +0800554 * MMU Setup
555 */
Becky Bruce31d82672008-05-08 19:02:12 -0500556#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu19580e62007-09-18 12:37:57 +0800557
558/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200559#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
560#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Dave Liu19580e62007-09-18 12:37:57 +0800561
Joe Hershberger8d858082011-10-11 23:57:18 -0500562#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500563 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500564 | BATL_MEMCOHERENCE)
565#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
566 | BATU_BL_256M \
567 | BATU_VS \
568 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200569#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
570#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu19580e62007-09-18 12:37:57 +0800571
Joe Hershberger8d858082011-10-11 23:57:18 -0500572#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500573 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500574 | BATL_MEMCOHERENCE)
575#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
576 | BATU_BL_256M \
577 | BATU_VS \
578 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200579#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
580#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu19580e62007-09-18 12:37:57 +0800581
582/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500583#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500584 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500585 | BATL_CACHEINHIBIT \
586 | BATL_GUARDEDSTORAGE)
587#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
588 | BATU_BL_8M \
589 | BATU_VS \
590 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200591#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
592#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu19580e62007-09-18 12:37:57 +0800593
594/* BCSR: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500595#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500596 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500597 | BATL_CACHEINHIBIT \
598 | BATL_GUARDEDSTORAGE)
599#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
600 | BATU_BL_128K \
601 | BATU_VS \
602 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200603#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
604#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu19580e62007-09-18 12:37:57 +0800605
606/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500607#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500608 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500609 | BATL_MEMCOHERENCE)
610#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
611 | BATU_BL_32M \
612 | BATU_VS \
613 | BATU_VP)
614#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500615 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500616 | BATL_CACHEINHIBIT \
617 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu19580e62007-09-18 12:37:57 +0800619
620/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500621#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger8d858082011-10-11 23:57:18 -0500622#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
623 | BATU_BL_128K \
624 | BATU_VS \
625 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200626#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
627#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu19580e62007-09-18 12:37:57 +0800628
629#ifdef CONFIG_PCI
630/* PCI MEM space: cacheable */
Joe Hershberger8d858082011-10-11 23:57:18 -0500631#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500632 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500633 | BATL_MEMCOHERENCE)
634#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
635 | BATU_BL_256M \
636 | BATU_VS \
637 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200638#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
639#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu19580e62007-09-18 12:37:57 +0800640/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger8d858082011-10-11 23:57:18 -0500641#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500642 | BATL_PP_RW \
Joe Hershberger8d858082011-10-11 23:57:18 -0500643 | BATL_CACHEINHIBIT \
644 | BATL_GUARDEDSTORAGE)
645#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
646 | BATU_BL_256M \
647 | BATU_VS \
648 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200649#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
650#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800651#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200652#define CONFIG_SYS_IBAT6L (0)
653#define CONFIG_SYS_IBAT6U (0)
654#define CONFIG_SYS_IBAT7L (0)
655#define CONFIG_SYS_IBAT7U (0)
656#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
657#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
658#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
659#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu19580e62007-09-18 12:37:57 +0800660#endif
661
Dave Liu19580e62007-09-18 12:37:57 +0800662#if defined(CONFIG_CMD_KGDB)
663#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Dave Liu19580e62007-09-18 12:37:57 +0800664#endif
665
666/*
667 * Environment Configuration
668 */
669
670#define CONFIG_ENV_OVERWRITE
671
672#if defined(CONFIG_TSEC_ENET)
673#define CONFIG_HAS_ETH0
Dave Liu19580e62007-09-18 12:37:57 +0800674#define CONFIG_HAS_ETH1
Dave Liu19580e62007-09-18 12:37:57 +0800675#endif
676
677#define CONFIG_BAUDRATE 115200
678
Kim Phillips79f516b2009-08-21 16:34:38 -0500679#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu19580e62007-09-18 12:37:57 +0800680
681#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
682#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
683
684#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger8d858082011-10-11 23:57:18 -0500685 "netdev=eth0\0" \
686 "consoledev=ttyS0\0" \
687 "ramdiskaddr=1000000\0" \
688 "ramdiskfile=ramfs.83xx\0" \
689 "fdtaddr=780000\0" \
690 "fdtfile=mpc8379_mds.dtb\0" \
691 ""
Dave Liu19580e62007-09-18 12:37:57 +0800692
693#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger8d858082011-10-11 23:57:18 -0500694 "setenv bootargs root=/dev/nfs rw " \
695 "nfsroot=$serverip:$rootpath " \
696 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
697 "$netdev:off " \
698 "console=$consoledev,$baudrate $othbootargs;" \
699 "tftp $loadaddr $bootfile;" \
700 "tftp $fdtaddr $fdtfile;" \
701 "bootm $loadaddr - $fdtaddr"
Dave Liu19580e62007-09-18 12:37:57 +0800702
703#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger8d858082011-10-11 23:57:18 -0500704 "setenv bootargs root=/dev/ram rw " \
705 "console=$consoledev,$baudrate $othbootargs;" \
706 "tftp $ramdiskaddr $ramdiskfile;" \
707 "tftp $loadaddr $bootfile;" \
708 "tftp $fdtaddr $fdtfile;" \
709 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu19580e62007-09-18 12:37:57 +0800710
711
712#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
713
714#endif /* __CONFIG_H */