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Wolfgang Denk460c3222005-08-04 01:14:12 +02001/* ported from ctfb.c (linux kernel):
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02002 * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
Wolfgang Denk460c3222005-08-04 01:14:12 +02003 *
4 * Ported to U-Boot:
5 * (C) Copyright 2002 Denis Peter, MPL AG Switzerland
wdenkc6097192002-11-03 00:24:07 +00006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00008 */
9
wdenkc6097192002-11-03 00:24:07 +000010#include <common.h>
11
12#ifdef CONFIG_VIDEO
13
14#include <pci.h>
15#include <video_fb.h>
wdenkeeb1b772004-03-23 22:53:55 +000016#include "videomodes.h"
wdenkc6097192002-11-03 00:24:07 +000017
wdenkc6097192002-11-03 00:24:07 +000018/* debug */
19#undef VGA_DEBUG
20#undef VGA_DUMP_REG
21#ifdef VGA_DEBUG
Wolfgang Denk8a2d1f22011-11-09 09:29:04 +000022#undef _DEBUG
23#define _DEBUG 1
wdenkc6097192002-11-03 00:24:07 +000024#else
Wolfgang Denk8a2d1f22011-11-09 09:29:04 +000025#undef _DEBUG
26#define _DEBUG 0
wdenkc6097192002-11-03 00:24:07 +000027#endif
28
29/* Macros */
30#ifndef min
31#define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
32#endif
33#ifndef max
34#define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b )
35#endif
36#ifdef minmax
37#error "term minmax already used."
38#endif
39#define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) )
40#define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) )
41
42/* CT Register Offsets */
43#define CT_AR_O 0x3c0 /* Index and Data write port of the attribute Registers */
44#define CT_GR_O 0x3ce /* Index port of the Graphic Controller Registers */
45#define CT_SR_O 0x3c4 /* Index port of the Sequencer Controller */
46#define CT_CR_O 0x3d4 /* Index port of the CRT Controller */
47#define CT_XR_O 0x3d6 /* Extended Register index */
48#define CT_MSR_W_O 0x3c2 /* Misc. Output Register (write only) */
49#define CT_LUT_MASK_O 0x3c6 /* Color Palette Mask */
50#define CT_LUT_START_O 0x3c8 /* Color Palette Write Mode Index */
51#define CT_LUT_RGB_O 0x3c9 /* Color Palette Data Port */
52#define CT_STATUS_REG0_O 0x3c2 /* Status Register 0 (read only) */
53#define CT_STATUS_REG1_O 0x3da /* Input Status Register 1 (read only) */
54
55#define CT_FP_O 0x3d0 /* Index port of the Flat panel Registers */
56#define CT_MR_O 0x3d2 /* Index Port of the Multimedia Extension */
57
58/* defines for the memory mapped registers */
59#define BR00_o 0x400000 /* Source and Destination Span Register */
60#define BR01_o 0x400004 /* Pattern/Source Expansion Background Color & Transparency Key Register */
61#define BR02_o 0x400008 /* Pattern/Source Expansion Foreground Color Register */
62#define BR03_o 0x40000C /* Monochrome Source Control Register */
63#define BR04_o 0x400010 /* BitBLT Control Register */
64#define BR05_o 0x400014 /* Pattern Address Registe */
65#define BR06_o 0x400018 /* Source Address Register */
66#define BR07_o 0x40001C /* Destination Address Register */
67#define BR08_o 0x400020 /* Destination Width & Height Register */
68#define BR09_o 0x400024 /* Source Expansion Background Color & Transparency Key Register */
69#define BR0A_o 0x400028 /* Source Expansion Foreground Color Register */
70
71#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
72#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
73#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
74#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
75
76/* Some Mode definitions */
77#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
78#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
79#define FB_SYNC_EXT 4 /* external sync */
80#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
81#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
82 /* vtotal = 144d/288n/576i => PAL */
83 /* vtotal = 121d/242n/484i => NTSC */
84#define FB_SYNC_ON_GREEN 32 /* sync on green */
85
86#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
87#define FB_VMODE_INTERLACED 1 /* interlaced */
88#define FB_VMODE_DOUBLE 2 /* double scan */
89#define FB_VMODE_MASK 255
90
91#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
92#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
93#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
94
95#define text 0
96#define fntwidth 8
97
98/* table for VGA Initialization */
99typedef struct {
100 const unsigned char reg;
101 const unsigned char val;
102} CT_CFG_TABLE;
103
104/* this table provides some basic initialisations such as Memory Clock etc */
105static CT_CFG_TABLE xreg[] = {
106 {0x09, 0x01}, /* CRT Controller Extensions Enable */
107 {0x0A, 0x02}, /* Frame Buffer Mapping */
108 {0x0B, 0x01}, /* PCI Write Burst support */
109 {0x20, 0x00}, /* BitBLT Configuration */
110 {0x40, 0x03}, /* Memory Access Control */
111 {0x60, 0x00}, /* Video Pin Control */
112 {0x61, 0x00}, /* DPMS Synch control */
113 {0x62, 0x00}, /* GPIO Pin Control */
114 {0x63, 0xBD}, /* GPIO Pin Data */
115 {0x67, 0x00}, /* Pin Tri-State */
116 {0x80, 0x80}, /* Pixel Pipeline Config 0 register */
117 {0xA0, 0x00}, /* Cursor 1 Control Reg */
118 {0xA1, 0x00}, /* Cursor 1 Vertical Extension Reg */
119 {0xA2, 0x00}, /* Cursor 1 Base Address Low */
120 {0xA3, 0x00}, /* Cursor 1 Base Address High */
121 {0xA4, 0x00}, /* Cursor 1 X-Position Low */
122 {0xA5, 0x00}, /* Cursor 1 X-Position High */
123 {0xA6, 0x00}, /* Cursor 1 Y-Position Low */
124 {0xA7, 0x00}, /* Cursor 1 Y-Position High */
125 {0xA8, 0x00}, /* Cursor 2 Control Reg */
126 {0xA9, 0x00}, /* Cursor 2 Vertical Extension Reg */
127 {0xAA, 0x00}, /* Cursor 2 Base Address Low */
128 {0xAB, 0x00}, /* Cursor 2 Base Address High */
129 {0xAC, 0x00}, /* Cursor 2 X-Position Low */
130 {0xAD, 0x00}, /* Cursor 2 X-Position High */
131 {0xAE, 0x00}, /* Cursor 2 Y-Position Low */
132 {0xAF, 0x00}, /* Cursor 2 Y-Position High */
133 {0xC0, 0x7D}, /* Dot Clock 0 VCO M-Divisor */
134 {0xC1, 0x07}, /* Dot Clock 0 VCO N-Divisor */
135 {0xC3, 0x34}, /* Dot Clock 0 Divisor select */
136 {0xC4, 0x55}, /* Dot Clock 1 VCO M-Divisor */
137 {0xC5, 0x09}, /* Dot Clock 1 VCO N-Divisor */
138 {0xC7, 0x24}, /* Dot Clock 1 Divisor select */
139 {0xC8, 0x7D}, /* Dot Clock 2 VCO M-Divisor */
140 {0xC9, 0x07}, /* Dot Clock 2 VCO N-Divisor */
141 {0xCB, 0x34}, /* Dot Clock 2 Divisor select */
142 {0xCC, 0x38}, /* Memory Clock 0 VCO M-Divisor */
143 {0xCD, 0x03}, /* Memory Clock 0 VCO N-Divisor */
144 {0xCE, 0x90}, /* Memory Clock 0 Divisor select */
145 {0xCF, 0x06}, /* Clock Config */
146 {0xD0, 0x0F}, /* Power Down */
147 {0xD1, 0x01}, /* Power Down BitBLT */
148 {0xFF, 0xFF} /* end of table */
149};
150/* Clock Config:
151 * =============
152 *
153 * PD Registers:
154 * -------------
155 * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor.
156 * They are encoded as follows:
157 *
158 * +---+--------------+
159 * | 2 | Loop Divisor |
160 * +---+--------------+
161 * | 1 | 1 |
162 * +---+--------------+
163 * | 0 | 4 |
164 * +---+--------------+
165 * Note: The Memory Clock does not have a Loop Divisor.
166 * +---+---+---+--------------+
167 * | 6 | 5 | 4 | Post Divisor |
168 * +---+---+---+--------------+
169 * | 0 | 0 | 0 | 1 |
170 * +---+---+---+--------------+
171 * | 0 | 0 | 1 | 2 |
172 * +---+---+---+--------------+
173 * | 0 | 1 | 0 | 4 |
174 * +---+---+---+--------------+
175 * | 0 | 1 | 1 | 8 |
176 * +---+---+---+--------------+
177 * | 1 | 0 | 0 | 16 |
178 * +---+---+---+--------------+
179 * | 1 | 0 | 1 | 32 |
180 * +---+---+---+--------------+
181 * | 1 | 1 | X | reserved |
182 * +---+---+---+--------------+
183 *
184 * All other bits are reserved in these registers.
185 *
186 * Clock VCO M Registers:
187 * ----------------------
188 * These Registers contain the M Value -2.
189 *
190 * Clock VCO N Registers:
191 * ----------------------
192 * These Registers contain the N Value -2.
193 *
194 * Formulas:
195 * ---------
196 * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz
197 * Fout = Fvco / Post Divisor
198 *
199 * Dot Clk0 (default 25MHz):
200 * -------------------------
201 * Fvco = 14.318 * 127 / 9 = 202.045MHz
202 * Fout = 202.045MHz / 8 = 25.25MHz
203 * Post Divisor = 8
204 * Loop Divisor = 1
205 * XRC0 = (M - 2) = 125 = 0x7D
206 * XRC1 = (N - 2) = 7 = 0x07
207 * XRC3 = 0x34
208 *
209 * Dot Clk1 (default 28MHz):
210 * -------------------------
211 * Fvco = 14.318 * 87 / 11 = 113.24MHz
212 * Fout = 113.24MHz / 4 = 28.31MHz
213 * Post Divisor = 4
214 * Loop Divisor = 1
215 * XRC4 = (M - 2) = 85 = 0x55
216 * XRC5 = (N - 2) = 9 = 0x09
217 * XRC7 = 0x24
218 *
219 * Dot Clk2 (variable for extended modes set to 25MHz):
220 * ----------------------------------------------------
221 * Fvco = 14.318 * 127 / 9 = 202.045MHz
222 * Fout = 202.045MHz / 8 = 25.25MHz
223 * Post Divisor = 8
224 * Loop Divisor = 1
225 * XRC8 = (M - 2) = 125 = 0x7D
226 * XRC9 = (N - 2) = 7 = 0x07
227 * XRCB = 0x34
228 *
229 * Memory Clk for most modes >50MHz:
230 * ----------------------------------
231 * Fvco = 14.318 * 58 / 5 = 166MHz
232 * Fout = 166MHz / 2 = 83MHz
233 * Post Divisor = 2
234 * XRCC = (M - 2) = 57 = 0x38
235 * XRCD = (N - 2) = 3 = 0x03
236 * XRCE = 0x90
237 *
238 * Note Bit7 enables the clock source from the VCO
239 *
240 */
241
wdenkc6097192002-11-03 00:24:07 +0000242/*******************************************************************
243 * Chips struct
244 *******************************************************************/
245struct ctfb_chips_properties {
246 int device_id; /* PCI Device ID */
247 unsigned long max_mem; /* memory for frame buffer */
248 int vld_set; /* value of VLD if bit2 in clock control is set */
249 int vld_not_set; /* value of VLD if bit2 in clock control is set */
250 int mn_diff; /* difference between M/N Value + mn_diff = M/N Register */
251 int mn_min; /* min value of M/N Value */
252 int mn_max; /* max value of M/N Value */
253 int vco_min; /* VCO Min in MHz */
254 int vco_max; /* VCO Max in MHz */
255};
256
257static const struct ctfb_chips_properties chips[] = {
258 {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
Stefan Roesea7b9fb92006-01-18 20:05:34 +0100259#ifdef CONFIG_USE_CPCIDVI
260 {PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220},
261#endif
wdenkc6097192002-11-03 00:24:07 +0000262 {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
263 {0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
264};
265
wdenkc6097192002-11-03 00:24:07 +0000266/*
267 * The Graphic Device
268 */
269GraphicDevice ctfb;
270
271/*******************************************************************************
272*
273* Low Level Routines
274*/
275
276/*******************************************************************************
277*
278* Read CT ISA register
279*/
280#ifdef VGA_DEBUG
281static unsigned char
282ctRead (unsigned short index)
283{
284 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
285 if (index == CT_AR_O)
286 /* synch the Flip Flop */
287 in8 (pGD->isaBase + CT_STATUS_REG1_O);
288
289 return (in8 (pGD->isaBase + index));
290}
291#endif
292/*******************************************************************************
293*
294* Write CT ISA register
295*/
296static void
297ctWrite (unsigned short index, unsigned char val)
298{
299 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
300
301 out8 ((pGD->isaBase + index), val);
302}
303
304/*******************************************************************************
305*
306* Read CT ISA register indexed
307*/
308static unsigned char
309ctRead_i (unsigned short index, char reg)
310{
311 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
312 if (index == CT_AR_O)
313 /* synch the Flip Flop */
314 in8 (pGD->isaBase + CT_STATUS_REG1_O);
315 out8 ((pGD->isaBase + index), reg);
316 return (in8 (pGD->isaBase + index + 1));
317}
318
319/*******************************************************************************
320*
321* Write CT ISA register indexed
322*/
323static void
324ctWrite_i (unsigned short index, char reg, char val)
325{
326 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
327 if (index == CT_AR_O) {
328 /* synch the Flip Flop */
329 in8 (pGD->isaBase + CT_STATUS_REG1_O);
330 out8 ((pGD->isaBase + index), reg);
331 out8 ((pGD->isaBase + index), val);
332 } else {
333 out8 ((pGD->isaBase + index), reg);
334 out8 ((pGD->isaBase + index + 1), val);
335 }
336}
337
338/*******************************************************************************
339*
340* Write a table of CT ISA register
341*/
342static void
343ctLoadRegs (unsigned short index, CT_CFG_TABLE * regTab)
344{
345 while (regTab->reg != 0xFF) {
346 ctWrite_i (index, regTab->reg, regTab->val);
347 regTab++;
348 }
349}
350
351/*****************************************************************************/
352static void
353SetArRegs (void)
354{
355 int i, tmp;
356
357 for (i = 0; i < 0x10; i++)
358 ctWrite_i (CT_AR_O, i, i);
359 if (text)
360 tmp = 0x04;
361 else
362 tmp = 0x41;
363
364 ctWrite_i (CT_AR_O, 0x10, tmp); /* Mode Control Register */
365 ctWrite_i (CT_AR_O, 0x11, 0x00); /* Overscan Color Register */
366 ctWrite_i (CT_AR_O, 0x12, 0x0f); /* Memory Plane Enable Register */
367 if (fntwidth == 9)
368 tmp = 0x08;
369 else
370 tmp = 0x00;
371 ctWrite_i (CT_AR_O, 0x13, tmp); /* Horizontal Pixel Panning */
372 ctWrite_i (CT_AR_O, 0x14, 0x00); /* Color Select Register */
373 ctWrite (CT_AR_O, 0x20); /* enable video */
374}
375
376/*****************************************************************************/
377static void
378SetGrRegs (void)
379{ /* Set Graphics Mode */
380 int i;
381
382 for (i = 0; i < 0x05; i++)
383 ctWrite_i (CT_GR_O, i, 0);
384 if (text) {
385 ctWrite_i (CT_GR_O, 0x05, 0x10);
386 ctWrite_i (CT_GR_O, 0x06, 0x02);
387 } else {
388 ctWrite_i (CT_GR_O, 0x05, 0x40);
389 ctWrite_i (CT_GR_O, 0x06, 0x05);
390 }
391 ctWrite_i (CT_GR_O, 0x07, 0x0f);
392 ctWrite_i (CT_GR_O, 0x08, 0xff);
393}
394
395/*****************************************************************************/
396static void
397SetSrRegs (void)
398{
399 int tmp = 0;
400
401 ctWrite_i (CT_SR_O, 0x00, 0x00); /* reset */
402 /*rr( sr, 0x01, tmp );
403 if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01;
404 wr( sr, 0x01, tmp ); */
405 if (fntwidth == 8)
406 ctWrite_i (CT_SR_O, 0x01, 0x01); /* Clocking Mode Register */
407 else
408 ctWrite_i (CT_SR_O, 0x01, 0x00); /* Clocking Mode Register */
409 ctWrite_i (CT_SR_O, 0x02, 0x0f); /* Enable CPU wr access to given memory plane */
410 ctWrite_i (CT_SR_O, 0x03, 0x00); /* Character Map Select Register */
411 if (text)
412 tmp = 0x02;
413 else
414 tmp = 0x0e;
415 ctWrite_i (CT_SR_O, 0x04, tmp); /* Enable CPU accesses to the rest of the 256KB
416 total VGA memory beyond the first 64KB and set
417 fb mapping mode. */
418 ctWrite_i (CT_SR_O, 0x00, 0x03); /* enable */
419}
420
421/*****************************************************************************/
422static void
423SetBitsPerPixelIntoXrRegs (int bpp)
424{
425 unsigned int n = (bpp >> 3), tmp; /* only for 15, 8, 16, 24 bpp */
426 static char md[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */
427 static char off[4] = { ~0x20, ~0x30, ~0x20, ~0x10 }; /* mask */
428 static char on[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */
429 if (bpp == 15)
430 n = 0;
431 tmp = ctRead_i (CT_XR_O, 0x20);
432 tmp &= off[n];
433 tmp |= on[n];
434 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
435 ctWrite_i (CT_XR_O, 0x81, md[n]);
436}
437
438/*****************************************************************************/
439static void
440SetCrRegs (struct ctfb_res_modes *var, int bits_per_pixel)
441{ /* he -le- ht|0 hd -ri- hs -h- he */
442 unsigned char cr[0x7a];
443 int i, tmp;
444 unsigned int hd, hs, he, ht, hbe; /* Horizontal. */
445 unsigned int vd, vs, ve, vt; /* vertical */
446 unsigned int bpp, wd, dblscan, interlaced, bcast, CrtHalfLine;
447 unsigned int CompSyncCharClkDelay, CompSyncPixelClkDelay;
448 unsigned int NTSC_PAL_HorizontalPulseWidth, BlDelayCtrl;
449 unsigned int HorizontalEqualizationPulses;
450 unsigned int HorizontalSerration1Start, HorizontalSerration2Start;
451
452 const int LineCompare = 0x3ff;
453 unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */
454 unsigned int RAMDAC_BlankPedestalEnable = 0; /* 1=en-, 0=disable, see XR82 */
455
456 hd = (var->xres) / 8; /* HDisp. */
457 hs = (var->xres + var->right_margin) / 8; /* HsStrt */
458 he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */
459 ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */
460 hbe = ht - 1; /* HBlankEnable todo docu wants ht here, but it does not work */
461 /* ve -up- vt|0 vd -lo- vs -v- ve */
462 vd = var->yres; /* VDisplay */
463 vs = var->yres + var->lower_margin; /* VSyncStart */
464 ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */
465 vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */
466 bpp = bits_per_pixel;
467 dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0;
468 interlaced = var->vmode & FB_VMODE_INTERLACED;
469 bcast = var->sync & FB_SYNC_BROADCAST;
470 CrtHalfLine = bcast ? (hd >> 1) : 0;
471 BlDelayCtrl = bcast ? 1 : 0;
472 CompSyncCharClkDelay = 0; /* 2 bit */
473 CompSyncPixelClkDelay = 0; /* 3 bit */
474 if (bcast) {
475 NTSC_PAL_HorizontalPulseWidth = 7; /*( var->hsync_len >> 1 ) + 1 */
476 HorizontalEqualizationPulses = 0; /* inverse value */
477 HorizontalSerration1Start = 31; /* ( ht >> 1 ) */
478 HorizontalSerration2Start = 89; /* ( ht >> 1 ) */
479 } else {
480 NTSC_PAL_HorizontalPulseWidth = 0;
481 /* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] )
482 * / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */
483 HorizontalEqualizationPulses = 1; /* inverse value */
484 HorizontalSerration1Start = 0; /* ( ht >> 1 ) */
485 HorizontalSerration2Start = 0; /* ( ht >> 1 ) */
486 }
487
488 if (bpp == 15)
489 bpp = 16;
490 wd = var->xres * bpp / 64; /* double words per line */
491 if (interlaced) { /* we divide all vertical timings, exept vd */
492 vs >>= 1;
493 ve >>= 1;
494 vt >>= 1;
495 }
496 memset (cr, 0, sizeof (cr));
497 cr[0x00] = 0xff & (ht - 5);
498 cr[0x01] = hd - 1; /* soll:4f ist 59 */
499 cr[0x02] = hd;
500 cr[0x03] = (hbe & 0x1F) | 0x80; /* hd + ht - hd */
501 cr[0x04] = hs;
502 cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
503 cr[0x06] = (vt - 2) & 0xFF;
504 cr[0x30] = (vt - 2) >> 8;
505 cr[0x07] = ((vt & 0x100) >> 8)
506 | ((vd & 0x100) >> 7)
507 | ((vs & 0x100) >> 6)
508 | ((vs & 0x100) >> 5)
509 | ((LineCompare & 0x100) >> 4)
510 | ((vt & 0x200) >> 4)
511 | ((vd & 0x200) >> 3)
512 | ((vs & 0x200) >> 2);
513 cr[0x08] = 0x00;
514 cr[0x09] = (dblscan << 7)
515 | ((LineCompare & 0x200) >> 3)
516 | ((vs & 0x200) >> 4)
517 | (TextScanLines - 1);
518 cr[0x10] = vs & 0xff; /* VSyncPulseStart */
519 cr[0x32] = (vs & 0xf00) >> 8; /* VSyncPulseStart */
520 cr[0x11] = (ve & 0x0f); /* | 0x20; */
521 cr[0x12] = (vd - 1) & 0xff; /* LineCount */
522 cr[0x31] = ((vd - 1) & 0xf00) >> 8; /* LineCount */
523 cr[0x13] = wd & 0xff;
524 cr[0x41] = (wd & 0xf00) >> 8;
525 cr[0x15] = vs & 0xff;
526 cr[0x33] = (vs & 0xf00) >> 8;
527 cr[0x38] = (0x100 & (ht - 5)) >> 8;
528 cr[0x3C] = 0xc0 & hbe;
529 cr[0x16] = (vt - 1) & 0xff; /* vbe - docu wants vt here, */
530 cr[0x17] = 0xe3; /* but it does not work */
531 cr[0x18] = 0xff & LineCompare;
532 cr[0x22] = 0xff; /* todo? */
533 cr[0x70] = interlaced ? (0x80 | CrtHalfLine) : 0x00; /* check:0xa6 */
534 cr[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable << 6)
535 | (BlDelayCtrl << 5)
536 | ((0x03 & CompSyncCharClkDelay) << 3)
537 | (0x07 & CompSyncPixelClkDelay); /* todo: see XR82 */
538 cr[0x72] = HorizontalSerration1Start;
539 cr[0x73] = HorizontalSerration2Start;
540 cr[0x74] = (HorizontalEqualizationPulses << 5)
541 | NTSC_PAL_HorizontalPulseWidth;
542 /* todo: ct69000 has also 0x75-79 */
543 /* now set the registers */
544 for (i = 0; i <= 0x0d; i++) { /*CR00 .. CR0D */
545 ctWrite_i (CT_CR_O, i, cr[i]);
546 }
547 for (i = 0x10; i <= 0x18; i++) { /*CR10 .. CR18 */
548 ctWrite_i (CT_CR_O, i, cr[i]);
549 }
550 i = 0x22; /*CR22 */
551 ctWrite_i (CT_CR_O, i, cr[i]);
552 for (i = 0x30; i <= 0x33; i++) { /*CR30 .. CR33 */
553 ctWrite_i (CT_CR_O, i, cr[i]);
554 }
555 i = 0x38; /*CR38 */
556 ctWrite_i (CT_CR_O, i, cr[i]);
557 i = 0x3C; /*CR3C */
558 ctWrite_i (CT_CR_O, i, cr[i]);
559 for (i = 0x40; i <= 0x41; i++) { /*CR40 .. CR41 */
560 ctWrite_i (CT_CR_O, i, cr[i]);
561 }
562 for (i = 0x70; i <= 0x74; i++) { /*CR70 .. CR74 */
563 ctWrite_i (CT_CR_O, i, cr[i]);
564 }
565 tmp = ctRead_i (CT_CR_O, 0x40);
566 tmp &= 0x0f;
567 tmp |= 0x80;
568 ctWrite_i (CT_CR_O, 0x40, tmp); /* StartAddressEnable */
569}
570
571/* pixelclock control */
572
573/*****************************************************************************
574 We have a rational number p/q and need an m/n which is very close to p/q
575 but has m and n within mnmin and mnmax. We have no floating point in the
576 kernel. We can use long long without divide. And we have time to compute...
577******************************************************************************/
578static unsigned int
579FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin,
580 unsigned int mnmax, unsigned int *pm, unsigned int *pn)
581{
582 /* this code is not for general purpose usable but good for our number ranges */
583 unsigned int n = mnmin, m = 0;
584 long long int L = 0, P = p, Q = q, H = P >> 1;
585 long long int D = 0x7ffffffffffffffLL;
586 for (n = mnmin; n <= mnmax; n++) {
587 m = mnmin; /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */
588 L = P * n - m * Q; /* n * vco - m * fref should be near 0 */
589 while (L > 0 && m < mnmax) {
590 L -= q; /* difference is greater as 0 subtract fref */
591 m++; /* and increment m */
592 }
593 /* difference is less or equal than 0 or m > maximum */
594 if (m > mnmax)
595 break; /* no solution: if we increase n we get the same situation */
596 /* L is <= 0 now */
597 if (-L > H && m > mnmin) { /* if difference > the half fref */
598 L += q; /* we take the situation before */
599 m--; /* because its closer to 0 */
600 }
601 L = (L < 0) ? -L : +L; /* absolute value */
602 if (D < L) /* if last difference was better take next n */
603 continue;
604 D = L;
605 *pm = m;
606 *pn = n; /* keep improved data */
607 if (D == 0)
608 break; /* best result we can get */
609 }
610 return (unsigned int) (0xffffffff & D);
611}
612
613/* that is the hardware < 69000 we have to manage
614 +---------+ +-------------------+ +----------------------+ +--+
Albert ARIBAUDfa82f872011-08-04 18:45:45 +0200615 | REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
616 | 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | |
wdenkc6097192002-11-03 00:24:07 +0000617 +---------+ +-------------------+ +----------------------+ +--+ |
618 ___________________________________________________________________|
619 |
620 | fvco fout
621 | +--------+ +------------+ +-----+ +-------------------+ +----+
622 +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
Albert ARIBAUDfa82f872011-08-04 18:45:45 +0200623 +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
wdenkc6097192002-11-03 00:24:07 +0000624 | +--------+ +------------+ +-----+ | +-------------------+ +----+
625 | |
626 | +--+ +---------------+ |
Albert ARIBAUDfa82f872011-08-04 18:45:45 +0200627 |____|÷M|___|VCO Loop Divide|__________|
628 | | |(VLD)(÷4, ÷16) |
wdenkc6097192002-11-03 00:24:07 +0000629 +--+ +---------------+
630****************************************************************************
631 that is the hardware >= 69000 we have to manage
632 +---------+ +--+
Albert ARIBAUDfa82f872011-08-04 18:45:45 +0200633 | REFCLK |__|÷N|__
wdenkc6097192002-11-03 00:24:07 +0000634 | 14.3MHz | | | |
635 +---------+ +--+ |
636 __________________|
637 |
638 | fvco fout
639 | +--------+ +------------+ +-----+ +-------------------+ +----+
640 +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
Albert ARIBAUDfa82f872011-08-04 18:45:45 +0200641 +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
wdenkc6097192002-11-03 00:24:07 +0000642 | +--------+ +------------+ +-----+ | +-------------------+ +----+
643 | |
644 | +--+ +---------------+ |
Albert ARIBAUDfa82f872011-08-04 18:45:45 +0200645 |____|÷M|___|VCO Loop Divide|__________|
646 | | |(VLD)(÷1, ÷4) |
wdenkc6097192002-11-03 00:24:07 +0000647 +--+ +---------------+
648
649
650*/
651
652#define VIDEO_FREF 14318180; /* Hz */
653/*****************************************************************************/
654static int
655ReadPixClckFromXrRegsBack (struct ctfb_chips_properties *param)
656{
657 unsigned int m, n, vld, pd, PD, fref, xr_cb, i, pixclock;
658 i = 0;
659 pixclock = -1;
660 fref = VIDEO_FREF;
661 m = ctRead_i (CT_XR_O, 0xc8);
662 n = ctRead_i (CT_XR_O, 0xc9);
663 m -= param->mn_diff;
664 n -= param->mn_diff;
665 xr_cb = ctRead_i (CT_XR_O, 0xcb);
666 PD = (0x70 & xr_cb) >> 4;
667 pd = 1;
668 for (i = 0; i < PD; i++) {
669 pd *= 2;
670 }
671 vld = (0x04 & xr_cb) ? param->vld_set : param->vld_not_set;
672 if (n * vld * m) {
673 unsigned long long p = 1000000000000LL * pd * n;
674 unsigned long long q = (long long) fref * vld * m;
675 while ((p > 0xffffffffLL) || (q > 0xffffffffLL)) {
676 p >>= 1; /* can't divide with long long so we scale down */
677 q >>= 1;
678 }
679 pixclock = (unsigned) p / (unsigned) q;
680 } else
681 printf ("Invalid data in xr regs.\n");
682 return pixclock;
683}
684
685/*****************************************************************************/
686static void
687FindAndSetPllParamIntoXrRegs (unsigned int pixelclock,
688 struct ctfb_chips_properties *param)
689{
690 unsigned int m, n, vld, pd, PD, fref, xr_cb;
691 unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk;
692 unsigned int pfreq, fvco, new_pixclock;
wdenk3e386912003-04-05 00:53:31 +0000693 unsigned int D,nback,mback;
wdenkc6097192002-11-03 00:24:07 +0000694
695 fref = VIDEO_FREF;
696 pd = 1;
697 PD = 0;
698 fvcomin = param->vco_min;
699 fvcomax = param->vco_max; /* MHz */
700 pclckmin = 1000000 / fvcomax + 1; /* 4546 */
701 pclckmax = 32000000 / fvcomin - 1; /* 666665 */
702 pclk = minmax (pclckmin, pixelclock, pclckmax); /* ps pp */
703 pfreq = 250 * (4000000000U / pclk);
704 fvco = pfreq; /* Hz */
705 new_pixclock = 0;
706 while (fvco < fvcomin * 1000000) {
707 /* double VCO starting with the pixelclock frequency
708 * as long as it is lower than the minimal VCO frequency */
709 fvco *= 2;
710 pd *= 2;
711 PD++;
712 }
713 /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */
wdenk3e386912003-04-05 00:53:31 +0000714 /* first try */
715 vld = param->vld_set;
716 D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */
717 mback=m;
718 nback=n;
719 /* second try */
720 vld = param->vld_not_set;
721 if(D<FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n)) { /* rds = 1 */
722 /* first try was better */
723 m=mback;
724 n=nback;
725 vld = param->vld_set;
726 }
wdenkc6097192002-11-03 00:24:07 +0000727 m += param->mn_diff;
728 n += param->mn_diff;
Wolfgang Denk8a2d1f22011-11-09 09:29:04 +0000729 debug("VCO %d, pd %d, m %d n %d vld %d\n", fvco, pd, m, n, vld);
wdenkc6097192002-11-03 00:24:07 +0000730 xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0);
731 /* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
732 * written, and in order from XRC8 to XRCB, before the hardware will
733 * update the synthesizer s settings.
734 */
735 ctWrite_i (CT_XR_O, 0xc8, m);
736 ctWrite_i (CT_XR_O, 0xc9, n); /* xrca does not exist in CT69000 and CT69030 */
737 ctWrite_i (CT_XR_O, 0xca, 0); /* because of a hw bug I guess, but we write */
738 ctWrite_i (CT_XR_O, 0xcb, xr_cb); /* 0 to it for savety */
739 new_pixclock = ReadPixClckFromXrRegsBack (param);
Wolfgang Denk8a2d1f22011-11-09 09:29:04 +0000740 debug("pixelclock.set = %d, pixelclock.real = %d\n",
wdenkc6097192002-11-03 00:24:07 +0000741 pixelclock, new_pixclock);
742}
743
744/*****************************************************************************/
745static void
746SetMsrRegs (struct ctfb_res_modes *mode)
747{
748 unsigned char h_synch_high, v_synch_high;
749
750 h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */
751 v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */
752 ctWrite (CT_MSR_W_O, (h_synch_high | v_synch_high | 0x29));
753 /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
754 * Selects the upper 64KB page.Bit5=1
755 * CLK2 (left reserved in standard VGA) Bit3|2=1|0
756 * Disables CPU access to frame buffer. Bit1=0
757 * Sets the I/O address decode for ST01, FCR, and all CR registers
758 * to the 3Dx I/O address range (CGA emulation). Bit0=1
759 */
760}
761
762/************************************************************************************/
763#ifdef VGA_DUMP_REG
764
765static void
766ctDispRegs (unsigned short index, int from, int to)
767{
768 unsigned char status;
769 int i;
770
771 for (i = from; i < to; i++) {
772 status = ctRead_i (index, i);
773 printf ("%02X: is %02X\n", i, status);
774 }
775}
776
777void
778video_dump_reg (void)
779{
780 int i;
781
782 printf ("Extended Regs:\n");
783 ctDispRegs (CT_XR_O, 0, 0xC);
784 ctDispRegs (CT_XR_O, 0xe, 0xf);
785 ctDispRegs (CT_XR_O, 0x20, 0x21);
786 ctDispRegs (CT_XR_O, 0x40, 0x50);
787 ctDispRegs (CT_XR_O, 0x60, 0x64);
788 ctDispRegs (CT_XR_O, 0x67, 0x68);
789 ctDispRegs (CT_XR_O, 0x70, 0x72);
790 ctDispRegs (CT_XR_O, 0x80, 0x83);
791 ctDispRegs (CT_XR_O, 0xA0, 0xB0);
792 ctDispRegs (CT_XR_O, 0xC0, 0xD3);
793 printf ("Sequencer Regs:\n");
794 ctDispRegs (CT_SR_O, 0, 0x8);
795 printf ("Graphic Regs:\n");
796 ctDispRegs (CT_GR_O, 0, 0x9);
797 printf ("CRT Regs:\n");
798 ctDispRegs (CT_CR_O, 0, 0x19);
799 ctDispRegs (CT_CR_O, 0x22, 0x23);
800 ctDispRegs (CT_CR_O, 0x30, 0x34);
801 ctDispRegs (CT_CR_O, 0x38, 0x39);
802 ctDispRegs (CT_CR_O, 0x3C, 0x3D);
803 ctDispRegs (CT_CR_O, 0x40, 0x42);
804 ctDispRegs (CT_CR_O, 0x70, 0x80);
805 /* don't display the attributes */
806}
807
808#endif
809
810#ifdef CONFIG_VIDEO_HW_CURSOR
811/***************************************************************
812 * Set Hardware Cursor in Pixel
813 */
814void
815video_set_hw_cursor (int x, int y)
816{
817 int sig_x = 0, sig_y = 0;
818 if (x < 0) {
819 x *= -1;
820 sig_x = 1;
821 }
822 if (y < 0) {
823 y *= -1;
824 sig_y = 1;
825 }
826 ctWrite_i (CT_XR_O, 0xa4, x & 0xff);
827 ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7);
828 ctWrite_i (CT_XR_O, 0xa6, y & 0xff);
829 ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7);
830}
831
832/***************************************************************
833 * Init Hardware Cursor. To know the size of the Cursor,
834 * we have to know the Font size.
835 */
836void
837video_init_hw_cursor (int font_width, int font_height)
838{
839 unsigned char xr_80;
840 unsigned long *curs, pattern;
841 int i;
842 int cursor_start;
843 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
844
845 cursor_start = pGD->dprBase;
846 xr_80 = ctRead_i (CT_XR_O, 0x80);
847 /* set start address */
848 ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0);
849 ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f);
850 /* set cursor shape */
851 curs = (unsigned long *) cursor_start;
852 i = 0;
853 while (i < 0x400) {
854 curs[i++] = 0xffffffff; /* AND mask */
855 curs[i++] = 0xffffffff; /* AND mask */
856 curs[i++] = 0; /* XOR mask */
857 curs[i++] = 0; /* XOR mask */
858 /* Transparent */
859 }
860 pattern = 0xffffffff >> font_width;
861 i = 0;
862 while (i < (font_height * 2)) {
863 curs[i++] = pattern; /* AND mask */
864 curs[i++] = pattern; /* AND mask */
865 curs[i++] = 0; /* XOR mask */
866 curs[i++] = 0; /* XOR mask */
867 /* Cursor Color 0 */
868 }
869 /* set blink rate */
870 ctWrite_i (CT_FP_O, 0x19, 0xf);
871
872 /* set cursors colors */
873 xr_80 = ctRead_i (CT_XR_O, 0x80);
874 xr_80 |= 0x1; /* alternate palette select */
875 ctWrite_i (CT_XR_O, 0x80, xr_80);
876 video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL);
877 /* position 4 is color 0 cursor 0 */
878 xr_80 &= 0xfe; /* normal palette select */
879 ctWrite_i (CT_XR_O, 0x80, xr_80);
880 /* cursor enable */
881 ctWrite_i (CT_XR_O, 0xa0, 0x91);
882 xr_80 |= 0x10; /* enable hwcursor */
883 ctWrite_i (CT_XR_O, 0x80, xr_80);
884 video_set_hw_cursor (0, 0);
885}
886#endif /* CONFIG_VIDEO_HW_CURSOR */
887
888/***************************************************************
889 * Wait for BitBlt ready
890 */
891static int
892video_wait_bitblt (unsigned long addr)
893{
894 unsigned long br04;
895 int i = 0;
896 br04 = in32r (addr);
897 while (br04 & 0x80000000) {
898 udelay (1);
899 br04 = in32r (addr);
900 if (i++ > 1000000) {
901 printf ("ERROR Timeout %lx\n", br04);
902 return 1;
903 }
904 }
905 return 0;
906}
907
908/***************************************************************
909 * Set up BitBlt Registrs
910 */
911static void
912SetDrawingEngine (int bits_per_pixel)
913{
914 unsigned long br04, br00;
915 unsigned char tmp;
916
917 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
918
919 tmp = ctRead_i (CT_XR_O, 0x20); /* BitBLT Configuration */
920 tmp |= 0x02; /* reset BitBLT */
921 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
922 udelay (10);
923 tmp &= 0xfd; /* release reset BitBLT */
924 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
925 video_wait_bitblt (pGD->pciBase + BR04_o);
926
927 /* set pattern Address */
928 out32r (pGD->pciBase + BR05_o, PATTERN_ADR & 0x003ffff8);
929 br04 = 0;
930 if (bits_per_pixel == 1) {
931 br04 |= 0x00040000; /* monochome Pattern */
932 br04 |= 0x00001000; /* monochome source */
933 }
934 br00 = ((pGD->winSizeX * pGD->gdfBytesPP) << 16) + (pGD->winSizeX * pGD->gdfBytesPP); /* bytes per scanline */
935 out32r (pGD->pciBase + BR00_o, br00); /* */
936 out32r (pGD->pciBase + BR08_o, (10 << 16) + 10); /* dummy */
937 out32r (pGD->pciBase + BR04_o, br04); /* write all 0 */
938 out32r (pGD->pciBase + BR07_o, 0); /* destination */
939 video_wait_bitblt (pGD->pciBase + BR04_o);
940}
941
wdenkc6097192002-11-03 00:24:07 +0000942/****************************************************************************
943* supported Video Chips
944*/
945static struct pci_device_id supported[] = {
946 {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
Stefan Roesea7b9fb92006-01-18 20:05:34 +0100947#ifdef CONFIG_USE_CPCIDVI
948 {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030},
949#endif
wdenkc6097192002-11-03 00:24:07 +0000950 {}
951};
952
953/*******************************************************************************
954*
955* Init video chip
956*/
957void *
958video_hw_init (void)
959{
960 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
961 unsigned short device_id;
962 pci_dev_t devbusfn;
963 int videomode;
964 unsigned long t1, hsynch, vsynch;
965 unsigned int pci_mem_base, *vm;
966 int tmp, i, bits_per_pixel;
967 char *penv;
968 struct ctfb_res_modes *res_mode;
969 struct ctfb_res_modes var_mode;
970 struct ctfb_chips_properties *chips_param;
971 /* Search for video chip */
972
973 if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
974#ifdef CONFIG_VIDEO_ONBOARD
975 printf ("Video: Controller not found !\n");
976#endif
977 return (NULL);
978 }
979
980 /* PCI setup */
981 pci_write_config_dword (devbusfn, PCI_COMMAND,
982 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
983 pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
984 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
985 pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base);
986
987 /* get chips params */
988 for (chips_param = (struct ctfb_chips_properties *) &chips[0];
989 chips_param->device_id != 0; chips_param++) {
990 if (chips_param->device_id == device_id)
991 break;
992 }
993 if (chips_param->device_id == 0) {
994#ifdef CONFIG_VIDEO_ONBOARD
995 printf ("Video: controller 0x%X not supported\n", device_id);
996#endif
997 return NULL;
998 }
999 /* supported Video controller found */
1000 printf ("Video: ");
1001
1002 tmp = 0;
1003 videomode = 0x301;
1004 /* get video mode via environment */
1005 if ((penv = getenv ("videomode")) != NULL) {
1006 /* deceide if it is a string */
1007 if (penv[0] <= '9') {
1008 videomode = (int) simple_strtoul (penv, NULL, 16);
1009 tmp = 1;
1010 }
1011 } else {
1012 tmp = 1;
1013 }
1014 if (tmp) {
1015 /* parameter are vesa modes */
1016 /* search params */
1017 for (i = 0; i < VESA_MODES_COUNT; i++) {
1018 if (vesa_modes[i].vesanr == videomode)
1019 break;
1020 }
1021 if (i == VESA_MODES_COUNT) {
1022 printf ("no VESA Mode found, switching to mode 0x301 ");
1023 i = 0;
1024 }
1025 res_mode =
1026 (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].
1027 resindex];
1028 bits_per_pixel = vesa_modes[i].bits_per_pixel;
1029 } else {
1030
1031 res_mode = (struct ctfb_res_modes *) &var_mode;
1032 bits_per_pixel = video_get_params (res_mode, penv);
1033 }
1034
1035 /* calculate available color depth for controller memory */
1036 if (bits_per_pixel == 15)
1037 tmp = 2;
1038 else
1039 tmp = bits_per_pixel >> 3; /* /8 */
1040 if (((chips_param->max_mem -
1041 ACCELMEMORY) / (res_mode->xres * res_mode->yres)) < tmp) {
1042 tmp =
1043 ((chips_param->max_mem -
1044 ACCELMEMORY) / (res_mode->xres * res_mode->yres));
1045 if (tmp == 0) {
1046 printf
1047 ("No matching videomode found .-> reduce resolution\n");
1048 return NULL;
1049 } else {
1050 printf ("Switching back to %d Bits per Pixel ",
1051 tmp << 3);
1052 bits_per_pixel = tmp << 3;
1053 }
1054 }
1055
1056 /* calculate hsynch and vsynch freq (info only) */
1057 t1 = (res_mode->left_margin + res_mode->xres +
1058 res_mode->right_margin + res_mode->hsync_len) / 8;
1059 t1 *= 8;
1060 t1 *= res_mode->pixclock;
1061 t1 /= 1000;
1062 hsynch = 1000000000L / t1;
1063 t1 *=
1064 (res_mode->upper_margin + res_mode->yres +
1065 res_mode->lower_margin + res_mode->vsync_len);
1066 t1 /= 1000;
1067 vsynch = 1000000000L / t1;
1068
1069 /* fill in Graphic device struct */
1070 sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
1071 res_mode->yres, bits_per_pixel, (hsynch / 1000),
1072 (vsynch / 1000));
1073 printf ("%s\n", pGD->modeIdent);
1074 pGD->winSizeX = res_mode->xres;
1075 pGD->winSizeY = res_mode->yres;
1076 pGD->plnSizeX = res_mode->xres;
1077 pGD->plnSizeY = res_mode->yres;
1078 switch (bits_per_pixel) {
1079 case 8:
1080 pGD->gdfBytesPP = 1;
1081 pGD->gdfIndex = GDF__8BIT_INDEX;
1082 break;
1083 case 15:
1084 pGD->gdfBytesPP = 2;
1085 pGD->gdfIndex = GDF_15BIT_555RGB;
1086 break;
1087 case 16:
1088 pGD->gdfBytesPP = 2;
1089 pGD->gdfIndex = GDF_16BIT_565RGB;
1090 break;
1091 case 24:
1092 pGD->gdfBytesPP = 3;
1093 pGD->gdfIndex = GDF_24BIT_888RGB;
1094 break;
1095 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001096 pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
wdenkc6097192002-11-03 00:24:07 +00001097 pGD->pciBase = pci_mem_base;
1098 pGD->frameAdrs = pci_mem_base;
1099 pGD->memSize = chips_param->max_mem;
1100 /* Cursor Start Address */
1101 pGD->dprBase =
1102 (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + pci_mem_base;
1103 if ((pGD->dprBase & 0x0fff) != 0) {
1104 /* allign it */
1105 pGD->dprBase &= 0xfffff000;
1106 pGD->dprBase += 0x00001000;
1107 }
Wolfgang Denk8a2d1f22011-11-09 09:29:04 +00001108 debug("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
wdenkc6097192002-11-03 00:24:07 +00001109 PATTERN_ADR);
1110 pGD->vprBase = pci_mem_base; /* Dummy */
1111 pGD->cprBase = pci_mem_base; /* Dummy */
1112 /* set up Hardware */
1113
Stefan Roesea7b9fb92006-01-18 20:05:34 +01001114#ifdef CONFIG_USE_CPCIDVI
1115 if (device_id == PCI_DEVICE_ID_CT_69030) {
1116 ctWrite (CT_MSR_W_O, 0x0b);
1117 ctWrite (0x3cd, 0x13);
1118 ctWrite_i (CT_FP_O, 0x02, 0x00);
1119 ctWrite_i (CT_FP_O, 0x05, 0x00);
1120 ctWrite_i (CT_FP_O, 0x06, 0x00);
1121 ctWrite (0x3c2, 0x0b);
1122 ctWrite_i (CT_FP_O, 0x02, 0x10);
1123 ctWrite_i (CT_FP_O, 0x01, 0x09);
1124 } else {
1125 ctWrite (CT_MSR_W_O, 0x01);
1126 }
1127#else
wdenkc6097192002-11-03 00:24:07 +00001128 ctWrite (CT_MSR_W_O, 0x01);
Stefan Roesea7b9fb92006-01-18 20:05:34 +01001129#endif
wdenkc6097192002-11-03 00:24:07 +00001130
1131 /* set the extended Registers */
1132 ctLoadRegs (CT_XR_O, xreg);
1133 /* set atribute registers */
1134 SetArRegs ();
1135 /* set Graphics register */
1136 SetGrRegs ();
1137 /* set sequencer */
1138 SetSrRegs ();
1139
1140 /* set msr */
1141 SetMsrRegs (res_mode);
1142
1143 /* set CRT Registers */
1144 SetCrRegs (res_mode, bits_per_pixel);
1145 /* set color mode */
1146 SetBitsPerPixelIntoXrRegs (bits_per_pixel);
1147
1148 /* set PLL */
1149 FindAndSetPllParamIntoXrRegs (res_mode->pixclock, chips_param);
1150
1151 ctWrite_i (CT_SR_O, 0, 0x03); /* clear synchronous reset */
1152 /* Clear video memory */
1153 i = pGD->memSize / 4;
1154 vm = (unsigned int *) pGD->pciBase;
1155 while (i--)
1156 *vm++ = 0;
1157 SetDrawingEngine (bits_per_pixel);
1158#ifdef VGA_DUMP_REG
1159 video_dump_reg ();
1160#endif
1161
1162 return ((void *) &ctfb);
1163}
1164
1165 /*******************************************************************************
1166*
1167* Set a RGB color in the LUT (8 bit index)
1168*/
1169void
1170video_set_lut (unsigned int index, /* color number */
1171 unsigned char r, /* red */
1172 unsigned char g, /* green */
1173 unsigned char b /* blue */
1174 )
1175{
1176
1177 ctWrite (CT_LUT_MASK_O, 0xff);
1178
1179 ctWrite (CT_LUT_START_O, (char) index);
1180
1181 ctWrite (CT_LUT_RGB_O, r); /* red */
1182 ctWrite (CT_LUT_RGB_O, g); /* green */
1183 ctWrite (CT_LUT_RGB_O, b); /* blue */
1184 udelay (1);
1185 ctWrite (CT_LUT_MASK_O, 0xff);
1186}
1187
1188/*******************************************************************************
1189*
1190* Drawing engine fill on screen region
1191*/
1192void
1193video_hw_rectfill (unsigned int bpp, /* bytes per pixel */
1194 unsigned int dst_x, /* dest pos x */
1195 unsigned int dst_y, /* dest pos y */
1196 unsigned int dim_x, /* frame width */
1197 unsigned int dim_y, /* frame height */
1198 unsigned int color /* fill color */
1199 )
1200{
1201 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
1202 unsigned long *p, br04;
1203
1204 video_wait_bitblt (pGD->pciBase + BR04_o);
1205
1206 p = (unsigned long *) PATTERN_ADR;
1207 dim_x *= bpp;
1208 if (bpp == 3)
1209 bpp++; /* 24Bit needs a 32bit pattern */
1210 memset (p, color, (bpp * sizeof (unsigned char) * 8 * 8)); /* 8 x 8 pattern data */
1211 out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */
1212 br04 = in32r (pGD->pciBase + BR04_o) & 0xffffff00;
1213 br04 |= 0xF0; /* write Pattern P -> D */
1214 out32r (pGD->pciBase + BR04_o, br04); /* */
1215 out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* starts the BITBlt */
1216 video_wait_bitblt (pGD->pciBase + BR04_o);
1217}
1218
1219/*******************************************************************************
1220*
1221* Drawing engine bitblt with screen region
1222*/
1223void
1224video_hw_bitblt (unsigned int bpp, /* bytes per pixel */
1225 unsigned int src_x, /* source pos x */
1226 unsigned int src_y, /* source pos y */
1227 unsigned int dst_x, /* dest pos x */
1228 unsigned int dst_y, /* dest pos y */
1229 unsigned int dim_x, /* frame width */
1230 unsigned int dim_y /* frame height */
1231 )
1232{
1233 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
1234 unsigned long br04;
1235
1236 br04 = in32r (pGD->pciBase + BR04_o);
1237
1238 /* to prevent data corruption due to overlap, we have to
1239 * find out if, and how the frames overlaps */
1240 if (src_x < dst_x) {
1241 /* src is more left than dest
1242 * the frame may overlap -> start from right to left */
1243 br04 |= 0x00000100; /* set bit 8 */
1244 src_x += dim_x;
1245 dst_x += dim_x;
1246 } else {
1247 br04 &= 0xfffffeff; /* clear bit 8 left to right */
1248 }
1249 if (src_y < dst_y) {
1250 /* src is higher than dst
1251 * the frame may overlap => start from bottom */
1252 br04 |= 0x00000200; /* set bit 9 */
1253 src_y += dim_y;
1254 dst_y += dim_y;
1255 } else {
1256 br04 &= 0xfffffdff; /* clear bit 9 top to bottom */
1257 }
1258 dim_x *= bpp;
1259 out32r (pGD->pciBase + BR06_o, ((pGD->winSizeX * src_y) + src_x) * pGD->gdfBytesPP); /* source */
1260 out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */
1261 br04 &= 0xffffff00;
1262 br04 |= 0x000000CC; /* S -> D */
1263 out32r (pGD->pciBase + BR04_o, br04); /* */
1264 out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* start the BITBlt */
1265 video_wait_bitblt (pGD->pciBase + BR04_o);
1266}
wdenkc6097192002-11-03 00:24:07 +00001267#endif /* CONFIG_VIDEO */