Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Wolfgang Denk | ff7fefe | 2006-03-13 12:37:35 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2003 |
| 4 | * Texas Instruments <www.ti.com> |
| 5 | * |
| 6 | * (C) Copyright 2002 |
| 7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 8 | * Marius Groeger <mgroeger@sysgo.de> |
| 9 | * |
| 10 | * (C) Copyright 2002 |
| 11 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 12 | * Alex Zuepke <azu@sysgo.de> |
| 13 | * |
| 14 | * (C) Copyright 2002-2004 |
Detlev Zundel | 792a09e | 2009-05-13 10:54:10 +0200 | [diff] [blame] | 15 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
Wolfgang Denk | ff7fefe | 2006-03-13 12:37:35 +0100 | [diff] [blame] | 16 | * |
| 17 | * (C) Copyright 2004 |
| 18 | * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> |
Wolfgang Denk | ff7fefe | 2006-03-13 12:37:35 +0100 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | #include <common.h> |
Wolfgang Denk | ff7fefe | 2006-03-13 12:37:35 +0100 | [diff] [blame] | 22 | |
Gururaja Hebbar K R | e8f1207 | 2008-08-25 11:11:34 +0200 | [diff] [blame] | 23 | #define TIMER_ENABLE (1 << 7) |
| 24 | #define TIMER_MODE_MSK (1 << 6) |
| 25 | #define TIMER_MODE_FR (0 << 6) |
| 26 | #define TIMER_MODE_PD (1 << 6) |
| 27 | |
| 28 | #define TIMER_INT_EN (1 << 5) |
| 29 | #define TIMER_PRS_MSK (3 << 2) |
| 30 | #define TIMER_PRS_8S (1 << 3) |
| 31 | #define TIMER_SIZE_MSK (1 << 2) |
| 32 | #define TIMER_ONE_SHT (1 << 0) |
| 33 | |
Wolfgang Denk | ff7fefe | 2006-03-13 12:37:35 +0100 | [diff] [blame] | 34 | int timer_init (void) |
| 35 | { |
Gururaja Hebbar K R | e8f1207 | 2008-08-25 11:11:34 +0200 | [diff] [blame] | 36 | ulong tmr_ctrl_val; |
| 37 | |
| 38 | /* 1st disable the Timer */ |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 39 | tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); |
Gururaja Hebbar K R | e8f1207 | 2008-08-25 11:11:34 +0200 | [diff] [blame] | 40 | tmr_ctrl_val &= ~TIMER_ENABLE; |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 41 | *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; |
Gururaja Hebbar K R | e8f1207 | 2008-08-25 11:11:34 +0200 | [diff] [blame] | 42 | |
| 43 | /* |
| 44 | * The Timer Control Register has one Undefined/Shouldn't Use Bit |
| 45 | * So we should do read/modify/write Operation |
| 46 | */ |
| 47 | |
| 48 | /* |
| 49 | * Timer Mode : Free Running |
| 50 | * Interrupt : Disabled |
| 51 | * Prescale : 8 Stage, Clk/256 |
| 52 | * Tmr Siz : 16 Bit Counter |
| 53 | * Tmr in Wrapping Mode |
| 54 | */ |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 55 | tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); |
Gururaja Hebbar K R | e8f1207 | 2008-08-25 11:11:34 +0200 | [diff] [blame] | 56 | tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); |
| 57 | tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); |
| 58 | |
Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 59 | *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; |
Wolfgang Denk | ff7fefe | 2006-03-13 12:37:35 +0100 | [diff] [blame] | 60 | |
Wolfgang Denk | ff7fefe | 2006-03-13 12:37:35 +0100 | [diff] [blame] | 61 | return 0; |
| 62 | } |