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wdenkab255f22002-09-18 09:04:55 +00001/*
stroese8b1ccd82004-09-16 12:34:51 +00002 * (C) Copyright 2001-2004
wdenkab255f22002-09-18 09:04:55 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_AR405 1 /* ...on a AR405 board */
wdenkab255f22002-09-18 09:04:55 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkab255f22002-09-18 09:04:55 +000041
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
wdenkab255f22002-09-18 09:04:55 +000043
stroese8b1ccd82004-09-16 12:34:51 +000044#define CONFIG_BOARD_TYPES 1 /* support board types */
45
wdenkab255f22002-09-18 09:04:55 +000046#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
49#if 1
50#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */
51#else
52#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
53#endif
54
55#if 0
wdenkc837dcb2004-01-20 23:12:12 +000056#define CONFIG_BOOTARGS "root=/dev/nfs " \
57 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
wdenkab255f22002-09-18 09:04:55 +000058 "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
59#else
60#define CONFIG_BOOTARGS "root=/dev/hda1 " \
61 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
62
63#endif
64
stroese8b1ccd82004-09-16 12:34:51 +000065#define CONFIG_PREBOOT /* enable preboot variable */
66
wdenkab255f22002-09-18 09:04:55 +000067#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
68#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
69
70#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000071#define CONFIG_PHY_ADDR 0 /* PHY address */
stroese8b1ccd82004-09-16 12:34:51 +000072#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
wdenkab255f22002-09-18 09:04:55 +000073
wdenkab255f22002-09-18 09:04:55 +000074
Jon Loeliger498ff9a2007-07-05 19:13:52 -050075/*
Jon Loeliger11799432007-07-10 09:02:57 -050076 * BOOTP options
77 */
78#define CONFIG_BOOTP_BOOTFILESIZE
79#define CONFIG_BOOTP_BOOTPATH
80#define CONFIG_BOOTP_GATEWAY
81#define CONFIG_BOOTP_HOSTNAME
82
83
84/*
Jon Loeliger498ff9a2007-07-05 19:13:52 -050085 * Command line configuration.
86 */
87#include <config_cmd_default.h>
88
89#define CONFIG_CMD_DHCP
90#define CONFIG_CMD_PCI
91#define CONFIG_CMD_IRQ
92#define CONFIG_CMD_ELF
93#define CONFIG_CMD_MII
94#define CONFIG_CMD_PING
95#define CONFIG_CMD_BSP
96
wdenkab255f22002-09-18 09:04:55 +000097
98#undef CONFIG_WATCHDOG /* watchdog disabled */
99
wdenkc837dcb2004-01-20 23:12:12 +0000100#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkab255f22002-09-18 09:04:55 +0000101
102/*
103 * Miscellaneous configurable options
104 */
105#define CFG_LONGHELP /* undef to save memory */
106#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500107#if defined(CONFIG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +0000108#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkab255f22002-09-18 09:04:55 +0000109#else
wdenkc837dcb2004-01-20 23:12:12 +0000110#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkab255f22002-09-18 09:04:55 +0000111#endif
112#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
113#define CFG_MAXARGS 16 /* max number of command args */
114#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
115
stroese8b1ccd82004-09-16 12:34:51 +0000116#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
117
wdenkc837dcb2004-01-20 23:12:12 +0000118#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkab255f22002-09-18 09:04:55 +0000119
stroese8b1ccd82004-09-16 12:34:51 +0000120#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
stroesea20b27a2004-12-16 18:05:42 +0000121#define CONFIG_LOOPW 1 /* enable loopw command */
122#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
stroese8b1ccd82004-09-16 12:34:51 +0000123
wdenkab255f22002-09-18 09:04:55 +0000124#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
125#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
126
wdenkc837dcb2004-01-20 23:12:12 +0000127#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
wdenkab255f22002-09-18 09:04:55 +0000128
129/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000130#define CFG_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000131 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
132 57600, 115200, 230400, 460800, 921600 }
wdenkab255f22002-09-18 09:04:55 +0000133
134#define CFG_LOAD_ADDR 0x100000 /* default load address */
135#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
136
wdenkc837dcb2004-01-20 23:12:12 +0000137#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkab255f22002-09-18 09:04:55 +0000138
139#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
140
141/*-----------------------------------------------------------------------
142 * PCI stuff
143 *-----------------------------------------------------------------------
144 */
wdenkc837dcb2004-01-20 23:12:12 +0000145#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
146#define PCI_HOST_FORCE 1 /* configure as pci host */
147#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkab255f22002-09-18 09:04:55 +0000148
wdenkc837dcb2004-01-20 23:12:12 +0000149#define CONFIG_PCI /* include pci support */
150#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
151#define CONFIG_PCI_PNP /* do pci plug-and-play */
152 /* resource configuration */
wdenkab255f22002-09-18 09:04:55 +0000153
wdenkc837dcb2004-01-20 23:12:12 +0000154#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroesead10dd92003-02-14 11:21:23 +0000155
stroesea20b27a2004-12-16 18:05:42 +0000156#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
157
wdenkc837dcb2004-01-20 23:12:12 +0000158#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
stroesead10dd92003-02-14 11:21:23 +0000159
wdenkc837dcb2004-01-20 23:12:12 +0000160#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
161#define CFG_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */
162#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
163#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
164#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
165#define CFG_PCI_PTM2LA 0xfff00000 /* point to flash */
166#define CFG_PCI_PTM2MS 0xfff00001 /* 1MB, enable */
167#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkab255f22002-09-18 09:04:55 +0000168
169/*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
172 * Please note that CFG_SDRAM_BASE _must_ start at 0
173 */
174#define CFG_SDRAM_BASE 0x00000000
stroese8b1ccd82004-09-16 12:34:51 +0000175#define CFG_FLASH_BASE 0xFFFC0000
wdenkab255f22002-09-18 09:04:55 +0000176#define CFG_MONITOR_BASE CFG_FLASH_BASE
stroese8b1ccd82004-09-16 12:34:51 +0000177#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
wdenkab255f22002-09-18 09:04:55 +0000178#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
179
180/*
181 * For booting Linux, the board info and command line data
182 * have to be in the first 8 MB of memory, since this is
183 * the maximum mapped by the Linux kernel during initialization.
184 */
185#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
186/*-----------------------------------------------------------------------
187 * FLASH organization
188 */
stroese8b1ccd82004-09-16 12:34:51 +0000189#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenkab255f22002-09-18 09:04:55 +0000190#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
191
192#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
193#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
194
wdenkc837dcb2004-01-20 23:12:12 +0000195#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
196#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
197#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkab255f22002-09-18 09:04:55 +0000198/*
199 * The following defines are added for buggy IOP480 byte interface.
200 * All other boards should use the standard values (CPCI405 etc.)
201 */
wdenkc837dcb2004-01-20 23:12:12 +0000202#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
203#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
204#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
wdenkab255f22002-09-18 09:04:55 +0000205
wdenkc837dcb2004-01-20 23:12:12 +0000206#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkab255f22002-09-18 09:04:55 +0000207
wdenkc837dcb2004-01-20 23:12:12 +0000208#define CFG_ENV_IS_IN_FLASH 1
stroesea20b27a2004-12-16 18:05:42 +0000209#define CFG_ENV_ADDR 0xFFFB0000 /* Address of Environment Sector*/
wdenkc837dcb2004-01-20 23:12:12 +0000210#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
stroesea20b27a2004-12-16 18:05:42 +0000211#define CFG_ENV_SIZE 0x04000 /* Size of Environment */
212
213#define CFG_ENV_ADDR_REDUND 0xFFFA0000
214#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
wdenkab255f22002-09-18 09:04:55 +0000215
wdenkab255f22002-09-18 09:04:55 +0000216/*
217 * Init Memory Controller:
218 *
219 * BR0/1 and OR0/1 (FLASH)
220 */
221
stroese8b1ccd82004-09-16 12:34:51 +0000222#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
wdenkab255f22002-09-18 09:04:55 +0000223
224/*-----------------------------------------------------------------------
225 * External Bus Controller (EBC) Setup
226 */
227
wdenkc837dcb2004-01-20 23:12:12 +0000228/* Memory Bank 0 (Flash Bank 0) initialization */
229#define CFG_EBC_PB0AP 0x92015480
230#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkab255f22002-09-18 09:04:55 +0000231
wdenkc837dcb2004-01-20 23:12:12 +0000232/* Memory Bank 1 (CAN0, 1, 2, 3) initialization */
233#define CFG_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */
234#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkab255f22002-09-18 09:04:55 +0000235
wdenkc837dcb2004-01-20 23:12:12 +0000236/* Memory Bank 2 (Expension Bus) initialization */
237#define CFG_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */
238#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
wdenkab255f22002-09-18 09:04:55 +0000239
wdenkc837dcb2004-01-20 23:12:12 +0000240/* Memory Bank 3 (16552) initialization */
241#define CFG_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */
242#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkab255f22002-09-18 09:04:55 +0000243
wdenkc837dcb2004-01-20 23:12:12 +0000244/* Memory Bank 4 (FPGA regs) initialization */
245#define CFG_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */
246#define CFG_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
wdenkab255f22002-09-18 09:04:55 +0000247
wdenkc837dcb2004-01-20 23:12:12 +0000248/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */
249#define CFG_EBC_PB5AP 0x92015480
250#define CFG_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkab255f22002-09-18 09:04:55 +0000251
252/*-----------------------------------------------------------------------
stroesec5d22902003-07-11 08:13:25 +0000253 * Definitions for initial stack pointer and data area (in data cache)
wdenkab255f22002-09-18 09:04:55 +0000254 */
wdenkc837dcb2004-01-20 23:12:12 +0000255#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
wdenkab255f22002-09-18 09:04:55 +0000256
wdenkc837dcb2004-01-20 23:12:12 +0000257#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
258#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
stroesec5d22902003-07-11 08:13:25 +0000259#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
260#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000261#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenkab255f22002-09-18 09:04:55 +0000262
263/*
264 * Internal Definitions
265 *
266 * Boot Flags
267 */
268#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
269#define BOOTFLAG_WARM 0x02 /* Software reboot */
270
271#endif /* __CONFIG_H */