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wdenk5e5f9ed2005-04-13 23:15:10 +00001/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
34#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
35
36#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
37
38#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39#define BOOTFLAG_WARM 0x02 /* Software reboot */
40
wdenk5e5f9ed2005-04-13 23:15:10 +000041#define CONFIG_BOARD_EARLY_INIT_R
42
43/*
44 * Serial console configuration
45 */
46#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
49
wdenk5e5f9ed2005-04-13 23:15:10 +000050
Jon Loeliger37e4f242007-07-04 22:31:56 -050051/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050052 * BOOTP options
53 */
54#define CONFIG_BOOTP_BOOTFILESIZE
55#define CONFIG_BOOTP_BOOTPATH
56#define CONFIG_BOOTP_GATEWAY
57#define CONFIG_BOOTP_HOSTNAME
58
59
60/*
Jon Loeliger37e4f242007-07-04 22:31:56 -050061 * Command line configuration.
62 */
63#include <config_cmd_default.h>
64
65#define CONFIG_CMD_ASKENV
66#define CONFIG_CMD_DATE
67#define CONFIG_CMD_DHCP
68#define CONFIG_CMD_IMMAP
69#define CONFIG_CMD_MII
70#define CONFIG_CMD_NFS
71#define CONFIG_CMD_REGINFO
72#define CONFIG_CMD_SNTP
73
wdenk5e5f9ed2005-04-13 23:15:10 +000074
75/*
76 * MUST be low boot - HIGHBOOT is not supported anymore
77 */
78#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
79# define CFG_LOWBOOT 1
80# define CFG_LOWBOOT16 1
81#else
82# error "TEXT_BASE must be 0xFE000000"
83#endif
84
85/*
86 * Autobooting
87 */
88#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
89
90#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010091 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk5e5f9ed2005-04-13 23:15:10 +000092 "echo"
93
94#undef CONFIG_BOOTARGS
95
96#define CONFIG_EXTRA_ENV_SETTINGS \
97 "netdev=eth0\0" \
98 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010099 "nfsroot=${serverip}:${rootpath}\0" \
wdenk5e5f9ed2005-04-13 23:15:10 +0000100 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100101 "addip=setenv bootargs ${bootargs} " \
102 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
103 ":${hostname}:${netdev}:off panic=1\0" \
wdenk5e5f9ed2005-04-13 23:15:10 +0000104 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100105 "bootm ${kernel_addr}\0" \
wdenk5e5f9ed2005-04-13 23:15:10 +0000106 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100107 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
108 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk5e5f9ed2005-04-13 23:15:10 +0000109 "rootpath=/opt/eldk/ppc_6xx\0" \
110 "bootfile=/tftpboot/canmb/uImage\0" \
111 ""
112
113#define CONFIG_BOOTCOMMAND "run flash_self"
114
115/*
116 * IPB Bus clocking configuration.
117 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200118#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenk5e5f9ed2005-04-13 23:15:10 +0000119
120/*
121 * Flash configuration, expect one 16 Megabyte Bank at most
122 */
123#define CFG_FLASH_BASE 0xFE000000
124#define CFG_FLASH_SIZE 0x02000000
125#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
126#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
127
128#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
129#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
130
131#define CFG_FLASH_CFI_DRIVER
132#define CFG_FLASH_CFI
133#define CFG_FLASH_EMPTY_INFO
134
135/*
wdenk5e5f9ed2005-04-13 23:15:10 +0000136 * Environment settings
137 */
138#define CFG_ENV_IS_IN_FLASH 1
139#define CFG_ENV_OFFSET (2*128*1024)
140#define CFG_ENV_SIZE 0x2000
141#define CFG_ENV_SECT_SIZE (128*1024)
142
143/*
144 * Memory map
145 *
146 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
147 */
148#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
149#define CFG_SDRAM_BASE 0x00000000
150#define CFG_DEFAULT_MBAR 0x80000000
151
152/* Use SRAM until RAM will be available */
153#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
154#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
155
156
157#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
158#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
159#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
160
161#define CFG_MONITOR_BASE TEXT_BASE
162#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
163# define CFG_RAMBOOT 1
164#endif
165
166#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
167#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
168#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
169
170/*
171 * Ethernet configuration
172 */
173#define CONFIG_MPC5xxx_FEC 1
wdenka6310922005-04-21 21:10:22 +0000174#define CONFIG_PHY_ADDR 0x0
wdenk5e5f9ed2005-04-13 23:15:10 +0000175/*
176 * GPIO configuration:
177 * PSC1,2,3 predefined as UART
178 * PCI disabled
179 * Ethernet 100 with MD
180 */
181#define CFG_GPS_PORT_CONFIG 0x00058444
182
183/*
184 * Miscellaneous configurable options
185 */
186#define CFG_LONGHELP /* undef to save memory */
187#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500188#if defined(CONFIG_CMD_KGDB)
wdenk5e5f9ed2005-04-13 23:15:10 +0000189# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
190#else
191# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
192#endif
193#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
194#define CFG_MAXARGS 16 /* max number of command args */
195#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
196
197#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
198#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
199
200#define CFG_LOAD_ADDR 0x200000 /* default load address */
201
202#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
203
204#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
205
Jon Loeliger37e4f242007-07-04 22:31:56 -0500206#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
207#if defined(CONFIG_CMD_KGDB)
208# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
209#endif
210
wdenk5e5f9ed2005-04-13 23:15:10 +0000211/*
212 * Various low-level settings
213 */
214#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
215#define CFG_HID0_FINAL HID0_ICE
216
217#define CFG_BOOTCS_START CFG_FLASH_BASE
218#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
219#define CFG_BOOTCS_CFG 0x00047D01
220#define CFG_CS0_START CFG_FLASH_BASE
221#define CFG_CS0_SIZE CFG_FLASH_SIZE
222
223#define CFG_CS_BURST 0x00000000
224#define CFG_CS_DEADCYCLE 0x33333333
225
226#define CFG_RESET_ADDRESS 0x7f000000
227
228#endif /* __CONFIG_H */