blob: 15f690af16953aa922b11242328f8cf55d7c803b [file] [log] [blame]
Dan Malek35171dc2007-01-05 09:15:34 +01001/*
2 * (C) Copyright 2005 Embedded Alley Solutions, Inc.
3 * Dan Malek <dan@embeddedalley.com>
4 * Copied from STx GP3.
5 * Updates for Silicon Tx GP3 SSA board.
6 *
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/* mpc8560ads board configuration file */
30/* please refer to doc/README.mpc85xx for more info */
31/* make sure you change the MAC address and other network params first,
32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38/* High Level Configuration Options */
39#define CONFIG_BOOKE 1 /* BOOKE */
40#define CONFIG_E500 1 /* BOOKE e500 family */
41#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
42#define CONFIG_CPM2 1 /* has CPM2 */
43#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
44
Wolfgang Denkf1152f82007-07-06 02:50:19 +020045#define CONFIG_PCI /* PCI ethernet support */
46#define CONFIG_TSEC_ENET /* tsec ethernet support*/
47#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
Dan Malek35171dc2007-01-05 09:15:34 +010048#define CONFIG_ENV_OVERWRITE
Wolfgang Denkf1152f82007-07-06 02:50:19 +020049#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
50#undef CONFIG_DDR_ECC /* only for ECC DDR module */
51#undef CONFIG_DDR_DLL /* possible DLL fix needed */
Dan Malek35171dc2007-01-05 09:15:34 +010052#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
53
Kumar Gala572b13a2008-01-16 09:11:53 -060054#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Dan Malek35171dc2007-01-05 09:15:34 +010055
56/* sysclk for MPC85xx
57 */
58
Wolfgang Denkf1152f82007-07-06 02:50:19 +020059#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
Dan Malek35171dc2007-01-05 09:15:34 +010060
61/* Blinkin' LEDs for Robert :-)
62*/
63#define CONFIG_SHOW_ACTIVITY 1
64
65/*
66 * These can be toggled for performance analysis, otherwise use default.
67 */
Wolfgang Denkf1152f82007-07-06 02:50:19 +020068#define CONFIG_L2_CACHE /* toggle L2 cache */
69#define CONFIG_BTB /* toggle branch predition */
70#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
Dan Malek35171dc2007-01-05 09:15:34 +010071
Wolfgang Denkf1152f82007-07-06 02:50:19 +020072#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Dan Malek35171dc2007-01-05 09:15:34 +010073
Wolfgang Denkf1152f82007-07-06 02:50:19 +020074#undef CFG_DRAM_TEST /* memory test, takes time */
75#define CFG_MEMTEST_START 0x00200000 /* memtest region */
76#define CFG_MEMTEST_END 0x00400000
Dan Malek35171dc2007-01-05 09:15:34 +010077
78
Wolfgang Denkf1152f82007-07-06 02:50:19 +020079/* Localbus connector. There are many options that can be
Dan Malek35171dc2007-01-05 09:15:34 +010080 * connected here, including sdram or lots of flash.
81 * This address, however, is used to configure a 256M local bus
82 * window that includes the Config latch below.
83 */
Wolfgang Denkf1152f82007-07-06 02:50:19 +020084#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
Dan Malek35171dc2007-01-05 09:15:34 +010085#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
86
87/* There are various flash options used, we configure for the largest,
88 * which is 64Mbytes. The CFI works fine and will discover the proper
89 * sizes.
90 */
Wolfgang Denkee152982007-05-31 17:20:09 +020091#ifdef CONFIG_STXSSA_4M
Wolfgang Denkf1152f82007-07-06 02:50:19 +020092#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
Wolfgang Denkee152982007-05-31 17:20:09 +020093#else
Wolfgang Denkf1152f82007-07-06 02:50:19 +020094#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
Wolfgang Denkee152982007-05-31 17:20:09 +020095#endif
96#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
97#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
Dan Malek35171dc2007-01-05 09:15:34 +010098
99#define CFG_FLASH_CFI 1
100#define CFG_FLASH_CFI_DRIVER 1
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200101#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
Dan Malek35171dc2007-01-05 09:15:34 +0100102#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
103#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
104
105#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
106
107#define CFG_FLASH_PROTECTION
108
109/* The configuration latch is Chip Select 1.
110 * It's an 8-bit latch in the lower 8 bits of the word.
111 */
Wolfgang Denkee152982007-05-31 17:20:09 +0200112#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
113#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200114#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
Dan Malek35171dc2007-01-05 09:15:34 +0100115
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200116#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
Dan Malek35171dc2007-01-05 09:15:34 +0100117
118#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
119#define CFG_RAMBOOT
120#else
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200121#undef CFG_RAMBOOT
Dan Malek35171dc2007-01-05 09:15:34 +0100122#endif
123
124#ifdef CFG_RAMBOOT
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200125#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
Dan Malek35171dc2007-01-05 09:15:34 +0100126#else
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200127#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
Dan Malek35171dc2007-01-05 09:15:34 +0100128#endif
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200129#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
Kumar Galaf69766e2008-01-30 14:55:14 -0600130#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
Dan Malek35171dc2007-01-05 09:15:34 +0100131#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
132
133
134/*
135 * DDR Setup
136 */
137
138/*
139 * Base addresses -- Note these are effective addresses where the
140 * actual resources get mapped (not physical addresses)
141 */
142#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
143#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
144
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200145#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
Dan Malek35171dc2007-01-05 09:15:34 +0100146
147#undef CONFIG_CLOCKS_IN_MHZ
148
149/* local bus definitions */
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200150#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
Dan Malek35171dc2007-01-05 09:15:34 +0100151#define CFG_OR2_PRELIM 0xfc006901
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200152#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
Dan Malek35171dc2007-01-05 09:15:34 +0100153#define CFG_LBC_LBCR 0x00000000
154#define CFG_LBC_LSRT 0x20000000
155#define CFG_LBC_MRTPR 0x20000000
156#define CFG_LBC_LSDMR_1 0x2861b723
157#define CFG_LBC_LSDMR_2 0x0861b723
158#define CFG_LBC_LSDMR_3 0x0861b723
159#define CFG_LBC_LSDMR_4 0x1861b723
160#define CFG_LBC_LSDMR_5 0x4061b723
161
162#define CONFIG_L1_INIT_RAM
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200163#define CFG_INIT_RAM_LOCK 1
164#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
165#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
Dan Malek35171dc2007-01-05 09:15:34 +0100166
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200167#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
Dan Malek35171dc2007-01-05 09:15:34 +0100168#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
169#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
170
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200171#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
172#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dan Malek35171dc2007-01-05 09:15:34 +0100173
174/* Serial Port */
175#define CONFIG_CONS_INDEX 2
176#undef CONFIG_SERIAL_SOFTWARE_FIFO
177#define CFG_NS16550
178#define CFG_NS16550_SERIAL
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200179#define CFG_NS16550_REG_SIZE 1
Dan Malek35171dc2007-01-05 09:15:34 +0100180#define CFG_NS16550_CLK get_bus_freq(0)
181
Dan Malek35171dc2007-01-05 09:15:34 +0100182#define CFG_BAUDRATE_TABLE \
183 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
184
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200185#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
186#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
Dan Malek35171dc2007-01-05 09:15:34 +0100187
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200188#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
189#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200190#ifdef CFG_HUSH_PARSER
Dan Malek35171dc2007-01-05 09:15:34 +0100191#define CFG_PROMPT_HUSH_PS2 "> "
192#endif
193
Wolfgang Denke1893812007-10-12 15:49:39 +0200194/*
195 * I2C
196 */
Dan Malek35171dc2007-01-05 09:15:34 +0100197#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200198#define CONFIG_HARD_I2C /* I2C with hardware support*/
Dan Malek35171dc2007-01-05 09:15:34 +0100199#undef CONFIG_SOFT_I2C /* I2C bit-banged */
200#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
201#define CFG_I2C_SLAVE 0x7F
Dan Malek35171dc2007-01-05 09:15:34 +0100202#undef CFG_I2C_NOPROBES
Dan Malek35171dc2007-01-05 09:15:34 +0100203#define CFG_I2C_OFFSET 0x3000
204
Wolfgang Denke1893812007-10-12 15:49:39 +0200205/* I2C RTC */
206#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
207#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
208
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200209/* I2C EEPROM. AT24C32, we keep our environment in here.
Dan Malek35171dc2007-01-05 09:15:34 +0100210*/
211#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
212#define CFG_I2C_EEPROM_ADDR_LEN 2
213#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
214#define CFG_EEPROM_PAGE_WRITE_ENABLE
215#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
216
217/*
218 * Standard 8555 PCI mapping.
219 * Addresses are mapped 1-1.
220 */
221#define CFG_PCI1_MEM_BASE 0x80000000
222#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
223#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
224#define CFG_PCI1_IO_BASE 0x00000000
225#define CFG_PCI1_IO_PHYS 0xe2000000
226#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
227
228#define CFG_PCI2_MEM_BASE 0xa0000000
229#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
230#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
231#define CFG_PCI2_IO_BASE 0x00000000
232#define CFG_PCI2_IO_PHYS 0xe3000000
233#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
234
235#if defined(CONFIG_PCI) /* PCI Ethernet card */
Grzegorz Bernacki38ad82d2007-09-11 15:42:11 +0200236#define CONFIG_MPC85XX_PCI2 1
Dan Malek35171dc2007-01-05 09:15:34 +0100237#define CONFIG_NET_MULTI
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200238#define CONFIG_PCI_PNP /* do pci plug-and-play */
Dan Malek35171dc2007-01-05 09:15:34 +0100239
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200240#define CONFIG_EEPRO100
241#define CONFIG_TULIP
Dan Malek35171dc2007-01-05 09:15:34 +0100242
243#if !defined(CONFIG_PCI_PNP)
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200244 #define PCI_ENET0_IOADDR 0xe0000000
245 #define PCI_ENET0_MEMADDR 0xe0000000
246 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
Dan Malek35171dc2007-01-05 09:15:34 +0100247#endif
248
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200249#define CONFIG_PCI_SCAN_SHOW
250#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Dan Malek35171dc2007-01-05 09:15:34 +0100251
252#endif /* CONFIG_PCI */
253
254#if defined(CONFIG_TSEC_ENET)
255
256#ifndef CONFIG_NET_MULTI
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200257#define CONFIG_NET_MULTI 1
Dan Malek35171dc2007-01-05 09:15:34 +0100258#endif
259
260#define CONFIG_MII 1 /* MII PHY management */
261
Kim Phillips255a35772007-05-16 16:52:19 -0500262#define CONFIG_TSEC1 1
263#define CONFIG_TSEC1_NAME "TSEC0"
264#define CONFIG_TSEC2 1
265#define CONFIG_TSEC2_NAME "TSEC1"
Dan Malek35171dc2007-01-05 09:15:34 +0100266
267#define TSEC1_PHY_ADDR 2
268#define TSEC2_PHY_ADDR 4
269#define TSEC1_PHYIDX 0
270#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500271#define TSEC1_FLAGS TSEC_GIGABIT
272#define TSEC2_FLAGS TSEC_GIGABIT
Dan Malek35171dc2007-01-05 09:15:34 +0100273#define CONFIG_ETHPRIME "TSEC0"
274
275#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
276
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200277#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
278#undef CONFIG_ETHER_NONE /* define if ether on something else */
279#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
Dan Malek35171dc2007-01-05 09:15:34 +0100280
281#if (CONFIG_ETHER_INDEX == 2)
282 /*
283 * - Rx-CLK is CLK13
284 * - Tx-CLK is CLK14
285 * - Select bus for bd/buffers
286 * - Full duplex
287 */
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200288 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
289 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
290 #define CFG_CPMFCR_RAMTYPE 0
Dan Malek35171dc2007-01-05 09:15:34 +0100291#if 0
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200292 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
Dan Malek35171dc2007-01-05 09:15:34 +0100293#else
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200294 #define CFG_FCC_PSMR 0
Dan Malek35171dc2007-01-05 09:15:34 +0100295#endif
296 #define FETH2_RST 0x01
297#elif (CONFIG_ETHER_INDEX == 3)
298 /* need more definitions here for FE3 */
299 #define FETH3_RST 0x80
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200300#endif /* CONFIG_ETHER_INDEX */
Dan Malek35171dc2007-01-05 09:15:34 +0100301
302/* MDIO is done through the TSEC0 control.
303*/
304#define CONFIG_MII /* MII PHY management */
305#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
306
307#endif
308
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200309/* Environment - default config is in flash, see below */
310#if 0 /* in EEPROM */
Wolfgang Denkee152982007-05-31 17:20:09 +0200311# define CFG_ENV_IS_IN_EEPROM 1
312# define CFG_ENV_OFFSET 0
313# define CFG_ENV_SIZE 2048
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200314#else /* in flash */
Wolfgang Denkee152982007-05-31 17:20:09 +0200315# define CFG_ENV_IS_IN_FLASH 1
316# ifdef CONFIG_STXSSA_4M
317# define CFG_ENV_SECT_SIZE 0x20000
318# else /* default configuration - 64 MiB flash */
319# define CFG_ENV_SECT_SIZE 0x40000
320# endif
321# define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
322# define CFG_ENV_SIZE 0x4000
323# define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
324# define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
Dan Malek35171dc2007-01-05 09:15:34 +0100325#endif
326
Dan Malek35171dc2007-01-05 09:15:34 +0100327#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
328#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
329
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200330#define CONFIG_TIMESTAMP /* Print image info with ts */
331
Jon Loeliger2835e512007-06-13 13:22:08 -0500332
333/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500334 * BOOTP options
335 */
336#define CONFIG_BOOTP_BOOTFILESIZE
337#define CONFIG_BOOTP_BOOTPATH
338#define CONFIG_BOOTP_GATEWAY
339#define CONFIG_BOOTP_HOSTNAME
340
341
342/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500343 * Command line configuration.
344 */
345#include <config_cmd_default.h>
346
Wolfgang Denke1893812007-10-12 15:49:39 +0200347#define CONFIG_CMD_DATE
348#define CONFIG_CMD_DHCP
349#define CONFIG_CMD_EEPROM
Jon Loeliger2835e512007-06-13 13:22:08 -0500350#define CONFIG_CMD_I2C
Wolfgang Denke1893812007-10-12 15:49:39 +0200351#define CONFIG_CMD_NFS
352#define CONFIG_CMD_PING
353#define CONFIG_CMD_SNTP
Jon Loeliger2835e512007-06-13 13:22:08 -0500354
355#if defined(CONFIG_PCI)
356 #define CONFIG_CMD_PCI
Dan Malek35171dc2007-01-05 09:15:34 +0100357#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500358
359#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
360 #define CONFIG_CMD_MII
361#endif
362
363#if defined(CFG_RAMBOOT)
364 #undef CONFIG_CMD_ENV
365 #undef CONFIG_CMD_LOADS
366#else
367 #define CONFIG_CMD_ELF
368#endif
369
Dan Malek35171dc2007-01-05 09:15:34 +0100370
371#undef CONFIG_WATCHDOG /* watchdog disabled */
372
373/*
374 * Miscellaneous configurable options
375 */
376#define CFG_LONGHELP /* undef to save memory */
377#define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */
Jon Loeligeref0df522007-07-04 22:31:07 -0500378#if defined(CONFIG_CMD_KGDB)
Dan Malek35171dc2007-01-05 09:15:34 +0100379#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
380#else
381#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
382#endif
383#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
384#define CFG_MAXARGS 16 /* max number of command args */
385#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
386#define CFG_LOAD_ADDR 0x1000000 /* default load address */
387#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
388
389/*
390 * For booting Linux, the board info and command line data
391 * have to be in the first 8 MB of memory, since this is
392 * the maximum mapped by the Linux kernel during initialization.
393 */
394#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
395
Dan Malek35171dc2007-01-05 09:15:34 +0100396/*
397 * Internal Definitions
398 *
399 * Boot Flags
400 */
401#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
402#define BOOTFLAG_WARM 0x02 /* Software reboot */
403
Jon Loeligeref0df522007-07-04 22:31:07 -0500404#if defined(CONFIG_CMD_KGDB)
Dan Malek35171dc2007-01-05 09:15:34 +0100405#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
406#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
407#endif
408
409/*Note: change below for your network setting!!! */
410#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500411#define CONFIG_HAS_ETH0
Dan Malek35171dc2007-01-05 09:15:34 +0100412#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
413#define CONFIG_HAS_ETH1
414#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
415#define CONFIG_HAS_ETH2
416#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
417#endif
418
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200419/*
420 * Environment in EEPROM is compatible with different flash sector sizes,
421 * but only little space is available, so we use a very simple setup.
422 * With environment in flash, we use a more powerful default configuration.
423 */
424#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
425
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200426#define CONFIG_BAUDRATE 38400
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200427
428#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
429#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
430#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
Dan Malek35171dc2007-01-05 09:15:34 +0100431#define CONFIG_SERVERIP 192.168.85.1
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200432#define CONFIG_IPADDR 192.168.85.60
Dan Malek35171dc2007-01-05 09:15:34 +0100433#define CONFIG_GATEWAYIP 192.168.85.1
434#define CONFIG_NETMASK 255.255.255.0
435#define CONFIG_HOSTNAME STX_SSA
436#define CONFIG_ROOTPATH /gppproot
437#define CONFIG_BOOTFILE uImage
438#define CONFIG_LOADADDR 0x1000000
439
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200440#else /* ENV IS IN FLASH -- use a full-blown envionment */
441
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200442#define CONFIG_BAUDRATE 115200
Wolfgang Denkc64a89d2007-05-03 16:34:41 +0200443
444#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
445
446#define CONFIG_PREBOOT "echo;" \
447 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
448 "echo"
449
450#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
451
452#define CONFIG_EXTRA_ENV_SETTINGS \
453 "hostname=gp3ssa\0" \
454 "bootfile=/tftpboot/gp3ssa/uImage\0" \
455 "loadaddr=400000\0" \
456 "netdev=eth0\0" \
457 "consdev=ttyS1\0" \
458 "nfsargs=setenv bootargs root=/dev/nfs rw " \
459 "nfsroot=$serverip:$rootpath\0" \
460 "ramargs=setenv bootargs root=/dev/ram rw\0" \
461 "addip=setenv bootargs $bootargs " \
462 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
463 ":$hostname:$netdev:off panic=1\0" \
464 "addcons=setenv bootargs $bootargs " \
465 "console=$consdev,$baudrate\0" \
466 "flash_nfs=run nfsargs addip addcons;" \
467 "bootm $kernel_addr\0" \
468 "flash_self=run ramargs addip addcons;" \
469 "bootm $kernel_addr $ramdisk_addr\0" \
470 "net_nfs=tftp $loadaddr $bootfile;" \
471 "run nfsargs addip addcons;bootm\0" \
472 "rootpath=/opt/eldk/ppc_85xx\0" \
473 "kernel_addr=FC000000\0" \
474 "ramdisk_addr=FC200000\0" \
475 ""
476#define CONFIG_BOOTCOMMAND "run flash_self"
477
478#endif /* CFG_ENV_IS_IN_EEPROM */
479
Dan Malek35171dc2007-01-05 09:15:34 +0100480#endif /* __CONFIG_H */