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wdenk7abf0c52004-04-18 21:45:42 +00001/*
2 * (C) Copyright 2003 Embedded Edge, LLC
3 * Dan Malek <dan@embeddededge.com>
4 * Copied from ADS85xx.
5 * Updates for Silicon Tx GP3 8560 board.
6 *
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/* mpc8560ads board configuration file */
30/* please refer to doc/README.mpc85xx for more info */
31/* make sure you change the MAC address and other network params first,
32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38/* High Level Configuration Options */
39#define CONFIG_BOOKE 1 /* BOOKE */
40#define CONFIG_E500 1 /* BOOKE e500 family */
41#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050042#define CONFIG_CPM2 1 /* has CPM2 */
wdenk7abf0c52004-04-18 21:45:42 +000043#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
Kumar Galaf0600542008-06-11 00:44:10 -050044#define CONFIG_MPC8560 1
wdenk7abf0c52004-04-18 21:45:42 +000045
Wolfgang Denk53677ef2008-05-20 16:00:29 +020046#undef CONFIG_PCI /* pci ethernet support */
47#define CONFIG_TSEC_ENET /* tsec ethernet support*/
wdenk7abf0c52004-04-18 21:45:42 +000048#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
49#define CONFIG_ENV_OVERWRITE
wdenk7abf0c52004-04-18 21:45:42 +000050
Kumar Gala572b13a2008-01-16 09:11:53 -060051#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk9aea9532004-08-01 23:02:45 +000052
53/* sysclk for MPC85xx
wdenk7abf0c52004-04-18 21:45:42 +000054 */
wdenk7abf0c52004-04-18 21:45:42 +000055
56#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
57
58/* Blinkin' LEDs for Robert :-)
59*/
60#define CONFIG_SHOW_ACTIVITY 1
61
wdenk9aea9532004-08-01 23:02:45 +000062/*
63 * These can be toggled for performance analysis, otherwise use default.
64 */
wdenk7abf0c52004-04-18 21:45:42 +000065#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk9aea9532004-08-01 23:02:45 +000066#define CONFIG_BTB /* toggle branch predition */
wdenk7abf0c52004-04-18 21:45:42 +000067
wdenk9aea9532004-08-01 23:02:45 +000068#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Peter Tyser004eca02009-09-16 22:03:08 -050069#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk7abf0c52004-04-18 21:45:42 +000070
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
72#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
73#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk7abf0c52004-04-18 21:45:42 +000074
wdenk7abf0c52004-04-18 21:45:42 +000075
76/* Localbus SDRAM is an option, not all boards have it.
wdenk9aea9532004-08-01 23:02:45 +000077 * This address, however, is used to configure a 256M local bus
78 * window that includes the Config latch below.
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
81#define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
wdenk7abf0c52004-04-18 21:45:42 +000082
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
84#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk7abf0c52004-04-18 21:45:42 +000085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
87#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
88#define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */
89#undef CONFIG_SYS_FLASH_CHECKSUM
90#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
91#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk7abf0c52004-04-18 21:45:42 +000092
93/* The configuration latch is Chip Select 1.
wdenk9aea9532004-08-01 23:02:45 +000094 * It's an 8-bit latch in the lower 8 bits of the word.
wdenk7abf0c52004-04-18 21:45:42 +000095 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */
97#define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
98#define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
wdenk7abf0c52004-04-18 21:45:42 +000099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
wdenk7abf0c52004-04-18 21:45:42 +0000101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
103#define CONFIG_SYS_RAMBOOT
wdenk7abf0c52004-04-18 21:45:42 +0000104#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#undef CONFIG_SYS_RAMBOOT
wdenk7abf0c52004-04-18 21:45:42 +0000106#endif
107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#ifdef CONFIG_SYS_RAMBOOT
109#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
wdenk7abf0c52004-04-18 21:45:42 +0000110#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
wdenk7abf0c52004-04-18 21:45:42 +0000112#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
114#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
115#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenk7abf0c52004-04-18 21:45:42 +0000116
Kumar Galac360d9b2008-08-27 01:03:42 -0500117/* DDR Setup */
118#define CONFIG_FSL_DDR1
119#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
120#define CONFIG_DDR_SPD
121#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk7abf0c52004-04-18 21:45:42 +0000122
Kumar Galac360d9b2008-08-27 01:03:42 -0500123#undef CONFIG_DDR_ECC /* only for ECC DDR module */
124#define CONFIG_DDR_DLL /* possible DLL fix needed */
125#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
wdenk7abf0c52004-04-18 21:45:42 +0000126
Kumar Galac360d9b2008-08-27 01:03:42 -0500127#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
130#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +0000131
Kumar Galac360d9b2008-08-27 01:03:42 -0500132#define CONFIG_NUM_DDR_CONTROLLERS 1
133#define CONFIG_DIMM_SLOTS_PER_CTLR 1
134#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
135
136/* I2C addresses of SPD EEPROMs */
137#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
wdenk7abf0c52004-04-18 21:45:42 +0000138
139#undef CONFIG_CLOCKS_IN_MHZ
140
141/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
143#define CONFIG_SYS_OR2_PRELIM 0xfc006901
144#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
145#define CONFIG_SYS_LBC_LBCR 0x00000000
146#define CONFIG_SYS_LBC_LSRT 0x20000000
147#define CONFIG_SYS_LBC_MRTPR 0x20000000
148#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
149#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
150#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
151#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
152#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
wdenk7abf0c52004-04-18 21:45:42 +0000153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_INIT_RAM_LOCK 1
155#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
156#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk7abf0c52004-04-18 21:45:42 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
159#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
160#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk7abf0c52004-04-18 21:45:42 +0000161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
163#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk7abf0c52004-04-18 21:45:42 +0000164
165/* Serial Port */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200166#define CONFIG_CONS_ON_SCC /* define if console on SCC */
167#undef CONFIG_CONS_NONE /* define if console on something else */
168#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
wdenk7abf0c52004-04-18 21:45:42 +0000169
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200170#define CONFIG_BAUDRATE 38400
wdenk7abf0c52004-04-18 21:45:42 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk7abf0c52004-04-18 21:45:42 +0000173 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
174
175/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_HUSH_PARSER
177#ifdef CONFIG_SYS_HUSH_PARSER
178#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk7abf0c52004-04-18 21:45:42 +0000179#endif
180
Jon Loeliger20476722006-10-20 15:50:15 -0500181/*
182 * I2C
183 */
184#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
185#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk7abf0c52004-04-18 21:45:42 +0000186#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
188#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk7abf0c52004-04-18 21:45:42 +0000189#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */
wdenk7abf0c52004-04-18 21:45:42 +0000191#else
192/* I did the 'if 0' so we could keep the syntax above if ever needed. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#undef CONFIG_SYS_I2C_NOPROBES
wdenk7abf0c52004-04-18 21:45:42 +0000194#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk7abf0c52004-04-18 21:45:42 +0000196
wdenk9aea9532004-08-01 23:02:45 +0000197/* RapdIO Map configuration, mapped 1:1.
198*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
200#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
201#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */
wdenk9aea9532004-08-01 23:02:45 +0000202
203/* Standard 8560 PCI addressing, mapped 1:1.
204*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
206#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
207#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
208#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
209#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
210#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */
wdenk7abf0c52004-04-18 21:45:42 +0000211
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200212#if defined(CONFIG_PCI) /* PCI Ethernet card */
wdenk9aea9532004-08-01 23:02:45 +0000213
wdenk7abf0c52004-04-18 21:45:42 +0000214#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200215#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk9aea9532004-08-01 23:02:45 +0000216
217#undef CONFIG_EEPRO100
218#undef CONFIG_TULIP
219
220#if !defined(CONFIG_PCI_PNP)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200221 #define PCI_ENET0_IOADDR 0xe0000000
wdenk7abf0c52004-04-18 21:45:42 +0000222 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200223 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk7abf0c52004-04-18 21:45:42 +0000224#endif
wdenk9aea9532004-08-01 23:02:45 +0000225
226#undef CONFIG_PCI_SCAN_SHOW
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk9aea9532004-08-01 23:02:45 +0000228
229#endif /* CONFIG_PCI */
230
231#if defined(CONFIG_TSEC_ENET)
232
233#ifndef CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200234#define CONFIG_NET_MULTI 1
wdenk9aea9532004-08-01 23:02:45 +0000235#endif
236
wdenk7abf0c52004-04-18 21:45:42 +0000237#define CONFIG_MII 1 /* MII PHY management */
wdenk9aea9532004-08-01 23:02:45 +0000238
Kim Phillips255a35772007-05-16 16:52:19 -0500239#define CONFIG_TSEC1 1
240#define CONFIG_TSEC1_NAME "TSEC0"
241#define CONFIG_TSEC2 1
242#define CONFIG_TSEC2_NAME "TSEC1"
wdenk9aea9532004-08-01 23:02:45 +0000243
244#define TSEC1_PHY_ADDR 2
245#define TSEC2_PHY_ADDR 4
246#define TSEC1_PHYIDX 0
247#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500248#define TSEC1_FLAGS TSEC_GIGABIT
249#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500250#define CONFIG_ETHPRIME "TSEC0"
wdenk9aea9532004-08-01 23:02:45 +0000251
wdenk7abf0c52004-04-18 21:45:42 +0000252#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
wdenk9aea9532004-08-01 23:02:45 +0000253
wdenk7abf0c52004-04-18 21:45:42 +0000254#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
255#undef CONFIG_ETHER_NONE /* define if ether on something else */
256#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk9aea9532004-08-01 23:02:45 +0000257
258#if (CONFIG_ETHER_INDEX == 2)
wdenk7abf0c52004-04-18 21:45:42 +0000259 /*
260 * - Rx-CLK is CLK13
261 * - Tx-CLK is CLK14
262 * - Select bus for bd/buffers
263 * - Full duplex
264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
266 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
267 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
wdenk7abf0c52004-04-18 21:45:42 +0000268#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk7abf0c52004-04-18 21:45:42 +0000270#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271 #define CONFIG_SYS_FCC_PSMR 0
wdenk7abf0c52004-04-18 21:45:42 +0000272#endif
273 #define FETH2_RST 0x01
wdenk9aea9532004-08-01 23:02:45 +0000274#elif (CONFIG_ETHER_INDEX == 3)
wdenk7abf0c52004-04-18 21:45:42 +0000275 /* need more definitions here for FE3 */
276 #define FETH3_RST 0x80
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200277#endif /* CONFIG_ETHER_INDEX */
wdenk9aea9532004-08-01 23:02:45 +0000278
279/* MDIO is done through the TSEC0 control.
280*/
wdenk7abf0c52004-04-18 21:45:42 +0000281#define CONFIG_MII /* MII PHY management */
282#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
wdenk7abf0c52004-04-18 21:45:42 +0000283
wdenk7abf0c52004-04-18 21:45:42 +0000284#endif
285
286/* Environment */
287/* We use the top boot sector flash, so we have some 16K sectors for env
wdenk7abf0c52004-04-18 21:45:42 +0000288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200290 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200292 #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
293 #define CONFIG_ENV_SIZE 0x2000
wdenk7abf0c52004-04-18 21:45:42 +0000294#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200296 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200298 #define CONFIG_ENV_SIZE 0x2000
wdenk7abf0c52004-04-18 21:45:42 +0000299#endif
300
301#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
wdenk9aea9532004-08-01 23:02:45 +0000302#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
wdenk7abf0c52004-04-18 21:45:42 +0000303#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
304
305#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk7abf0c52004-04-18 21:45:42 +0000307
Jon Loeliger2835e512007-06-13 13:22:08 -0500308/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500309 * BOOTP options
310 */
311#define CONFIG_BOOTP_BOOTFILESIZE
312#define CONFIG_BOOTP_BOOTPATH
313#define CONFIG_BOOTP_GATEWAY
314#define CONFIG_BOOTP_HOSTNAME
315
316
317/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500318 * Command line configuration.
319 */
320#include <config_cmd_default.h>
321
322#define CONFIG_CMD_PING
323#define CONFIG_CMD_I2C
324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500326 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500327 #undef CONFIG_CMD_LOADS
wdenk7abf0c52004-04-18 21:45:42 +0000328#else
Jon Loeliger2835e512007-06-13 13:22:08 -0500329 #define CONFIG_CMD_ELF
wdenk7abf0c52004-04-18 21:45:42 +0000330#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500331
332#if defined(CONFIG_PCI)
333 #define CONFIG_CMD_PCI
334#endif
335
336#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
337 #define CONFIG_CMD_MII
338#endif
339
wdenk7abf0c52004-04-18 21:45:42 +0000340
341#undef CONFIG_WATCHDOG /* watchdog disabled */
342
343/*
344 * Miscellaneous configurable options
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_LONGHELP /* undef to save memory */
347#define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500348#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7abf0c52004-04-18 21:45:42 +0000350#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7abf0c52004-04-18 21:45:42 +0000352#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
354#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
355#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
356#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
357#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk7abf0c52004-04-18 21:45:42 +0000358
359/*
360 * For booting Linux, the board info and command line data
361 * have to be in the first 8 MB of memory, since this is
362 * the maximum mapped by the Linux kernel during initialization.
363 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7abf0c52004-04-18 21:45:42 +0000365
wdenk7abf0c52004-04-18 21:45:42 +0000366/*
367 * Internal Definitions
368 *
369 * Boot Flags
370 */
371#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
372#define BOOTFLAG_WARM 0x02 /* Software reboot */
373
Jon Loeliger2835e512007-06-13 13:22:08 -0500374#if defined(CONFIG_CMD_KGDB)
wdenk7abf0c52004-04-18 21:45:42 +0000375#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
376#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
377#endif
378
379/*Note: change below for your network setting!!! */
380#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500381#define CONFIG_HAS_ETH0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200382#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
wdenke2ffd592004-12-31 09:32:47 +0000383#define CONFIG_HAS_ETH1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200384#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
wdenke2ffd592004-12-31 09:32:47 +0000385#define CONFIG_HAS_ETH2
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200386#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
wdenk7abf0c52004-04-18 21:45:42 +0000387#endif
388
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200389#define CONFIG_SERVERIP 192.168.85.1
390#define CONFIG_IPADDR 192.168.85.60
wdenk7abf0c52004-04-18 21:45:42 +0000391#define CONFIG_GATEWAYIP 192.168.85.1
392#define CONFIG_NETMASK 255.255.255.0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200393#define CONFIG_HOSTNAME STX_GP3
394#define CONFIG_ROOTPATH /gppproot
395#define CONFIG_BOOTFILE uImage
wdenk9aea9532004-08-01 23:02:45 +0000396#define CONFIG_LOADADDR 0x1000000
wdenk7abf0c52004-04-18 21:45:42 +0000397
398#endif /* __CONFIG_H */