blob: a1020c1c6e2edae7a056391057eb6bbfd5fc00e6 [file] [log] [blame]
wdenkf4675562002-10-02 14:20:15 +00001/*
wdenkf12e5682003-07-07 20:07:54 +00002 * (C) Copyright 2000-2003
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
43#if 0
44#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
45#else
46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47#endif
48
49#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
50
51#define CONFIG_BOARD_TYPES 1 /* support board types */
52
53#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
54
55#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000056
57#define CONFIG_EXTRA_ENV_SETTINGS \
58 "nfsargs=setenv bootargs root=/dev/nfs rw " \
59 "nfsroot=$(serverip):$(rootpath)\0" \
60 "ramargs=setenv bootargs root=/dev/ram rw\0" \
61 "addip=setenv bootargs $(bootargs) " \
62 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
63 ":$(hostname):$(netdev):off panic=1\0" \
64 "flash_nfs=run nfsargs addip;" \
65 "bootm $(kernel_addr)\0" \
66 "flash_self=run ramargs addip;" \
67 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
68 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
69 "rootpath=/opt/eldk/ppc_8xx\0" \
wdenk3bac3512003-03-12 10:41:04 +000070 "bootfile=/tftpboot/TQM860L/uImage\0" \
wdenk6aff3112002-12-17 01:51:00 +000071 "kernel_addr=40040000\0" \
72 "ramdisk_addr=40100000\0" \
73 ""
74#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000075
76#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
77#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
78
79#undef CONFIG_WATCHDOG /* watchdog disabled */
80
81#define CONFIG_STATUS_LED 1 /* Status LED enabled */
82
83#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
84
85#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
86
87#define CONFIG_MAC_PARTITION
88#define CONFIG_DOS_PARTITION
89
90#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
91
92#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk6aff3112002-12-17 01:51:00 +000093 CFG_CMD_ASKENV | \
wdenkf4675562002-10-02 14:20:15 +000094 CFG_CMD_DHCP | \
95 CFG_CMD_IDE | \
96 CFG_CMD_DATE )
97
98/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
99#include <cmd_confdefs.h>
100
101/*
102 * Miscellaneous configurable options
103 */
104#define CFG_LONGHELP /* undef to save memory */
wdenk6aff3112002-12-17 01:51:00 +0000105#define CFG_PROMPT "=> " /* Monitor Command Prompt */
106
107#if 0
108#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
109#endif
110#ifdef CFG_HUSH_PARSER
111#define CFG_PROMPT_HUSH_PS2 "> "
112#endif
113
wdenkf4675562002-10-02 14:20:15 +0000114#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenk6aff3112002-12-17 01:51:00 +0000115#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000116#else
wdenk6aff3112002-12-17 01:51:00 +0000117#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000118#endif
119#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenk6aff3112002-12-17 01:51:00 +0000120#define CFG_MAXARGS 16 /* max number of command args */
wdenkf4675562002-10-02 14:20:15 +0000121#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
122
123#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
124#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
125
126#define CFG_LOAD_ADDR 0x100000 /* default load address */
127
wdenk6aff3112002-12-17 01:51:00 +0000128#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf4675562002-10-02 14:20:15 +0000129
130#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
131
132/*
133 * Low Level Configuration Settings
134 * (address mappings, register initial values, etc.)
135 * You should know what you are doing if you make changes here.
136 */
137/*-----------------------------------------------------------------------
138 * Internal Memory Mapped Register
139 */
140#define CFG_IMMR 0xFFF00000
141
142/*-----------------------------------------------------------------------
143 * Definitions for initial stack pointer and data area (in DPRAM)
144 */
145#define CFG_INIT_RAM_ADDR CFG_IMMR
146#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
147#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
148#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
149#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
150
151/*-----------------------------------------------------------------------
152 * Start addresses for the final memory configuration
153 * (Set up by the startup code)
154 * Please note that CFG_SDRAM_BASE _must_ start at 0
155 */
156#define CFG_SDRAM_BASE 0x00000000
157#define CFG_FLASH_BASE 0x40000000
158#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
159#define CFG_MONITOR_BASE CFG_FLASH_BASE
160#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
161
162/*
163 * For booting Linux, the board info and command line data
164 * have to be in the first 8 MB of memory, since this is
165 * the maximum mapped by the Linux kernel during initialization.
166 */
167#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
168
169/*-----------------------------------------------------------------------
170 * FLASH organization
171 */
172#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenkaacf9a42003-01-17 16:27:01 +0000173#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000174
175#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
176#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
177
178#define CFG_ENV_IS_IN_FLASH 1
179#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
180#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
181
182/* Address and size of Redundant Environment Sector */
183#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
184#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
185
186/*-----------------------------------------------------------------------
187 * Hardware Information Block
188 */
189#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
190#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
191#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
192
193/*-----------------------------------------------------------------------
194 * Cache Configuration
195 */
196#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
197#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
198#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
199#endif
200
201/*-----------------------------------------------------------------------
202 * SYPCR - System Protection Control 11-9
203 * SYPCR can only be written once after reset!
204 *-----------------------------------------------------------------------
205 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
206 */
207#if defined(CONFIG_WATCHDOG)
208#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
209 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
210#else
211#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
212#endif
213
214/*-----------------------------------------------------------------------
215 * SIUMCR - SIU Module Configuration 11-6
216 *-----------------------------------------------------------------------
217 * PCMCIA config., multi-function pin tri-state
218 */
219#ifndef CONFIG_CAN_DRIVER
220#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
221#else /* we must activate GPL5 in the SIUMCR for CAN */
222#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
223#endif /* CONFIG_CAN_DRIVER */
224
225/*-----------------------------------------------------------------------
226 * TBSCR - Time Base Status and Control 11-26
227 *-----------------------------------------------------------------------
228 * Clear Reference Interrupt Status, Timebase freezing enabled
229 */
230#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
231
232/*-----------------------------------------------------------------------
233 * RTCSC - Real-Time Clock Status and Control Register 11-27
234 *-----------------------------------------------------------------------
235 */
236#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
237
238/*-----------------------------------------------------------------------
239 * PISCR - Periodic Interrupt Status and Control 11-31
240 *-----------------------------------------------------------------------
241 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
242 */
243#define CFG_PISCR (PISCR_PS | PISCR_PITF)
244
245/*-----------------------------------------------------------------------
246 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
247 *-----------------------------------------------------------------------
248 * Reset PLL lock status sticky bit, timer expired status bit and timer
249 * interrupt status bit
250 *
251 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
252 */
253#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
254#define CFG_PLPRCR \
255 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
wdenkf12e5682003-07-07 20:07:54 +0000256#else /* up to 66 MHz we use a 1:1 clock */
wdenkf4675562002-10-02 14:20:15 +0000257#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
258#endif /* CONFIG_80MHz */
259
260/*-----------------------------------------------------------------------
261 * SCCR - System Clock and reset Control Register 15-27
262 *-----------------------------------------------------------------------
263 * Set clock output, timebase and RTC source and divider,
264 * power management and some other internal clocks
265 */
266#define SCCR_MASK SCCR_EBDF11
267#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
268#define CFG_SCCR (/* SCCR_TBS | */ \
269 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
270 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
271 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000272#else /* up to 66 MHz we use a 1:1 clock */
wdenkf4675562002-10-02 14:20:15 +0000273#define CFG_SCCR (SCCR_TBS | \
274 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
275 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
276 SCCR_DFALCD00)
277#endif /* CONFIG_80MHz */
278
279/*-----------------------------------------------------------------------
280 * PCMCIA stuff
281 *-----------------------------------------------------------------------
282 *
283 */
284#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
285#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
286#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
287#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
288#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
289#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
290#define CFG_PCMCIA_IO_ADDR (0xEC000000)
291#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
292
293/*-----------------------------------------------------------------------
294 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
295 *-----------------------------------------------------------------------
296 */
297
298#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
299
300#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
301#undef CONFIG_IDE_LED /* LED for ide not supported */
302#undef CONFIG_IDE_RESET /* reset for ide not supported */
303
304#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
305#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
306
307#define CFG_ATA_IDE0_OFFSET 0x0000
308
309#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
310
311/* Offset for data I/O */
312#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
313
314/* Offset for normal register accesses */
315#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
316
317/* Offset for alternate registers */
318#define CFG_ATA_ALT_OFFSET 0x0100
319
wdenkf4675562002-10-02 14:20:15 +0000320/*-----------------------------------------------------------------------
321 *
322 *-----------------------------------------------------------------------
323 *
324 */
wdenkf4675562002-10-02 14:20:15 +0000325#define CFG_DER 0
326
327/*
328 * Init Memory Controller:
329 *
330 * BR0/1 and OR0/1 (FLASH)
331 */
332
333#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
334#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
335
336/* used to re-map FLASH both when starting from SRAM or FLASH:
337 * restrict access enough to keep SRAM working (if any)
338 * but not too much to meddle with FLASH accesses
339 */
340#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
341#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
342
343/*
344 * FLASH timing:
345 */
346#if defined(CONFIG_80MHz)
347/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
348#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
349 OR_SCY_3_CLK | OR_EHTR | OR_BI)
350#elif defined(CONFIG_66MHz)
351/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
352#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
353 OR_SCY_3_CLK | OR_EHTR | OR_BI)
354#else /* 50 MHz */
355/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
356#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
357 OR_SCY_2_CLK | OR_EHTR | OR_BI)
358#endif /*CONFIG_??MHz */
359
360#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
361#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
362#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
363
364#define CFG_OR1_REMAP CFG_OR0_REMAP
365#define CFG_OR1_PRELIM CFG_OR0_PRELIM
366#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
367
368/*
369 * BR2/3 and OR2/3 (SDRAM)
370 *
371 */
372#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
373#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
374#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
375
376/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
377#define CFG_OR_TIMING_SDRAM 0x00000A00
378
379#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
380#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
381
382#ifndef CONFIG_CAN_DRIVER
383#define CFG_OR3_PRELIM CFG_OR2_PRELIM
384#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
385#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
386#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
387#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
388#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
389#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
390 BR_PS_8 | BR_MS_UPMB | BR_V )
391#endif /* CONFIG_CAN_DRIVER */
392
393/*
394 * Memory Periodic Timer Prescaler
395 *
396 * The Divider for PTA (refresh timer) configuration is based on an
397 * example SDRAM configuration (64 MBit, one bank). The adjustment to
398 * the number of chip selects (NCS) and the actually needed refresh
399 * rate is done by setting MPTPR.
400 *
401 * PTA is calculated from
402 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
403 *
404 * gclk CPU clock (not bus clock!)
405 * Trefresh Refresh cycle * 4 (four word bursts used)
406 *
407 * 4096 Rows from SDRAM example configuration
408 * 1000 factor s -> ms
409 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
410 * 4 Number of refresh cycles per period
411 * 64 Refresh cycle in ms per number of rows
412 * --------------------------------------------
413 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
414 *
415 * 50 MHz => 50.000.000 / Divider = 98
416 * 66 Mhz => 66.000.000 / Divider = 129
417 * 80 Mhz => 80.000.000 / Divider = 156
418 */
419#if defined(CONFIG_80MHz)
420#define CFG_MAMR_PTA 156
421#elif defined(CONFIG_66MHz)
422#define CFG_MAMR_PTA 129
423#else /* 50 MHz */
424#define CFG_MAMR_PTA 98
425#endif /*CONFIG_??MHz */
426
427/*
428 * For 16 MBit, refresh rates could be 31.3 us
429 * (= 64 ms / 2K = 125 / quad bursts).
430 * For a simpler initialization, 15.6 us is used instead.
431 *
432 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
433 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
434 */
435#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
436#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
437
438/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
439#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
440#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
441
442/*
443 * MAMR settings for SDRAM
444 */
445
446/* 8 column SDRAM */
447#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
448 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
449 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
450/* 9 column SDRAM */
451#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
452 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
453 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
454
455
456/*
457 * Internal Definitions
458 *
459 * Boot Flags
460 */
461#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
462#define BOOTFLAG_WARM 0x02 /* Software reboot */
463
464#endif /* __CONFIG_H */