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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada5894ca02014-10-03 19:21:06 +09002/*
Masahiro Yamada928f3242016-08-25 21:03:41 +09003 * Copyright (C) 2012-2014 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada5894ca02014-10-03 19:21:06 +09006 */
7
Simon Glass9a3b4ce2019-12-28 10:45:01 -07008#include <cpu_func.h>
Masahiro Yamadaf6e7f072015-05-29 17:30:00 +09009#include <linux/io.h>
Masahiro Yamada928f3242016-08-25 21:03:41 +090010#include <asm/secure.h>
Masahiro Yamada107b3fb2016-01-09 01:51:13 +090011
12#include "sc-regs.h"
Masahiro Yamada5894ca02014-10-03 19:21:06 +090013
Masahiro Yamada928f3242016-08-25 21:03:41 +090014/* If PSCI is enabled, this is used for SYSTEM_RESET function */
15#ifdef CONFIG_ARMV7_PSCI
16#define __SECURE __secure
17#else
18#define __SECURE
19#endif
20
Harald Seiler35b65dd2020-12-15 16:47:52 +010021void __SECURE reset_cpu(void)
Masahiro Yamada5894ca02014-10-03 19:21:06 +090022{
23 u32 tmp;
24
Masahiro Yamada739ba412019-07-10 20:07:41 +090025 writel(5, sc_base + SC_IRQTIMSET); /* default value */
Masahiro Yamada5894ca02014-10-03 19:21:06 +090026
Masahiro Yamada739ba412019-07-10 20:07:41 +090027 tmp = readl(sc_base + SC_SLFRSTSEL);
Masahiro Yamada5894ca02014-10-03 19:21:06 +090028 tmp &= ~0x3; /* mask [1:0] */
29 tmp |= 0x0; /* XRST reboot */
Masahiro Yamada739ba412019-07-10 20:07:41 +090030 writel(tmp, sc_base + SC_SLFRSTSEL);
Masahiro Yamada5894ca02014-10-03 19:21:06 +090031
Masahiro Yamada739ba412019-07-10 20:07:41 +090032 tmp = readl(sc_base + SC_SLFRSTCTL);
Masahiro Yamada5894ca02014-10-03 19:21:06 +090033 tmp |= 0x1;
Masahiro Yamada739ba412019-07-10 20:07:41 +090034 writel(tmp, sc_base + SC_SLFRSTCTL);
Masahiro Yamada5894ca02014-10-03 19:21:06 +090035}