| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Peter Griffin | 242b2f0 | 2015-07-30 18:55:21 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2015 Linaro |
| 4 | * Peter Griffin <peter.griffin@linaro.org> |
| Peter Griffin | 242b2f0 | 2015-07-30 18:55:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __HI6553_PMIC_H__ |
| 8 | #define __HI6553_PMIC_H__ |
| 9 | |
| 10 | /* Registers */ |
| 11 | enum { |
| 12 | HI6553_VERSION_REG = 0x000, |
| 13 | HI6553_ENABLE2_LDO1_8 = 0x029, |
| 14 | HI6553_DISABLE2_LDO1_8, |
| 15 | HI6553_ONOFF_STATUS2_LDO1_8, |
| 16 | HI6553_ENABLE3_LDO9_16, |
| 17 | HI6553_DISABLE3_LDO9_16, |
| 18 | HI6553_ONOFF_STATUS3_LDO9_16, |
| 19 | |
| 20 | HI6553_DISABLE6_XO_CLK = 0x036, |
| 21 | HI6553_PERI_EN_MARK = 0x040, |
| 22 | HI6553_BUCK2_REG1 = 0x04a, |
| 23 | HI6553_BUCK2_REG5 = 0x04e, |
| 24 | HI6553_BUCK2_REG6, |
| 25 | |
| 26 | HI6553_BUCK3_REG3 = 0x054, |
| 27 | HI6553_BUCK3_REG5 = 0x056, |
| 28 | HI6553_BUCK3_REG6, |
| 29 | HI6553_BUCK4_REG2 = 0x05b, |
| 30 | HI6553_BUCK4_REG5 = 0x05e, |
| 31 | HI6553_BUCK4_REG6, |
| 32 | |
| 33 | HI6553_CLK_TOP0 = 0x063, |
| 34 | HI6553_CLK_TOP3 = 0x066, |
| 35 | HI6553_CLK_TOP4, |
| 36 | HI6553_VSET_BUCK2_ADJ = 0x06d, |
| 37 | HI6553_VSET_BUCK3_ADJ, |
| 38 | HI6553_LDO7_REG_ADJ = 0x078, |
| 39 | HI6553_LDO10_REG_ADJ = 0x07b, |
| 40 | HI6553_LDO19_REG_ADJ = 0x084, |
| 41 | HI6553_LDO20_REG_ADJ, |
| 42 | HI6553_DR_LED_CTRL = 0x098, |
| 43 | HI6553_DR_OUT_CTRL, |
| 44 | HI6553_DR3_ISET, |
| 45 | HI6553_DR3_START_DEL, |
| 46 | HI6553_DR4_ISET, |
| 47 | HI6553_DR4_START_DEL, |
| 48 | HI6553_DR345_TIM_CONF0 = 0x0a0, |
| 49 | HI6553_NP_REG_ADJ1 = 0x0be, |
| 50 | HI6553_NP_REG_CHG = 0x0c0, |
| 51 | HI6553_BUCK01_CTRL2 = 0x0d9, |
| 52 | HI6553_BUCK0_CTRL1 = 0x0dd, |
| 53 | HI6553_BUCK0_CTRL5 = 0x0e1, |
| 54 | HI6553_BUCK0_CTRL7 = 0x0e3, |
| 55 | HI6553_BUCK1_CTRL1 = 0x0e8, |
| 56 | HI6553_BUCK1_CTRL5 = 0x0ec, |
| 57 | HI6553_BUCK1_CTRL7 = 0x0ef, |
| 58 | HI6553_CLK19M2_600_586_EN = 0x0fe, |
| 59 | }; |
| 60 | |
| 61 | #define HI6553_DISABLE6_XO_CLK_BB (1 << 0) |
| 62 | #define HI6553_DISABLE6_XO_CLK_CONN (1 << 1) |
| 63 | #define HI6553_DISABLE6_XO_CLK_NFC (1 << 2) |
| 64 | #define HI6553_DISABLE6_XO_CLK_RF1 (1 << 3) |
| 65 | #define HI6553_DISABLE6_XO_CLK_RF2 (1 << 4) |
| 66 | |
| 67 | #define HI6553_LED_START_DELAY_TIME 0x00 |
| 68 | #define HI6553_LED_ELEC_VALUE 0x07 |
| 69 | #define HI6553_LED_LIGHT_TIME 0xf0 |
| 70 | #define HI6553_LED_GREEN_ENABLE (1 << 1) |
| 71 | #define HI6553_LED_OUT_CTRL 0x00 |
| 72 | |
| 73 | #define HI6553_PMU_V300 0x30 |
| 74 | #define HI6553_PMU_V310 0x31 |
| 75 | |
| 76 | int power_hi6553_init(u8 *base); |
| 77 | |
| 78 | #endif /* __HI6553_PMIC_H__ */ |