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Pavel Machek5095ee02014-09-08 14:08:45 +02001/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
Dinh Nguyen48275c92015-12-03 16:05:59 -06006#ifndef __CONFIG_SOCFPGA_COMMON_H__
7#define __CONFIG_SOCFPGA_COMMON_H__
Pavel Machek5095ee02014-09-08 14:08:45 +02008
Pavel Machek5095ee02014-09-08 14:08:45 +02009
10/* Virtual target or real hardware */
11#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
12
Pavel Machek5095ee02014-09-08 14:08:45 +020013#define CONFIG_SYS_THUMB_BUILD
14
Pavel Machek5095ee02014-09-08 14:08:45 +020015/*
16 * High level configuration
17 */
18#define CONFIG_DISPLAY_CPUINFO
Marek Vasut7287d5f2014-12-30 21:29:35 +010019#define CONFIG_DISPLAY_BOARDINFO_LATE
Marek Vasut9ec74142015-07-22 05:40:12 +020020#define CONFIG_ARCH_MISC_INIT
Marek Vasutfc520892014-10-18 03:52:36 +020021#define CONFIG_ARCH_EARLY_INIT_R
Pavel Machek5095ee02014-09-08 14:08:45 +020022#define CONFIG_SYS_NO_FLASH
23#define CONFIG_CLOCKS
24
Marek Vasut251faa22015-07-09 03:41:53 +020025#define CONFIG_CRC32_VERIFY
26
Pavel Machek5095ee02014-09-08 14:08:45 +020027#define CONFIG_FIT
28#define CONFIG_OF_LIBFDT
29#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
30
31#define CONFIG_TIMESTAMP /* Print image info with timestamp */
32
33/*
34 * Memory configurations
35 */
36#define CONFIG_NR_DRAM_BANKS 1
37#define PHYS_SDRAM_1 0x0
Marek Vasut0223a952014-11-04 04:25:09 +010038#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
Pavel Machek5095ee02014-09-08 14:08:45 +020039#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
40#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
41
42#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
Marek Vasut7599b532015-07-12 15:23:28 +020043#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
44#define CONFIG_SYS_INIT_SP_OFFSET \
45 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
46#define CONFIG_SYS_INIT_SP_ADDR \
47 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
Pavel Machek5095ee02014-09-08 14:08:45 +020048
49#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
50#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
51#define CONFIG_SYS_TEXT_BASE 0x08000040
52#else
53#define CONFIG_SYS_TEXT_BASE 0x01000040
54#endif
55
56/*
57 * U-Boot general configurations
58 */
59#define CONFIG_SYS_LONGHELP
60#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
61#define CONFIG_SYS_PBSIZE \
62 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
63 /* Print buffer size */
64#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
65#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
66 /* Boot argument buffer size */
67#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
68#define CONFIG_AUTO_COMPLETE /* Command auto complete */
69#define CONFIG_CMDLINE_EDITING /* Command history etc */
70#define CONFIG_SYS_HUSH_PARSER
71
Marek Vasutea082342015-12-05 20:08:21 +010072#ifndef CONFIG_SYS_HOSTNAME
73#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
74#endif
75
Pavel Machek5095ee02014-09-08 14:08:45 +020076/*
77 * Cache
78 */
Pavel Machek5095ee02014-09-08 14:08:45 +020079#define CONFIG_SYS_CACHELINE_SIZE 32
80#define CONFIG_SYS_L2_PL310
81#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
82
83/*
Dinh Nguyencdd4e6c2015-06-02 22:52:50 -050084 * SDRAM controller
85 */
86#define CONFIG_ALTERA_SDRAM
87
88/*
Marek Vasut8a78ca92014-09-27 01:18:29 +020089 * EPCS/EPCQx1 Serial Flash Controller
90 */
91#ifdef CONFIG_ALTERA_SPI
92#define CONFIG_CMD_SPI
93#define CONFIG_CMD_SF
94#define CONFIG_SF_DEFAULT_SPEED 30000000
Marek Vasut8a78ca92014-09-27 01:18:29 +020095#define CONFIG_SPI_FLASH_BAR
96/*
97 * The base address is configurable in QSys, each board must specify the
98 * base address based on it's particular FPGA configuration. Please note
99 * that the address here is incremented by 0x400 from the Base address
100 * selected in QSys, since the SPI registers are at offset +0x400.
101 * #define CONFIG_SYS_SPI_BASE 0xff240400
102 */
103#endif
104
105/*
Pavel Machek5095ee02014-09-08 14:08:45 +0200106 * Ethernet on SoC (EMAC)
107 */
108#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
Pavel Machek5095ee02014-09-08 14:08:45 +0200109#define CONFIG_DW_ALTDESCRIPTOR
110#define CONFIG_MII
111#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
Pavel Machek5095ee02014-09-08 14:08:45 +0200112#define CONFIG_PHY_GIGE
113#endif
114
115/*
116 * FPGA Driver
117 */
118#ifdef CONFIG_CMD_FPGA
119#define CONFIG_FPGA
120#define CONFIG_FPGA_ALTERA
121#define CONFIG_FPGA_SOCFPGA
122#define CONFIG_FPGA_COUNT 1
123#endif
124
125/*
126 * L4 OSC1 Timer 0
127 */
128/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
129#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
130#define CONFIG_SYS_TIMER_COUNTS_DOWN
131#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
132#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
133#define CONFIG_SYS_TIMER_RATE 2400000
134#else
135#define CONFIG_SYS_TIMER_RATE 25000000
136#endif
137
138/*
139 * L4 Watchdog
140 */
141#ifdef CONFIG_HW_WATCHDOG
142#define CONFIG_DESIGNWARE_WATCHDOG
143#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
144#define CONFIG_DW_WDT_CLOCK_KHZ 25000
Stefan Roesed0e932d2014-12-19 13:49:10 +0100145#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000
Pavel Machek5095ee02014-09-08 14:08:45 +0200146#endif
147
148/*
149 * MMC Driver
150 */
151#ifdef CONFIG_CMD_MMC
152#define CONFIG_MMC
153#define CONFIG_BOUNCE_BUFFER
154#define CONFIG_GENERIC_MMC
155#define CONFIG_DWMMC
156#define CONFIG_SOCFPGA_DWMMC
157#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
Pavel Machek5095ee02014-09-08 14:08:45 +0200158/* FIXME */
159/* using smaller max blk cnt to avoid flooding the limited stack we have */
160#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
161#endif
162
Stefan Roese7fb0f592014-11-07 12:37:52 +0100163/*
Marek Vasutc339ea52015-12-20 04:00:46 +0100164 * NAND Support
165 */
166#ifdef CONFIG_NAND_DENALI
167#define CONFIG_SYS_MAX_NAND_DEVICE 1
168#define CONFIG_SYS_NAND_MAX_CHIPS 1
169#define CONFIG_SYS_NAND_ONFI_DETECTION
170#define CONFIG_NAND_DENALI_ECC_SIZE 512
171#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
172#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
173#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
174#endif
175
176/*
Stefan Roeseebcaf962014-10-30 09:33:13 +0100177 * I2C support
178 */
179#define CONFIG_SYS_I2C
180#define CONFIG_SYS_I2C_DW
181#define CONFIG_SYS_I2C_BUS_MAX 4
182#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
183#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
184#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
185#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
186/* Using standard mode which the speed up to 100Kb/s */
187#define CONFIG_SYS_I2C_SPEED 100000
188#define CONFIG_SYS_I2C_SPEED1 100000
189#define CONFIG_SYS_I2C_SPEED2 100000
190#define CONFIG_SYS_I2C_SPEED3 100000
191/* Address of device when used as slave */
192#define CONFIG_SYS_I2C_SLAVE 0x02
193#define CONFIG_SYS_I2C_SLAVE1 0x02
194#define CONFIG_SYS_I2C_SLAVE2 0x02
195#define CONFIG_SYS_I2C_SLAVE3 0x02
196#ifndef __ASSEMBLY__
197/* Clock supplied to I2C controller in unit of MHz */
198unsigned int cm_get_l4_sp_clk_hz(void);
199#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
200#endif
201#define CONFIG_CMD_I2C
202
Pavel Machek5095ee02014-09-08 14:08:45 +0200203/*
Stefan Roese7fb0f592014-11-07 12:37:52 +0100204 * QSPI support
205 */
Stefan Roese7fb0f592014-11-07 12:37:52 +0100206/* Enable multiple SPI NOR flash manufacturers */
Marek Vasutcbc95442015-07-21 16:17:39 +0200207#ifndef CONFIG_SPL_BUILD
Stefan Roese7fb0f592014-11-07 12:37:52 +0100208#define CONFIG_SPI_FLASH_MTD
Marek Vasut55b43122015-07-24 06:15:14 +0200209#define CONFIG_CMD_MTDPARTS
210#define CONFIG_MTD_DEVICE
211#define CONFIG_MTD_PARTITIONS
Chin Liang See55702fe2015-12-21 23:01:51 +0800212#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
Marek Vasutcbc95442015-07-21 16:17:39 +0200213#endif
Stefan Roese7fb0f592014-11-07 12:37:52 +0100214/* QSPI reference clock */
215#ifndef __ASSEMBLY__
216unsigned int cm_get_qspi_controller_clk_hz(void);
217#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
218#endif
219#define CONFIG_CQSPI_DECODER 0
220#define CONFIG_CMD_SF
Marek Vasutab48b192015-07-20 05:48:37 +0200221#define CONFIG_SPI_FLASH_BAR
Stefan Roese7fb0f592014-11-07 12:37:52 +0100222
Marek Vasut0c745d02015-08-19 23:23:53 +0200223/*
224 * Designware SPI support
225 */
Stefan Roesea6e73592014-11-07 13:50:34 +0100226#define CONFIG_CMD_SPI
Stefan Roesea6e73592014-11-07 13:50:34 +0100227
Stefan Roese7fb0f592014-11-07 12:37:52 +0100228/*
Pavel Machek5095ee02014-09-08 14:08:45 +0200229 * Serial Driver
230 */
Pavel Machek5095ee02014-09-08 14:08:45 +0200231#define CONFIG_SYS_NS16550_SERIAL
232#define CONFIG_SYS_NS16550_REG_SIZE -4
233#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
234#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
235#define CONFIG_SYS_NS16550_CLK 1000000
236#else
237#define CONFIG_SYS_NS16550_CLK 100000000
238#endif
239#define CONFIG_CONS_INDEX 1
240#define CONFIG_BAUDRATE 115200
241
242/*
Marek Vasut20cadbb2014-10-24 23:34:25 +0200243 * USB
244 */
245#ifdef CONFIG_CMD_USB
246#define CONFIG_USB_DWC2
247#define CONFIG_USB_STORAGE
Marek Vasut20cadbb2014-10-24 23:34:25 +0200248#endif
249
250/*
Marek Vasut0223a952014-11-04 04:25:09 +0100251 * USB Gadget (DFU, UMS)
252 */
253#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
254#define CONFIG_USB_GADGET
Marek Vasute30824f2015-08-19 23:27:26 +0200255#define CONFIG_USB_GADGET_DWC2_OTG
Marek Vasut0223a952014-11-04 04:25:09 +0100256#define CONFIG_USB_GADGET_DUALSPEED
257#define CONFIG_USB_GADGET_VBUS_DRAW 2
258
259/* USB Composite download gadget - g_dnl */
Paul Kocialkowski01acd6a2015-06-12 19:56:58 +0200260#define CONFIG_USB_GADGET_DOWNLOAD
261#define CONFIG_USB_FUNCTION_MASS_STORAGE
Marek Vasut0223a952014-11-04 04:25:09 +0100262
Paul Kocialkowski01acd6a2015-06-12 19:56:58 +0200263#define CONFIG_USB_FUNCTION_DFU
Marek Vasuteba522a2015-12-20 04:00:45 +0100264#ifdef CONFIG_DM_MMC
Marek Vasut0223a952014-11-04 04:25:09 +0100265#define CONFIG_DFU_MMC
Marek Vasuteba522a2015-12-20 04:00:45 +0100266#endif
Marek Vasut0223a952014-11-04 04:25:09 +0100267#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
268#define DFU_DEFAULT_POLL_TIMEOUT 300
269
270/* USB IDs */
271#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */
272#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */
273#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
274#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
275#ifndef CONFIG_G_DNL_MANUFACTURER
Marek Vasuta5cad672015-12-05 20:05:46 +0100276#define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR
Marek Vasut0223a952014-11-04 04:25:09 +0100277#endif
278#endif
279
280/*
Pavel Machek5095ee02014-09-08 14:08:45 +0200281 * U-Boot environment
282 */
283#define CONFIG_SYS_CONSOLE_IS_IN_ENV
284#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
285#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Pavel Machek5095ee02014-09-08 14:08:45 +0200286#define CONFIG_ENV_SIZE 4096
287
Chin Liang See79cc48e2015-12-21 21:02:45 +0800288/* Environment for SDMMC boot */
289#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
290#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
291#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
292#endif
293
Pavel Machek5095ee02014-09-08 14:08:45 +0200294/*
Chin Liang See55702fe2015-12-21 23:01:51 +0800295 * mtd partitioning for serial NOR flash
296 *
297 * device nor0 <ff705000.spi.0>, # parts = 6
298 * #: name size offset mask_flags
299 * 0: u-boot 0x00100000 0x00000000 0
300 * 1: env1 0x00040000 0x00100000 0
301 * 2: env2 0x00040000 0x00140000 0
302 * 3: UBI 0x03e80000 0x00180000 0
303 * 4: boot 0x00e80000 0x00180000 0
304 * 5: rootfs 0x01000000 0x01000000 0
305 *
306 */
307#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
308#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\
309 "1m(u-boot)," \
310 "256k(env1)," \
311 "256k(env2)," \
312 "14848k(boot)," \
313 "16m(rootfs)," \
314 "-@1536k(UBI)\0"
315#endif
316
Chin Liang See6cdd4652015-12-22 15:32:26 +0800317/* UBI and UBIFS support */
318#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
319#define CONFIG_CMD_UBI
320#define CONFIG_CMD_UBIFS
321#define CONFIG_RBTREE
322#define CONFIG_LZO
323#endif
324
Chin Liang See55702fe2015-12-21 23:01:51 +0800325/*
Pavel Machek5095ee02014-09-08 14:08:45 +0200326 * SPL
Marek Vasut34584d12014-10-16 12:25:40 +0200327 *
328 * SRAM Memory layout:
329 *
330 * 0xFFFF_0000 ...... Start of SRAM
331 * 0xFFFF_xxxx ...... Top of stack (grows down)
332 * 0xFFFF_yyyy ...... Malloc area
333 * 0xFFFF_zzzz ...... Global Data
334 * 0xFFFF_FF00 ...... End of SRAM
Pavel Machek5095ee02014-09-08 14:08:45 +0200335 */
336#define CONFIG_SPL_FRAMEWORK
Pavel Machek5095ee02014-09-08 14:08:45 +0200337#define CONFIG_SPL_RAM_DEVICE
Marek Vasut34584d12014-10-16 12:25:40 +0200338#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
Dinh Nguyen68681602015-03-30 17:01:03 -0500339#define CONFIG_SPL_MAX_SIZE (64 * 1024)
Marek Vasut7599b532015-07-12 15:23:28 +0200340#ifdef CONFIG_SPL_BUILD
341#define CONFIG_SYS_MALLOC_SIMPLE
342#endif
Pavel Machek5095ee02014-09-08 14:08:45 +0200343
Pavel Machek5095ee02014-09-08 14:08:45 +0200344#define CONFIG_SPL_LIBCOMMON_SUPPORT
345#define CONFIG_SPL_LIBGENERIC_SUPPORT
346#define CONFIG_SPL_WATCHDOG_SUPPORT
347#define CONFIG_SPL_SERIAL_SUPPORT
Marek Vasut4197a0f2015-12-20 04:00:44 +0100348#ifdef CONFIG_DM_MMC
Marek Vasutd3f34e72015-07-10 00:04:23 +0200349#define CONFIG_SPL_MMC_SUPPORT
Marek Vasut4197a0f2015-12-20 04:00:44 +0100350#endif
351#ifdef CONFIG_DM_SPI
Marek Vasut346d6f52015-07-21 07:50:03 +0200352#define CONFIG_SPL_SPI_SUPPORT
Marek Vasut4197a0f2015-12-20 04:00:44 +0100353#endif
Marek Vasutc339ea52015-12-20 04:00:46 +0100354#ifdef CONFIG_SPL_NAND_DENALI
355#define CONFIG_SPL_NAND_SUPPORT
356#endif
Marek Vasutd3f34e72015-07-10 00:04:23 +0200357
358/* SPL SDMMC boot support */
359#ifdef CONFIG_SPL_MMC_SUPPORT
360#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
361#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
362#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
363#define CONFIG_SPL_LIBDISK_SUPPORT
364#else
365#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3
366#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
367#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
368#endif
369#endif
Pavel Machek5095ee02014-09-08 14:08:45 +0200370
Marek Vasut346d6f52015-07-21 07:50:03 +0200371/* SPL QSPI boot support */
372#ifdef CONFIG_SPL_SPI_SUPPORT
373#define CONFIG_DM_SEQ_ALIAS 1
374#define CONFIG_SPL_SPI_FLASH_SUPPORT
375#define CONFIG_SPL_SPI_LOAD
376#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
377#endif
378
Marek Vasutc339ea52015-12-20 04:00:46 +0100379/* SPL NAND boot support */
380#ifdef CONFIG_SPL_NAND_SUPPORT
381#define CONFIG_SYS_NAND_USE_FLASH_BBT
382#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
383#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
384#endif
385
Dinh Nguyena717b812015-03-30 17:01:12 -0500386/*
387 * Stack setup
388 */
389#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
390
Dinh Nguyen48275c92015-12-03 16:05:59 -0600391#endif /* __CONFIG_SOCFPGA_COMMON_H__ */