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Marian Balakowicz991425f2006-03-14 16:24:38 +01001/*
Wolfgang Denk2ae18242010-10-06 09:05:45 +02002 * (C) Copyright 2006-2010
Marian Balakowicz991425f2006-03-14 16:24:38 +01003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Marian Balakowicz991425f2006-03-14 16:24:38 +01006 */
7
8/*
9 * mpc8349emds board configuration file
10 *
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Marian Balakowicz991425f2006-03-14 16:24:38 +010016/*
17 * High Level Configuration Options
18 */
19#define CONFIG_E300 1 /* E300 Family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050020#define CONFIG_MPC834x 1 /* MPC834x family */
Marian Balakowicz991425f2006-03-14 16:24:38 +010021#define CONFIG_MPC8349 1 /* MPC8349 specific */
22#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
23
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xFE000000
25
26#define CONFIG_PCI_66M
27#ifdef CONFIG_PCI_66M
Marian Balakowicz991425f2006-03-14 16:24:38 +010028#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
29#else
30#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
31#endif
32
Ira W. Snyder447ad572008-08-22 11:00:15 -070033#ifdef CONFIG_PCISLAVE
Ira W. Snyder447ad572008-08-22 11:00:15 -070034#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
35#endif /* CONFIG_PCISLAVE */
36
Marian Balakowicz991425f2006-03-14 16:24:38 +010037#ifndef CONFIG_SYS_CLK_FREQ
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038#ifdef CONFIG_PCI_66M
Marian Balakowicz991425f2006-03-14 16:24:38 +010039#define CONFIG_SYS_CLK_FREQ 66000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -050040#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
Marian Balakowicz991425f2006-03-14 16:24:38 +010041#else
42#define CONFIG_SYS_CLK_FREQ 33000000
Kumar Gala8fe9bf62006-04-20 13:45:32 -050043#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
Marian Balakowicz991425f2006-03-14 16:24:38 +010044#endif
45#endif
46
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_IMMR 0xE0000000
Marian Balakowicz991425f2006-03-14 16:24:38 +010048
Joe Hershberger32795ec2011-10-11 23:57:14 -050049#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
51#define CONFIG_SYS_MEMTEST_END 0x00100000
Marian Balakowicz991425f2006-03-14 16:24:38 +010052
53/*
54 * DDR Setup
55 */
Xie Xiaobo8d172c02007-02-14 18:26:44 +080056#define CONFIG_DDR_ECC /* support DDR ECC function */
Marian Balakowiczd326f4a2006-03-16 15:19:35 +010057#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
Marian Balakowicz991425f2006-03-14 16:24:38 +010058#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
59
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010060/*
York Sund26e34c2016-12-28 08:43:40 -080061 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
62 * unselect it to use old spd_sdram.c
York Sund4b91062011-08-26 11:32:45 -070063 */
York Sund4b91062011-08-26 11:32:45 -070064#define CONFIG_SYS_SPD_BUS_NUM 0
65#define SPD_EEPROM_ADDRESS1 0x52
66#define SPD_EEPROM_ADDRESS2 0x51
York Sund4b91062011-08-26 11:32:45 -070067#define CONFIG_DIMM_SLOTS_PER_CTLR 2
68#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
69#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
70#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
York Sund4b91062011-08-26 11:32:45 -070071
72/*
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010073 * 32-bit data path mode.
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020074 *
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010075 * Please note that using this mode for devices with the real density of 64-bit
76 * effectively reduces the amount of available memory due to the effect of
77 * wrapping around while translating address to row/columns, for example in the
78 * 256MB module the upper 128MB get aliased with contents of the lower
79 * 128MB); normally this define should be used for devices with real 32-bit
Wolfgang Denkcf48eb92006-04-16 10:51:58 +020080 * data path.
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010081 */
82#undef CONFIG_DDR_32BIT
83
Joe Hershberger32795ec2011-10-11 23:57:14 -050084#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
85#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershberger32795ec2011-10-11 23:57:14 -050087#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
88 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Marian Balakowicz991425f2006-03-14 16:24:38 +010089#undef CONFIG_DDR_2T_TIMING
90
Xie Xiaobo8d172c02007-02-14 18:26:44 +080091/*
92 * DDRCDR - DDR Control Driver Register
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
Xie Xiaobo8d172c02007-02-14 18:26:44 +080095
Marian Balakowicz991425f2006-03-14 16:24:38 +010096#if defined(CONFIG_SPD_EEPROM)
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010097/*
98 * Determine DDR configuration from I2C interface.
99 */
100#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100101#else
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100102/*
103 * Manually set up DDR parameters
104 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800106#if defined(CONFIG_DDR_II)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_DDRCDR 0x80080001
Joe Hershberger32795ec2011-10-11 23:57:14 -0500108#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
Joe Hershberger32795ec2011-10-11 23:57:14 -0500110#define CONFIG_SYS_DDR_TIMING_0 0x00220802
111#define CONFIG_SYS_DDR_TIMING_1 0x38357322
112#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
113#define CONFIG_SYS_DDR_TIMING_3 0x00000000
114#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_DDR_MODE 0x47d00432
116#define CONFIG_SYS_DDR_MODE2 0x8000c000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500117#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
119#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800120#else
Joe Hershberger2e651b22011-10-11 23:57:31 -0500121#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500122 | CSCONFIG_ROW_BIT_13 \
123 | CSCONFIG_COL_BIT_10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_DDR_TIMING_1 0x36332321
125#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500126#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100128
129#if defined(CONFIG_DDR_32BIT)
130/* set burst length to 8 for 32-bit data path */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500131 /* DLL,normal,seq,4/2.5, 8 burst len */
132#define CONFIG_SYS_DDR_MODE 0x00000023
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100133#else
134/* the default burst length is 4 - for 64-bit data path */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500135 /* DLL,normal,seq,4/2.5, 4 burst len */
136#define CONFIG_SYS_DDR_MODE 0x00000022
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100137#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100138#endif
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800139#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100140
141/*
142 * SDRAM on the Local Bus
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
145#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100146
147/*
148 * FLASH on the Local Bus
149 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500150#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
151#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500153#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
154#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100156
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500157#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
158 | BR_PS_16 /* 16 bit port */ \
159 | BR_MS_GPCM /* MSEL = GPCM */ \
160 | BR_V) /* valid */
161#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500162 | OR_UPM_XAM \
163 | OR_GPCM_CSNT \
164 | OR_GPCM_ACS_DIV2 \
165 | OR_GPCM_XACS \
166 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500167 | OR_GPCM_TRLX_SET \
168 | OR_GPCM_EHTR_SET \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500169 | OR_GPCM_EAD)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500170
Joe Hershberger32795ec2011-10-11 23:57:14 -0500171 /* window base at flash base */
172#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500173#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100174
Joe Hershberger32795ec2011-10-11 23:57:14 -0500175#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
176#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#undef CONFIG_SYS_FLASH_CHECKSUM
179#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100181
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200182#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
185#define CONFIG_SYS_RAMBOOT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100186#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#undef CONFIG_SYS_RAMBOOT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100188#endif
189
190/*
191 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
192 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500193#define CONFIG_SYS_BCSR 0xE2400000
194 /* Access window base at BCSR base */
195#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500196#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
197#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
198 | BR_PS_8 \
199 | BR_MS_GPCM \
200 | BR_V)
201 /* 0x00000801 */
202#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
203 | OR_GPCM_XAM \
204 | OR_GPCM_CSNT \
205 | OR_GPCM_SCY_15 \
206 | OR_GPCM_TRLX_CLEAR \
207 | OR_GPCM_EHTR_CLEAR)
208 /* 0xFFFFE8F0 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger32795ec2011-10-11 23:57:14 -0500211#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
212#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Marian Balakowicz991425f2006-03-14 16:24:38 +0100213
Joe Hershberger32795ec2011-10-11 23:57:14 -0500214#define CONFIG_SYS_GBL_DATA_OFFSET \
215 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Marian Balakowicz991425f2006-03-14 16:24:38 +0100217
Kevin Hao16c8c172016-07-08 11:25:14 +0800218#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500219#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100220
221/*
222 * Local Bus LCRR and LBCR regs
223 * LCRR: DLL bypass, Clock divider is 4
224 * External Local Bus rate is
225 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
226 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500227#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
228#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_LBC_LBCR 0x00000000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100230
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800231/*
232 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
Xie Xiaobo8d172c02007-02-14 18:26:44 +0800234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#undef CONFIG_SYS_LB_SDRAM
Marian Balakowicz991425f2006-03-14 16:24:38 +0100236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#ifdef CONFIG_SYS_LB_SDRAM
Marian Balakowicz991425f2006-03-14 16:24:38 +0100238/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
239/*
240 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Marian Balakowicz991425f2006-03-14 16:24:38 +0100242 *
243 * For BR2, need:
244 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
245 * port-size = 32-bits = BR2[19:20] = 11
246 * no parity checking = BR2[21:22] = 00
247 * SDRAM for MSEL = BR2[24:26] = 011
248 * Valid = BR[31] = 1
249 *
250 * 0 4 8 12 16 20 24 28
251 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
Marian Balakowicz991425f2006-03-14 16:24:38 +0100252 */
253
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500254#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
255 | BR_PS_32 /* 32-bit port */ \
256 | BR_MS_SDRAM /* MSEL = SDRAM */ \
257 | BR_V) /* Valid */
258 /* 0xF0001861 */
259#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
260#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100261
262/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Marian Balakowicz991425f2006-03-14 16:24:38 +0100264 *
265 * For OR2, need:
266 * 64MB mask for AM, OR2[0:7] = 1111 1100
267 * XAM, OR2[17:18] = 11
268 * 9 columns OR2[19-21] = 010
269 * 13 rows OR2[23-25] = 100
270 * EAD set for extra time OR[31] = 1
271 *
272 * 0 4 8 12 16 20 24 28
273 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
274 */
275
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500276#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
277 | OR_SDRAM_XAM \
278 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
279 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
280 | OR_SDRAM_EAD)
281 /* 0xFC006901 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100282
Joe Hershberger32795ec2011-10-11 23:57:14 -0500283 /* LB sdram refresh timer, about 6us */
284#define CONFIG_SYS_LBC_LSRT 0x32000000
285 /* LB refresh timer prescal, 266MHz/32 */
286#define CONFIG_SYS_LBC_MRTPR 0x20000000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100287
Joe Hershberger32795ec2011-10-11 23:57:14 -0500288#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
Kumar Gala540dcf12009-03-26 01:34:39 -0500289 | LSDMR_BSMA1516 \
290 | LSDMR_RFCR8 \
291 | LSDMR_PRETOACT6 \
292 | LSDMR_ACTTORW3 \
293 | LSDMR_BL8 \
294 | LSDMR_WRC3 \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500295 | LSDMR_CL3)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100296
297/*
298 * SDRAM Controller configuration sequence.
299 */
Kumar Gala540dcf12009-03-26 01:34:39 -0500300#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
301#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
302#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
303#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
304#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100305#endif
306
307/*
308 * Serial Port
309 */
310#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_NS16550_SERIAL
312#define CONFIG_SYS_NS16550_REG_SIZE 1
313#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500316 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Marian Balakowicz991425f2006-03-14 16:24:38 +0100317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
319#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100320
Kim Phillips22d71a72007-02-27 18:41:08 -0600321#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500322#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100323
324/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200325#define CONFIG_SYS_I2C
326#define CONFIG_SYS_I2C_FSL
327#define CONFIG_SYS_FSL_I2C_SPEED 400000
328#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
329#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
330#define CONFIG_SYS_FSL_I2C2_SPEED 400000
331#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
332#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
333#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Marian Balakowicz991425f2006-03-14 16:24:38 +0100334
Ben Warren80ddd222008-01-16 22:37:42 -0500335/* SPI */
Ben Warren8931ab12008-01-26 23:41:19 -0500336#define CONFIG_MPC8XXX_SPI
Ben Warren80ddd222008-01-16 22:37:42 -0500337#undef CONFIG_SOFT_SPI /* SPI bit-banged */
Ben Warren80ddd222008-01-16 22:37:42 -0500338
339/* GPIOs. Used as SPI chip selects */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_GPIO1_PRELIM
341#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
342#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
Ben Warren80ddd222008-01-16 22:37:42 -0500343
Marian Balakowicz991425f2006-03-14 16:24:38 +0100344/* TSEC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500346#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500348#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100349
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500350/* USB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100352
353/*
354 * General PCI
355 * Addresses are mapped 1-1.
356 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
358#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
359#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
360#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
361#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
362#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500363#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
364#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
365#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100366
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
368#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
369#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
370#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
371#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
372#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500373#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
374#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
375#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100376
377#if defined(CONFIG_PCI)
378
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500379#define PCI_ONE_PCI1
Marian Balakowicz991425f2006-03-14 16:24:38 +0100380#if defined(PCI_64BIT)
381#undef PCI_ALL_PCI1
382#undef PCI_TWO_PCI1
383#undef PCI_ONE_PCI1
384#endif
385
Ira W. Snyder162338e2008-08-22 11:00:13 -0700386#define CONFIG_83XX_PCI_STREAMING
Marian Balakowicz991425f2006-03-14 16:24:38 +0100387
388#undef CONFIG_EEPRO100
389#undef CONFIG_TULIP
390
391#if !defined(CONFIG_PCI_PNP)
392 #define PCI_ENET0_IOADDR 0xFIXME
393 #define PCI_ENET0_MEMADDR 0xFIXME
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200394 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100395#endif
396
397#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100399
400#endif /* CONFIG_PCI */
401
402/*
403 * TSEC configuration
404 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500405#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100406
407#if defined(CONFIG_TSEC_ENET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100408
409#define CONFIG_GMII 1 /* MII PHY management */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500410#define CONFIG_TSEC1 1
Kim Phillips255a35772007-05-16 16:52:19 -0500411#define CONFIG_TSEC1_NAME "TSEC0"
Joe Hershberger32795ec2011-10-11 23:57:14 -0500412#define CONFIG_TSEC2 1
Kim Phillips255a35772007-05-16 16:52:19 -0500413#define CONFIG_TSEC2_NAME "TSEC1"
Marian Balakowicz991425f2006-03-14 16:24:38 +0100414#define TSEC1_PHY_ADDR 0
415#define TSEC2_PHY_ADDR 1
416#define TSEC1_PHYIDX 0
417#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500418#define TSEC1_FLAGS TSEC_GIGABIT
419#define TSEC2_FLAGS TSEC_GIGABIT
Marian Balakowicz991425f2006-03-14 16:24:38 +0100420
421/* Options are: TSEC[0-1] */
422#define CONFIG_ETHPRIME "TSEC0"
423
424#endif /* CONFIG_TSEC_ENET */
425
426/*
427 * Configure on-board RTC
428 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500429#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
430#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100431
432/*
433 * Environment
434 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#ifndef CONFIG_SYS_RAMBOOT
Joe Hershberger32795ec2011-10-11 23:57:14 -0500436 #define CONFIG_ENV_ADDR \
437 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200438 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
439 #define CONFIG_ENV_SIZE 0x2000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100440
441/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200442#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
443#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100444
445#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200447 #define CONFIG_ENV_SIZE 0x2000
Marian Balakowicz991425f2006-03-14 16:24:38 +0100448#endif
449
450#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100452
Jon Loeliger8ea54992007-07-04 22:30:06 -0500453/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500454 * BOOTP options
455 */
456#define CONFIG_BOOTP_BOOTFILESIZE
457#define CONFIG_BOOTP_BOOTPATH
458#define CONFIG_BOOTP_GATEWAY
459#define CONFIG_BOOTP_HOSTNAME
460
Jon Loeliger659e2f62007-07-10 09:10:49 -0500461/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500462 * Command line configuration.
463 */
Jon Loeliger8ea54992007-07-04 22:30:06 -0500464
Marian Balakowicz991425f2006-03-14 16:24:38 +0100465#undef CONFIG_WATCHDOG /* watchdog disabled */
466
467/*
468 * Miscellaneous configurable options
469 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_LONGHELP /* undef to save memory */
471#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100472
Marian Balakowicz991425f2006-03-14 16:24:38 +0100473/*
474 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700475 * have to be in the first 256 MB of memory, since this is
Marian Balakowicz991425f2006-03-14 16:24:38 +0100476 * the maximum mapped by the Linux kernel during initialization.
477 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500478 /* Initial Memory map for Linux*/
479#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kevin Hao63865272016-07-08 11:25:15 +0800480#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100481
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100483
484#if 1 /*528/264*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100486 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
487 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500488 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100489 HRCWL_VCO_1X2 |\
490 HRCWL_CORE_TO_CSB_2X1)
491#elif 0 /*396/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100493 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
494 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500495 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100496 HRCWL_VCO_1X4 |\
497 HRCWL_CORE_TO_CSB_3X1)
498#elif 0 /*264/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100500 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
501 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500502 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100503 HRCWL_VCO_1X4 |\
504 HRCWL_CORE_TO_CSB_2X1)
505#elif 0 /*132/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100507 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
508 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500509 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100510 HRCWL_VCO_1X4 |\
511 HRCWL_CORE_TO_CSB_1X1)
512#elif 0 /*264/264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100514 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
515 HRCWL_DDR_TO_SCB_CLK_1X1 |\
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500516 HRCWL_CSB_TO_CLKIN |\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100517 HRCWL_VCO_1X4 |\
518 HRCWL_CORE_TO_CSB_1X1)
519#endif
520
Ira W. Snyder447ad572008-08-22 11:00:15 -0700521#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200522#define CONFIG_SYS_HRCW_HIGH (\
Ira W. Snyder447ad572008-08-22 11:00:15 -0700523 HRCWH_PCI_AGENT |\
524 HRCWH_64_BIT_PCI |\
525 HRCWH_PCI1_ARBITER_DISABLE |\
526 HRCWH_PCI2_ARBITER_DISABLE |\
527 HRCWH_CORE_ENABLE |\
528 HRCWH_FROM_0X00000100 |\
529 HRCWH_BOOTSEQ_DISABLE |\
530 HRCWH_SW_WATCHDOG_DISABLE |\
531 HRCWH_ROM_LOC_LOCAL_16BIT |\
532 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500533 HRCWH_TSEC2M_IN_GMII)
Ira W. Snyder447ad572008-08-22 11:00:15 -0700534#else
Marian Balakowicz991425f2006-03-14 16:24:38 +0100535#if defined(PCI_64BIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200536#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100537 HRCWH_PCI_HOST |\
538 HRCWH_64_BIT_PCI |\
539 HRCWH_PCI1_ARBITER_ENABLE |\
540 HRCWH_PCI2_ARBITER_DISABLE |\
541 HRCWH_CORE_ENABLE |\
542 HRCWH_FROM_0X00000100 |\
543 HRCWH_BOOTSEQ_DISABLE |\
544 HRCWH_SW_WATCHDOG_DISABLE |\
545 HRCWH_ROM_LOC_LOCAL_16BIT |\
546 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500547 HRCWH_TSEC2M_IN_GMII)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100548#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200549#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100550 HRCWH_PCI_HOST |\
551 HRCWH_32_BIT_PCI |\
552 HRCWH_PCI1_ARBITER_ENABLE |\
553 HRCWH_PCI2_ARBITER_ENABLE |\
554 HRCWH_CORE_ENABLE |\
555 HRCWH_FROM_0X00000100 |\
556 HRCWH_BOOTSEQ_DISABLE |\
557 HRCWH_SW_WATCHDOG_DISABLE |\
558 HRCWH_ROM_LOC_LOCAL_16BIT |\
559 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500560 HRCWH_TSEC2M_IN_GMII)
Ira W. Snyder447ad572008-08-22 11:00:15 -0700561#endif /* PCI_64BIT */
562#endif /* CONFIG_PCISLAVE */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100563
Lee Nippera5fe5142008-04-25 15:44:45 -0500564/*
565 * System performance
566 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500568#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200569#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
570#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
571#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
572#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Lee Nippera5fe5142008-04-25 15:44:45 -0500573
Marian Balakowicz991425f2006-03-14 16:24:38 +0100574/* System IO Config */
Kim Phillips3c9b1ee2009-06-05 14:11:33 -0500575#define CONFIG_SYS_SICRH 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200576#define CONFIG_SYS_SICRL SICRL_LDP_A
Marian Balakowicz991425f2006-03-14 16:24:38 +0100577
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_HID0_INIT 0x000000000
Joe Hershberger32795ec2011-10-11 23:57:14 -0500579#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
580 | HID0_ENABLE_INSTRUCTION_CACHE)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100581
Joe Hershberger32795ec2011-10-11 23:57:14 -0500582/* #define CONFIG_SYS_HID0_FINAL (\
Marian Balakowicz991425f2006-03-14 16:24:38 +0100583 HID0_ENABLE_INSTRUCTION_CACHE |\
584 HID0_ENABLE_M_BIT |\
Joe Hershberger32795ec2011-10-11 23:57:14 -0500585 HID0_ENABLE_ADDRESS_BROADCAST) */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100586
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200587#define CONFIG_SYS_HID2 HID2_HBE
Becky Bruce31d82672008-05-08 19:02:12 -0500588#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100589
590/* DDR @ 0x00000000 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500591#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500592 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500593 | BATL_MEMCOHERENCE)
594#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
595 | BATU_BL_256M \
596 | BATU_VS \
597 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100598
599/* PCI @ 0x80000000 */
600#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000601#define CONFIG_PCI_INDIRECT_BRIDGE
Joe Hershberger32795ec2011-10-11 23:57:14 -0500602#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500603 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500604 | BATL_MEMCOHERENCE)
605#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
606 | BATU_BL_256M \
607 | BATU_VS \
608 | BATU_VP)
609#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500610 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500611 | BATL_CACHEINHIBIT \
612 | BATL_GUARDEDSTORAGE)
613#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
614 | BATU_BL_256M \
615 | BATU_VS \
616 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100617#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618#define CONFIG_SYS_IBAT1L (0)
619#define CONFIG_SYS_IBAT1U (0)
620#define CONFIG_SYS_IBAT2L (0)
621#define CONFIG_SYS_IBAT2U (0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100622#endif
623
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500624#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger32795ec2011-10-11 23:57:14 -0500625#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500626 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500627 | BATL_MEMCOHERENCE)
628#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
629 | BATU_BL_256M \
630 | BATU_VS \
631 | BATU_VP)
632#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500633 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500634 | BATL_CACHEINHIBIT \
635 | BATL_GUARDEDSTORAGE)
636#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
637 | BATU_BL_256M \
638 | BATU_VS \
639 | BATU_VP)
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500640#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200641#define CONFIG_SYS_IBAT3L (0)
642#define CONFIG_SYS_IBAT3U (0)
643#define CONFIG_SYS_IBAT4L (0)
644#define CONFIG_SYS_IBAT4U (0)
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500645#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100646
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500647/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500648#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500649 | BATL_PP_RW \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500650 | BATL_CACHEINHIBIT \
651 | BATL_GUARDEDSTORAGE)
652#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
653 | BATU_BL_256M \
654 | BATU_VS \
655 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100656
Kumar Gala8fe9bf62006-04-20 13:45:32 -0500657/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger32795ec2011-10-11 23:57:14 -0500658#define CONFIG_SYS_IBAT6L (0xF0000000 \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500659 | BATL_PP_RW \
660 | BATL_MEMCOHERENCE \
661 | BATL_GUARDEDSTORAGE)
Joe Hershberger32795ec2011-10-11 23:57:14 -0500662#define CONFIG_SYS_IBAT6U (0xF0000000 \
663 | BATU_BL_256M \
664 | BATU_VS \
665 | BATU_VP)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100666
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200667#define CONFIG_SYS_IBAT7L (0)
668#define CONFIG_SYS_IBAT7U (0)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100669
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200670#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
671#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
672#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
673#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
674#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
675#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
676#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
677#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
678#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
679#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
680#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
681#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
682#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
683#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
684#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
685#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Marian Balakowicz991425f2006-03-14 16:24:38 +0100686
Jon Loeliger8ea54992007-07-04 22:30:06 -0500687#if defined(CONFIG_CMD_KGDB)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100688#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100689#endif
690
691/*
692 * Environment Configuration
693 */
694#define CONFIG_ENV_OVERWRITE
695
696#if defined(CONFIG_TSEC_ENET)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100697#define CONFIG_HAS_ETH1
Andy Fleming10327dc2007-08-16 16:35:02 -0500698#define CONFIG_HAS_ETH0
Marian Balakowicz991425f2006-03-14 16:24:38 +0100699#endif
700
Marian Balakowicz991425f2006-03-14 16:24:38 +0100701#define CONFIG_HOSTNAME mpc8349emds
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000702#define CONFIG_ROOTPATH "/nfsroot/rootfs"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000703#define CONFIG_BOOTFILE "uImage"
Marian Balakowicz991425f2006-03-14 16:24:38 +0100704
Joe Hershberger32795ec2011-10-11 23:57:14 -0500705#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100706
Marian Balakowicz991425f2006-03-14 16:24:38 +0100707#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100708 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100709 "echo"
710
711#define CONFIG_EXTRA_ENV_SETTINGS \
712 "netdev=eth0\0" \
713 "hostname=mpc8349emds\0" \
714 "nfsargs=setenv bootargs root=/dev/nfs rw " \
715 "nfsroot=${serverip}:${rootpath}\0" \
716 "ramargs=setenv bootargs root=/dev/ram rw\0" \
717 "addip=setenv bootargs ${bootargs} " \
718 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
719 ":${hostname}:${netdev}:off panic=1\0" \
720 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
721 "flash_nfs=run nfsargs addip addtty;" \
722 "bootm ${kernel_addr}\0" \
723 "flash_self=run ramargs addip addtty;" \
724 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
725 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
726 "bootm\0" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100727 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
728 "update=protect off fe000000 fe03ffff; " \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500729 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100730 "upd=run load update\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500731 "fdtaddr=780000\0" \
Kim Phillipscc861f72009-08-26 21:25:46 -0500732 "fdtfile=mpc834x_mds.dtb\0" \
Marian Balakowicz991425f2006-03-14 16:24:38 +0100733 ""
734
Joe Hershberger32795ec2011-10-11 23:57:14 -0500735#define CONFIG_NFSBOOTCOMMAND \
736 "setenv bootargs root=/dev/nfs rw " \
737 "nfsroot=$serverip:$rootpath " \
738 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
739 "$netdev:off " \
740 "console=$consoledev,$baudrate $othbootargs;" \
741 "tftp $loadaddr $bootfile;" \
742 "tftp $fdtaddr $fdtfile;" \
743 "bootm $loadaddr - $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600744
745#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger32795ec2011-10-11 23:57:14 -0500746 "setenv bootargs root=/dev/ram rw " \
747 "console=$consoledev,$baudrate $othbootargs;" \
748 "tftp $ramdiskaddr $ramdiskfile;" \
749 "tftp $loadaddr $bootfile;" \
750 "tftp $fdtaddr $fdtfile;" \
751 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600752
Marian Balakowicz991425f2006-03-14 16:24:38 +0100753#define CONFIG_BOOTCOMMAND "run flash_self"
754
755#endif /* __CONFIG_H */