| Prabhakar Kushwaha | 3b6e389 | 2016-06-03 18:41:35 +0530 | [diff] [blame] | 1 | Overview |
| 2 | -------- |
| 3 | QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance |
| 4 | development platform, with a complete debugging environment. |
| 5 | The LS1012ARDB board supports the QorIQ LS1012A processor and is |
| 6 | optimized to support the high-bandwidth DDR3L memory and |
| 7 | a full complement of high-speed SerDes ports. |
| 8 | |
| 9 | LS1012A SoC Overview |
| 10 | -------------------- |
| 11 | Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A |
| 12 | SoC overview. |
| 13 | |
| 14 | LS1012ARDB board Overview |
| 15 | ----------------------- |
| 16 | - SERDES Connections, 4 lanes supporting: |
| 17 | - PCI Express - 3.0 |
| 18 | - SGMII, SGMII 2.5 |
| 19 | - SATA 3.0 |
| 20 | - DDR Controller |
| 21 | - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s |
| 22 | -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select |
| 23 | signals to |
| 24 | - QSPI NOR flash memory (2 virtual banks) |
| 25 | - the QSPI emulator.s |
| 26 | - USB 3.0 |
| 27 | - one high-speed USB 2.0/3.0 port. |
| 28 | - Two enhanced secure digital host controllers: |
| 29 | - SDHC1 controller can be connected to onboard SDHC connector |
| 30 | - SDHC2 controller: Three dual 1:4 mux/demux devices, |
| 31 | 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC, |
| 32 | SDIO WiFi, SPI, and Ardiuno shield |
| 33 | - 2 I2C controllers |
| 34 | - One SATA onboard connectors |
| 35 | - UART |
| 36 | - The LS1012A processor consists of two UART controllers, |
| 37 | out of which only UART1 is used on RDB. |
| 38 | - ARM JTAG support |
| 39 | |
| 40 | Booting Options |
| 41 | --------------- |
| 42 | a) QSPI Flash Emu Boot |
| 43 | b) QSPI Flash 1 |
| 44 | c) QSPI Flash 2 |
| 45 | |
| 46 | QSPI flash map |
| 47 | -------------- |
| 48 | Images | Size |QSPI Flash Address |
| 49 | ------------------------------------------ |
| 50 | RCW + PBI | 1MB | 0x4000_0000 |
| 51 | U-boot | 1MB | 0x4010_0000 |
| 52 | U-boot Env | 1MB | 0x4020_0000 |
| 53 | PPA FIT image | 2MB | 0x4050_0000 |
| 54 | Linux ITB | ~53MB | 0x40A0_0000 |
| Bhaskar Upadhaya | b0ce187 | 2018-01-11 20:03:31 +0530 | [diff] [blame^] | 55 | |
| 56 | LS1012A2G5RDB board Overview |
| 57 | ----------------------- |
| 58 | - SERDES Connections, 3 lanes supporting: |
| 59 | - SGMII, SGMII 2.5 |
| 60 | - SATA 3.0 |
| 61 | - DDR Controller |
| 62 | - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s |
| 63 | -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select |
| 64 | signals to |
| 65 | - QSPI NOR flash memory |
| 66 | - USB 3.0 |
| 67 | - one high-speed USB 2.0/3.0 port. |
| 68 | - SDIO WiFi, SPI |
| 69 | - 2 I2C controllers |
| 70 | - One SATA onboard connectors |
| 71 | - UART |
| 72 | - The LS1012A processor consists of two UART controllers, |
| 73 | out of which only UART1 is used on 2G5RDB. |
| 74 | - ARM JTAG support |
| 75 | |
| 76 | Major Difference between LS1012ARDB and LS1012A-2G5RDB |
| 77 | ------------------------------------------------------ |
| 78 | 1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB |
| 79 | 2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs |
| 80 | of LS1012ARDB |
| 81 | 3. LS1012A-2G5RDB is not having Arduino header |
| 82 | 4. LS1012A-2G5RDB doesn't have PCI slot |
| 83 | |
| 84 | Booting Options |
| 85 | --------------- |
| 86 | QSPI Flash |
| 87 | |
| 88 | QSPI flash map |
| 89 | -------------- |
| 90 | Images | Size |QSPI Flash Address |
| 91 | ------------------------------------------ |
| 92 | RCW + PBI | 1MB | 0x4000_0000 |
| 93 | U-boot | 1MB | 0x4010_0000 |
| 94 | U-boot Env | 1MB | 0x4030_0000 |
| 95 | PPA FIT image | 2MB | 0x4040_0000 |
| 96 | PFE firmware | 20K | 0x00a0_0000 |
| 97 | Linux ITB | ~53MB | 0x4100_0000 |