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Bill Richardson55ae10f2012-10-20 11:44:34 +00001/*
2 * Copyright (c) 2012 The Chromium OS Authors.
Wolfgang Denk1a459662013-07-08 09:37:19 +02003 * SPDX-License-Identifier: GPL-2.0+
Bill Richardson55ae10f2012-10-20 11:44:34 +00004 */
5
6/*
7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8 * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9 * consisting of a standard header and a device-specific set of registers. PCI
10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11 * other things). Within the PCI configuration space, the GPIOBASE register
12 * tells us where in the device's I/O region we can find more registers to
13 * actually access the GPIOs.
14 *
15 * PCI bus/device/function 0:1f:0 => PCI config registers
16 * PCI config register "GPIOBASE"
17 * PCI I/O space + [GPIOBASE] => start of GPIO registers
18 * GPIO registers => gpio pin function, direction, value
Bill Richardson57be9172012-10-20 11:44:36 +000019 *
20 *
21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22 * ICH versions have more, but the decoding the matrix that describes them is
23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24 * but they will ONLY work for certain unspecified chipsets because the offset
25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26 * reserved or subject to arcane restrictions.
Bill Richardson55ae10f2012-10-20 11:44:34 +000027 */
28
29#include <common.h>
Simon Glass74141122014-10-10 07:49:18 -060030#include <dm.h>
31#include <errno.h>
32#include <fdtdec.h>
Bin Meng3ddc1c72016-02-01 01:40:47 -080033#include <pch.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000034#include <pci.h>
Simon Glass15cf75e2016-03-11 22:07:14 -070035#include <asm/cpu.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000036#include <asm/gpio.h>
37#include <asm/io.h>
Simon Glass1b4f25f2014-11-12 22:42:24 -070038#include <asm/pci.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000039
Simon Glass8b097912015-07-31 09:31:31 -060040DECLARE_GLOBAL_DATA_PTR;
41
Simon Glass74141122014-10-10 07:49:18 -060042#define GPIO_PER_BANK 32
43
Simon Glass74141122014-10-10 07:49:18 -060044struct ich6_bank_priv {
45 /* These are I/O addresses */
Bin Mengb71eec32014-12-17 15:50:38 +080046 uint16_t use_sel;
47 uint16_t io_sel;
48 uint16_t lvl;
Bill Richardson57be9172012-10-20 11:44:36 +000049};
Bill Richardson55ae10f2012-10-20 11:44:34 +000050
Gabriel Huau5318f182015-05-25 22:27:37 -070051#define GPIO_USESEL_OFFSET(x) (x)
52#define GPIO_IOSEL_OFFSET(x) (x + 4)
53#define GPIO_LVL_OFFSET(x) (x + 8)
54
Gabriel Huau5318f182015-05-25 22:27:37 -070055static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
56{
57 u32 val;
58
59 val = inl(base);
60 if (value)
61 val |= (1UL << offset);
62 else
63 val &= ~(1UL << offset);
64 outl(val, base);
65
66 return 0;
67}
68
Gabriel Huau5318f182015-05-25 22:27:37 -070069static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
70{
71 u32 val;
72
73 if (!dir) {
74 val = inl(base);
75 val |= (1UL << offset);
76 outl(val, base);
77 } else {
78 val = inl(base);
79 val &= ~(1UL << offset);
80 outl(val, base);
81 }
82
83 return 0;
84}
85
Gabriel Huau5318f182015-05-25 22:27:37 -070086static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
87{
88 struct ich6_bank_platdata *plat = dev_get_platdata(dev);
Bin Meng3ddc1c72016-02-01 01:40:47 -080089 u32 gpiobase;
Gabriel Huau5318f182015-05-25 22:27:37 -070090 int offset;
Bin Meng3ddc1c72016-02-01 01:40:47 -080091 int ret;
Gabriel Huau5318f182015-05-25 22:27:37 -070092
Bin Meng3ddc1c72016-02-01 01:40:47 -080093 ret = pch_get_gpio_base(dev->parent, &gpiobase);
94 if (ret)
95 return ret;
96
Simon Glass74141122014-10-10 07:49:18 -060097 offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
98 if (offset == -1) {
99 debug("%s: Invalid register offset %d\n", __func__, offset);
100 return -EINVAL;
101 }
Simon Glassd6d50db2016-03-06 19:28:13 -0700102 plat->offset = offset;
Simon Glass74141122014-10-10 07:49:18 -0600103 plat->base_addr = gpiobase + offset;
104 plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
105 "bank-name", NULL);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000106
Bill Richardson55ae10f2012-10-20 11:44:34 +0000107 return 0;
108}
109
Simon Glass1b4f25f2014-11-12 22:42:24 -0700110static int ich6_gpio_probe(struct udevice *dev)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000111{
Simon Glass74141122014-10-10 07:49:18 -0600112 struct ich6_bank_platdata *plat = dev_get_platdata(dev);
Simon Glasse564f052015-03-05 12:25:20 -0700113 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass74141122014-10-10 07:49:18 -0600114 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bin Meng27955732014-12-12 21:05:23 +0800115
Simon Glass74141122014-10-10 07:49:18 -0600116 uc_priv->gpio_count = GPIO_PER_BANK;
117 uc_priv->bank_name = plat->bank_name;
118 bank->use_sel = plat->base_addr;
119 bank->io_sel = plat->base_addr + 4;
120 bank->lvl = plat->base_addr + 8;
121
122 return 0;
123}
124
Simon Glass1b4f25f2014-11-12 22:42:24 -0700125static int ich6_gpio_request(struct udevice *dev, unsigned offset,
126 const char *label)
Simon Glass74141122014-10-10 07:49:18 -0600127{
128 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000129 u32 tmplong;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000130
131 /*
132 * Make sure that the GPIO pin we want isn't already in use for some
133 * built-in hardware function. We have to check this for every
134 * requested pin.
135 */
Simon Glass74141122014-10-10 07:49:18 -0600136 tmplong = inl(bank->use_sel);
137 if (!(tmplong & (1UL << offset))) {
Bill Richardson57be9172012-10-20 11:44:36 +0000138 debug("%s: gpio %d is reserved for internal use\n", __func__,
Simon Glass74141122014-10-10 07:49:18 -0600139 offset);
140 return -EPERM;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000141 }
142
Bill Richardson55ae10f2012-10-20 11:44:34 +0000143 return 0;
144}
145
Simon Glass74141122014-10-10 07:49:18 -0600146static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000147{
Simon Glass74141122014-10-10 07:49:18 -0600148 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson57be9172012-10-20 11:44:36 +0000149
Simon Glasse7cc0b62015-08-22 15:58:58 -0600150 return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000151}
152
Simon Glass74141122014-10-10 07:49:18 -0600153static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
154 int value)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000155{
Gabriel Huau5318f182015-05-25 22:27:37 -0700156 int ret;
Simon Glass74141122014-10-10 07:49:18 -0600157 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000158
Simon Glasse7cc0b62015-08-22 15:58:58 -0600159 ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
Gabriel Huau5318f182015-05-25 22:27:37 -0700160 if (ret)
161 return ret;
Axel Lin0a547452014-12-07 12:48:27 +0800162
Gabriel Huau5318f182015-05-25 22:27:37 -0700163 return _ich6_gpio_set_value(bank->lvl, offset, value);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000164}
165
Simon Glass74141122014-10-10 07:49:18 -0600166static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000167{
Simon Glass74141122014-10-10 07:49:18 -0600168 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000169 u32 tmplong;
Bill Richardson57be9172012-10-20 11:44:36 +0000170 int r;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000171
Simon Glass74141122014-10-10 07:49:18 -0600172 tmplong = inl(bank->lvl);
173 r = (tmplong & (1UL << offset)) ? 1 : 0;
Bill Richardson57be9172012-10-20 11:44:36 +0000174 return r;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000175}
176
Simon Glass74141122014-10-10 07:49:18 -0600177static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
178 int value)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000179{
Simon Glass74141122014-10-10 07:49:18 -0600180 struct ich6_bank_priv *bank = dev_get_priv(dev);
Gabriel Huau5318f182015-05-25 22:27:37 -0700181 return _ich6_gpio_set_value(bank->lvl, offset, value);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000182}
Simon Glass74141122014-10-10 07:49:18 -0600183
184static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
185{
186 struct ich6_bank_priv *bank = dev_get_priv(dev);
187 u32 mask = 1UL << offset;
188
189 if (!(inl(bank->use_sel) & mask))
190 return GPIOF_FUNC;
191 if (inl(bank->io_sel) & mask)
192 return GPIOF_INPUT;
193 else
194 return GPIOF_OUTPUT;
195}
196
197static const struct dm_gpio_ops gpio_ich6_ops = {
198 .request = ich6_gpio_request,
199 .direction_input = ich6_gpio_direction_input,
200 .direction_output = ich6_gpio_direction_output,
201 .get_value = ich6_gpio_get_value,
202 .set_value = ich6_gpio_set_value,
203 .get_function = ich6_gpio_get_function,
204};
205
206static const struct udevice_id intel_ich6_gpio_ids[] = {
207 { .compatible = "intel,ich6-gpio" },
208 { }
209};
210
211U_BOOT_DRIVER(gpio_ich6) = {
212 .name = "gpio_ich6",
213 .id = UCLASS_GPIO,
214 .of_match = intel_ich6_gpio_ids,
215 .ops = &gpio_ich6_ops,
216 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
217 .probe = ich6_gpio_probe,
218 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
219 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
220};