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wdenk3a473b22004-01-03 00:43:19 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#include <asm/processor.h>
32
33/* This define must be before the core.h include */
34#define CONFIG_DB64460 1 /* this is an DB64460 board */
35
36#ifndef __ASSEMBLY__
37#include "../board/Marvell/include/core.h"
38#endif
39
40/*-----------------------------------------------------*/
41/* #include "../board/db64460/local.h" */
42#ifndef __LOCAL_H
43#define __LOCAL_H
44
45#define CONFIG_ETHADDR 64:46:00:00:00:01
wdenke2ffd592004-12-31 09:32:47 +000046#define CONFIG_HAS_ETH1
wdenk3a473b22004-01-03 00:43:19 +000047#define CONFIG_ETH1ADDR 64:46:00:00:00:02
wdenke2ffd592004-12-31 09:32:47 +000048#define CONFIG_HAS_ETH2
wdenk3a473b22004-01-03 00:43:19 +000049#define CONFIG_ETH2ADDR 64:46:00:00:00:03
50
51#define CONFIG_ENV_OVERWRITE
52#endif /* __CONFIG_H */
53
54/*
55 * High Level Configuration Options
56 * (easy to change)
57 */
58
59#define CONFIG_74xx /* we have a 750FX (override local.h) */
60
61#define CONFIG_DB64460 1 /* this is an DB64460 board */
62
63#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
64/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
65 DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
66 so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
67 see sdram_init.c */
68#undef CONFIG_ECC /* enable ECC support */
69#define CONFIG_MV64460_ECC
70
71/* which initialization functions to call for this board */
72#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
wdenkc837dcb2004-01-20 23:12:12 +000073#define CONFIG_BOARD_EARLY_INIT_F
wdenk3a473b22004-01-03 00:43:19 +000074
75#define CFG_BOARD_NAME "DB64460"
76#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)"
77
78/*#define CFG_HUSH_PARSER */
79#undef CFG_HUSH_PARSER
80
81#define CFG_PROMPT_HUSH_PS2 "> "
82
83/*
84 * The following defines let you select what serial you want to use
85 * for your console driver.
86 *
87 * what to do:
88 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
89 * cable onto the second DUART channel, change the CFG_DUART port from 1
90 * to 0 below.
91 *
92 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
93 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
94 */
95
96#define CONFIG_MPSC_PORT 0
97
98/* to change the default ethernet port, use this define (options: 0, 1, 2) */
99#define CONFIG_NET_MULTI
100#define MV_ETH_DEVS 3
101
102/* #undef CONFIG_ETHER_PORT_MII */
103#if 0
104#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
105#else
106#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
107#endif
108#define CONFIG_ZERO_BOOTDELAY_CHECK
109
110
111#undef CONFIG_BOOTARGS
112/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
113
114/* ronen - autoboot using tftp */
115#if (CONFIG_BOOTDELAY >= 0)
116#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
117 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
118 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
119
120#define CONFIG_BOOTARGS "console=ttyS0,115200"
121
122#endif
123
124/* ronen - the u-boot.bin should be ~0x30000 bytes */
125#define CONFIG_EXTRA_ENV_SETTINGS \
126 "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
127cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
128 "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
129cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
130 "bootargs_root=root=/dev/nfs rw\0" \
131 "bootargs_end=:::DB64460:eth0:none \0"\
132 "ethprime=mv_enet0\0"\
133 "standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \
134ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0"
135
136/* --------------------------------------------------------------------------------------------------------------- */
137/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
138
139#define CONFIG_IPADDR 10.2.40.90
140
141#define CONFIG_SERIAL "No. 1"
142#define CONFIG_SERVERIP 10.2.1.126
143#define CONFIG_ROOTPATH /mnt/yellow_dog_mini
144
145
146#define CONFIG_TESTDRAMDATA y
147#define CONFIG_TESTDRAMADDRESS n
148#define CONFIG_TESETDRAMWALK n
149
150/* --------------------------------------------------------------------------------------------------------------- */
151
152#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
153#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
154
155#undef CONFIG_WATCHDOG /* watchdog disabled */
156#undef CONFIG_ALTIVEC /* undef to disable */
157
158#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
159 CONFIG_BOOTP_BOOTFILESIZE)
160
161/* Flash banks JFFS2 should use */
162#define CFG_JFFS2_FIRST_BANK 1
163#define CFG_JFFS2_NUM_BANKS 1
164
165#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
166 | CFG_CMD_ASKENV \
167 | CFG_CMD_I2C \
168 | CFG_CMD_EEPROM \
169 | CFG_CMD_CACHE \
170 | CFG_CMD_JFFS2 \
171 | CFG_CMD_PCI \
172 | CFG_CMD_NET )
173
174/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
175#include <cmd_confdefs.h>
176
177/*
178 * Miscellaneous configurable options
179 */
180#define CFG_I2C_EEPROM_ADDR_LEN 1
181#define CFG_I2C_MULTI_EEPROMS
182#define CFG_I2C_SPEED 40000 /* I2C speed default */
183
184/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
185#define CFG_LONGHELP /* undef to save memory */
186#define CFG_PROMPT "=> " /* Monitor Command Prompt */
187#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
188#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
189#else
190#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
191#endif
192#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
193#define CFG_MAXARGS 16 /* max number of command args */
194#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
195
196/*#define CFG_MEMTEST_START 0x00400000 memtest works on */
197/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
198/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
199
200/*
201#define CFG_DRAM_TEST
202 * DRAM tests
203 * CFG_DRAM_TEST - enables the following tests.
204 *
205 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
206 * Environment variable 'test_dram_data' must be
207 * set to 'y'.
208 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
209 * addressable. Environment variable
210 * 'test_dram_address' must be set to 'y'.
211 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
212 * This test takes about 6 minutes to test 64 MB.
213 * Environment variable 'test_dram_walk' must be
214 * set to 'y'.
215 */
216#define CFG_DRAM_TEST
217#if defined(CFG_DRAM_TEST)
218#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
219/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
220#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
221#define CFG_DRAM_TEST_DATA
222#define CFG_DRAM_TEST_ADDRESS
223#define CFG_DRAM_TEST_WALK
224#endif /* CFG_DRAM_TEST */
225
226#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
227#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
228
229#define CFG_LOAD_ADDR 0x00400000 /* default load address */
230
231#define CFG_HZ 1000 /* decr freq: 1ms ticks */
232/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
233#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
234#define CFG_BUS_CLK CFG_BUS_HZ
235
236#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
237#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
238
239/*ronen - this is the Tclk (MV64460 core) */
240#define CFG_TCLK 133000000
241
242
243#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
244
245#define CFG_750FX_HID0 0x8000c084
246#define CFG_750FX_HID1 0x54800000
247#define CFG_750FX_HID2 0x00000000
248
249/*
250 * Low Level Configuration Settings
251 * (address mappings, register initial values, etc.)
252 * You should know what you are doing if you make changes here.
253 */
254
255/*-----------------------------------------------------------------------
256 * Definitions for initial stack pointer and data area
257 */
258
259/*
260 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
261 * To an unused memory region. The stack will remain in cache until RAM
262 * is initialized
263*/
264#define CFG_INIT_RAM_LOCK
265#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */
266#define CFG_INIT_RAM_END 0x1000
267#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
268#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
269
270#define RELOCATE_INTERNAL_RAM_ADDR
271#ifdef RELOCATE_INTERNAL_RAM_ADDR
272 #define CFG_INTERNAL_RAM_ADDR 0xf8000000
273#endif
274
275/*-----------------------------------------------------------------------
276 * Start addresses for the final memory configuration
277 * (Set up by the startup code)
278 * Please note that CFG_SDRAM_BASE _must_ start at 0
279 */
280#define CFG_SDRAM_BASE 0x00000000
281/* Dummies for BAT 4-7 */
282#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
283#define CFG_SDRAM2_BASE 0x20000000
284#define CFG_SDRAM3_BASE 0x30000000
285#define CFG_SDRAM4_BASE 0x40000000
286#define CFG_FLASH_BASE 0xfff00000
287
288#define CFG_DFL_BOOTCS_BASE 0xff800000
289#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
290
291#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
292#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
293#define PCI0_IO_BASE_BOOTM 0xfd000000
294
295#define CFG_RESET_ADDRESS 0xfff00100
296#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
297#define CFG_MONITOR_BASE CFG_FLASH_BASE
298#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
299
300/* areas to map different things with the GT in physical space */
301#define CFG_DRAM_BANKS 4
302
303/* What to put in the bats. */
304#define CFG_MISC_REGION_BASE 0xf0000000
305
306/* Peripheral Device section */
307
308/*******************************************************/
309/* We have on the db64460 Board : */
310/* GT-Chipset Register Area */
311/* GT-Chipset internal SRAM 256k */
312/* SRAM on external device module */
313/* Real time clock on external device module */
314/* dobble UART on external device module */
315/* Data flash on external device module */
316/* Boot flash on external device module */
317/*******************************************************/
318#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
319#define CFG_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */
320
321/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
322#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
323#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */
324
325#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */
326#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
327#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
328#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */
329
330#define CFG_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */
331#define CFG_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */
332#define CFG_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */
333#define CFG_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */
334/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
335
336/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
337#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
338#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
339#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
340#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
341#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
342
343 /* c 4 a 8 2 4 1 c */
344 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
345 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
346 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
347 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
348
349
350/* ronen - update MPP Control MV64460*/
351#define CFG_MPP_CONTROL_0 0x02222222
352#define CFG_MPP_CONTROL_1 0x11333011
353#define CFG_MPP_CONTROL_2 0x40431111
354#define CFG_MPP_CONTROL_3 0x00000044
355
356/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
357
358
359# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
360 /* gpp[31] gpp[30] gpp[29] gpp[28] */
361 /* gpp[27] gpp[24]*/
362 /* gpp[19:14] */
363
364/* setup new config_value for MV64460 DDR-RAM !! */
365# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
366
367#define CFG_DUART_IO CFG_DEV2_SPACE
368#define CFG_DUART_CHAN 1 /* channel to use for console */
369#define CFG_INIT_CHAN1
370#define CFG_INIT_CHAN2
371
372#define SRAM_BASE CFG_DEV0_SPACE
373#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
374
375
376/*-----------------------------------------------------------------------
377 * PCI stuff
378 *-----------------------------------------------------------------------
379 */
380
381#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
382#define PCI_HOST_FORCE 1 /* configure as pci host */
383#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
384
385#define CONFIG_PCI /* include pci support */
386#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
387#define CONFIG_PCI_PNP /* do pci plug-and-play */
388#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
389
390/* PCI MEMORY MAP section */
391#define CFG_PCI0_MEM_BASE 0x80000000
392#define CFG_PCI0_MEM_SIZE _128M
393#define CFG_PCI1_MEM_BASE 0x88000000
394#define CFG_PCI1_MEM_SIZE _128M
395
396#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
397#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
398
399/* PCI I/O MAP section */
400#define CFG_PCI0_IO_BASE 0xfa000000
401#define CFG_PCI0_IO_SIZE _16M
402#define CFG_PCI1_IO_BASE 0xfb000000
403#define CFG_PCI1_IO_SIZE _16M
404
405#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
406#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
407#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
408#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
409
410#if defined (CONFIG_750CX)
411#define CFG_PCI_IDSEL 0x0
412#else
413#define CFG_PCI_IDSEL 0x30
414#endif
415/*----------------------------------------------------------------------
416 * Initial BAT mappings
417 */
418
419/* NOTES:
420 * 1) GUARDED and WRITE_THRU not allowed in IBATS
421 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
422 */
423
424/* SDRAM */
425#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
426#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
427#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
428#define CFG_DBAT0U CFG_IBAT0U
429
430/* init ram */
431#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
432#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
433#define CFG_DBAT1L CFG_IBAT1L
434#define CFG_DBAT1U CFG_IBAT1U
435
436/* PCI0, PCI1 in one BAT */
437#define CFG_IBAT2L BATL_NO_ACCESS
438#define CFG_IBAT2U CFG_DBAT2U
439#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
440#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
441
442/* GT regs, bootrom, all the devices, PCI I/O */
443#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
444#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
445#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
446#define CFG_DBAT3U CFG_IBAT3U
447
448/* I2C addresses for the two DIMM SPD chips */
449#define DIMM0_I2C_ADDR 0x56
450#define DIMM1_I2C_ADDR 0x54
451
452/*
453 * For booting Linux, the board info and command line data
454 * have to be in the first 8 MB of memory, since this is
455 * the maximum mapped by the Linux kernel during initialization.
456 */
457#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
458
459/*-----------------------------------------------------------------------
460 * FLASH organization
461 */
462#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
463#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
464
465#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
466#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */
467#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */
468
469#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
470#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
471#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
472#define CFG_FLASH_CFI 1
473
474#define CFG_ENV_IS_IN_FLASH 1
475#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
476#define CFG_ENV_SECT_SIZE 0x10000
477#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
478/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
479
480/*-----------------------------------------------------------------------
481 * Cache Configuration
482 */
483#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
484#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
485#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
486#endif
487
488/*-----------------------------------------------------------------------
489 * L2CR setup -- make sure this is right for your board!
490 * look in include/mpc74xx.h for the defines used here
491 */
492
493#define CFG_L2
494
495
496#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
497#define L2_INIT 0
498#else
499
500#define L2_INIT 0
501/*
502#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
503 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
504*/
505#endif
506
507#define L2_ENABLE (L2_INIT | L2CR_L2E)
508
509/*
510 * Internal Definitions
511 *
512 * Boot Flags
513 */
514#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
515#define BOOTFLAG_WARM 0x02 /* Software reboot */
516
517#define CFG_BOARD_ASM_INIT 1
518
519#endif /* __CONFIG_H */