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wdenkaa245092004-06-09 12:47:02 +00001/******************************************************************************
Josh Boyer31773492009-08-07 13:53:20 -04002 * This source code is dual-licensed. You may use it under the terms of the
3 * GNU General Public License version 2, or under the license below.
wdenkaa245092004-06-09 12:47:02 +00004 *
5 * This source code has been made available to you by IBM on an AS-IS
6 * basis. Anyone receiving this source is licensed under IBM
7 * copyrights to use it in any way he or she deems fit, including
8 * copying it, modifying it, compiling it, and redistributing it either
9 * with or without modifications. No license under IBM patents or
10 * patent applications is to be implied by the copyright license.
11 *
12 * Any user of this software should understand that IBM cannot provide
13 * technical support for this software and will not be responsible for
14 * any consequences resulting from the use of this software.
15 *
16 * Any person who transfers this source code or any derivative work
17 * must include the IBM copyright notice, this paragraph, and the
18 * preceding two paragraphs in the transferred software.
19 *
20 * COPYRIGHT I B M CORPORATION 1995
21 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22 *
23 *****************************************************************************/
24#include <config.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020025#include <asm/ppc4xx.h>
wdenkaa245092004-06-09 12:47:02 +000026
27#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
28
29#include <ppc_asm.tmpl>
30#include <ppc_defs.h>
31
32#include <asm/cache.h>
33#include <asm/mmu.h>
34
35#define LI32(reg,val) \
36 addis reg,0,val@h;\
37 ori reg,reg,val@l
38
39#define WDCR_EBC(reg,val) \
40 addi r4,0,reg;\
Stefan Roesed1c3b272009-09-09 16:25:29 +020041 mtdcr EBC0_CFGADDR,r4;\
wdenkaa245092004-06-09 12:47:02 +000042 addis r4,0,val@h;\
43 ori r4,r4,val@l;\
Stefan Roesed1c3b272009-09-09 16:25:29 +020044 mtdcr EBC0_CFGDATA,r4
wdenkaa245092004-06-09 12:47:02 +000045
46#define WDCR_SDRAM(reg,val) \
47 addi r4,0,reg;\
Stefan Roesed1c3b272009-09-09 16:25:29 +020048 mtdcr SDRAM0_CFGADDR,r4;\
wdenkaa245092004-06-09 12:47:02 +000049 addis r4,0,val@h;\
50 ori r4,r4,val@l;\
Stefan Roesed1c3b272009-09-09 16:25:29 +020051 mtdcr SDRAM0_CFGDATA,r4
wdenkaa245092004-06-09 12:47:02 +000052
53/******************************************************************************
54 * Function: ext_bus_cntlr_init
55 *
56 * Description: Configures EBC Controller and a few basic chip selects.
57 *
58 * CS0 is setup to get the Boot Flash out of the addresss range
59 * so that we may setup a stack. CS7 is setup so that we can
60 * access and reset the hardware watchdog.
61 *
62 * IMPORTANT: For pass1 this code must run from
63 * cache since you can not reliably change a peripheral banks
64 * timing register (pbxap) while running code from that bank.
65 * For ex., since we are running from ROM on bank 0, we can NOT
66 * execute the code that modifies bank 0 timings from ROM, so
67 * we run it from cache.
68 *
69 * Notes: Does NOT use the stack.
70 *****************************************************************************/
71 .section ".text"
72 .align 2
73 .globl ext_bus_cntlr_init
74 .type ext_bus_cntlr_init, @function
75ext_bus_cntlr_init:
76 mflr r0
77 /********************************************************************
78 * Prefetch entire ext_bus_cntrl_init function into the icache.
79 * This is necessary because we are going to change the same CS we
80 * are executing from. Otherwise a CPU lockup may occur.
81 *******************************************************************/
82 bl ..getAddr
83..getAddr:
84 mflr r3 /* get address of ..getAddr */
85
86 /* Calculate number of cache lines for this function */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
wdenkaa245092004-06-09 12:47:02 +000088 mtctr r4
89..ebcloop:
90 icbt r0, r3 /* prefetch cache line for addr in r3*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
wdenkaa245092004-06-09 12:47:02 +000092 bdnz ..ebcloop /* continue for $CTR cache lines */
93
94 /********************************************************************
95 * Delay to ensure all accesses to ROM are complete before changing
96 * bank 0 timings. 200usec should be enough.
97 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
98 *******************************************************************/
99 addis r3, 0, 0x0
100 ori r3, r3, 0xA000 /* wait 200us from reset */
101 mtctr r3
102..spinlp:
103 bdnz ..spinlp /* spin loop */
104
105 /********************************************************************
106 * SETUP CPC0_CR0
107 *******************************************************************/
108 LI32(r4, 0x00c01030)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200109 mtdcr CPC0_CR0, r4
wdenkaa245092004-06-09 12:47:02 +0000110
111 /********************************************************************
112 * Setup CPC0_CR1: Change PCIINT signal to PerWE
113 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200114 mfdcr r4, CPC0_CR1
wdenkaa245092004-06-09 12:47:02 +0000115 ori r4, r4, 0x4000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200116 mtdcr CPC0_CR1, r4
wdenkaa245092004-06-09 12:47:02 +0000117
118 /********************************************************************
119 * Setup External Bus Controller (EBC).
120 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200121 WDCR_EBC(EBC0_CFG, 0xd84c0000)
wdenkaa245092004-06-09 12:47:02 +0000122 /********************************************************************
123 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
124 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200125 /*WDCR_EBC(PB1AP, 0x03055200)*/
126 /*WDCR_EBC(PB1AP, 0x04055200)*/
127 WDCR_EBC(PB1AP, 0x08055200)
128 WDCR_EBC(PB0CR, 0xff87a000)
wdenkaa245092004-06-09 12:47:02 +0000129 /********************************************************************
130 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
131 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200132 /*WDCR_EBC(PB3AP, 0x07869200)*/
133 WDCR_EBC(PB3AP, 0x04055200)
134 WDCR_EBC(PB3CR, 0xf081c000)
wdenkaa245092004-06-09 12:47:02 +0000135 /********************************************************************
136 * Memory Bank 1,2,4-7 (Unused) initialization
137 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200138 WDCR_EBC(PB1AP, 0)
139 WDCR_EBC(PB1CR, 0)
140 WDCR_EBC(PB2AP, 0)
141 WDCR_EBC(PB2CR, 0)
142 WDCR_EBC(PB4AP, 0)
143 WDCR_EBC(PB4CR, 0)
144 WDCR_EBC(PB5AP, 0)
145 WDCR_EBC(PB5CR, 0)
146 WDCR_EBC(PB6AP, 0)
147 WDCR_EBC(PB6CR, 0)
148 WDCR_EBC(PB7AP, 0)
149 WDCR_EBC(PB7CR, 0)
wdenkaa245092004-06-09 12:47:02 +0000150
151 /* We are all done */
152 mtlr r0 /* Restore link register */
153 blr /* Return to calling function */
154.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
155/* end ext_bus_cntlr_init() */
156
157/******************************************************************************
158 * Function: sdram_init
159 *
160 * Description: Configures SDRAM memory banks.
161 *
162 * Notes: Does NOT use the stack.
163 *****************************************************************************/
164 .section ".text"
165 .align 2
166 .globl sdram_init
167 .type sdram_init, @function
168sdram_init:
169
170 /*
171 * Disable memory controller to allow
172 * values to be changed.
173 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200174 WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
wdenkaa245092004-06-09 12:47:02 +0000175
176 /*
177 * Configure Memory Banks
178 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200179 WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
180 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
181 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
182 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
wdenkaa245092004-06-09 12:47:02 +0000183
184 /*
185 * Set up SDTR1 (SDRAM Timing Register)
186 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200187 WDCR_SDRAM(SDRAM0_TR, 0x00854009)
wdenkaa245092004-06-09 12:47:02 +0000188
189 /*
190 * Set RTR (Refresh Timing Register)
191 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200192 WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
193 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
wdenkaa245092004-06-09 12:47:02 +0000194
195 /********************************************************************
196 * Delay to ensure 200usec have elapsed since reset. Assume worst
197 * case that the core is running 200Mhz:
198 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
199 *******************************************************************/
200 addis r3, 0, 0x0000
201 ori r3, r3, 0xA000 /* Wait >200us from reset */
202 mtctr r3
203..spinlp2:
204 bdnz ..spinlp2 /* spin loop */
205
206 /********************************************************************
207 * Set memory controller options reg, MCOPT1.
208 *******************************************************************/
Stefan Roese95b602b2009-09-24 13:59:57 +0200209 WDCR_SDRAM(SDRAM0_CFG,0x80800000)
wdenkaa245092004-06-09 12:47:02 +0000210
211..sdri_done:
212 blr /* Return to calling function */
213.Lfe1: .size sdram_init,.Lfe1-sdram_init
214/* end sdram_init() */